Lines Matching +full:usb3 +full:- +full:if

1 # SPDX-License-Identifier: GPL-2.0
4 	tristate "DesignWare USB3 DRD Core Support"
7 	select USB_XHCI_PLATFORM if USB_XHCI_HCD
8 	select USB_ROLE_SWITCH if USB_DWC3_DUAL_ROLE
10 	  Say Y or M here if your system has a Dual Role SuperSpeed
11 	  USB controller based on the DesignWare USB3 IP Core.
13 	  If you choose to build this driver as a dynamically linked
16 if USB_DWC3
22 	  Select this if you have ULPI type PHY attached to your DWC3
27 	default USB_DWC3_DUAL_ROLE if (USB && USB_GADGET)
28 	default USB_DWC3_HOST if (USB && !USB_GADGET)
29 	default USB_DWC3_GADGET if (!USB && USB_GADGET)
66 	  Say 'Y' or 'M' here if you have one such device
74 	  Exynos5800, Exynos5433, Exynos7) ship with one DesignWare Core USB3
75 	  IP inside, say 'Y' or 'M' if you have one such device.
78 	tristate "PCIe-based Platforms"
82 	  If you're using the DesignWare Core IP with a PCIe (but not HAPS
86 	tristate "Synopsys PCIe-based HAPS Platforms"
90 	  If you're using the DesignWare Core IP with a Synopsys PCIe HAPS
99 	  Say 'Y' or 'M' here if you have one such device
110 	  Say 'Y' or 'M' if you have one such device.
118 	  Currently supports Xilinx and Qualcomm DWC USB3 IP.
119 	  Say 'Y' or 'M' if you have one such device.
126 	  STMicroelectronics SoCs with one DesignWare Core USB3 IP
128 	  Say 'Y' or 'M' if you have one such device.
141 	  Say 'Y' or 'M' if you have one such device.
151 	  Say 'Y' or 'M' if you have one such device.
158 	  Support Xilinx SoCs with DesignWare Core USB3 IP.
160 	  Say 'Y' or 'M' if you have one such device.
167 	  Support TI's AM62 platforms with DesignWare Core USB3 IP.
168 	  The Designware Core USB3 IP is programmed to operate in
170 	  Say 'Y' or 'M' here if you have one such device
177 	  Support Cavium Octeon platforms with DesignWare Core USB3 IP.
179 	  Say 'Y' or 'M' here if you have one such device.
187 	  RTK DHC RTD SoCs with DesignWare Core USB3 IP inside,
189 	  or dual-role mode.
190 	  Say 'Y' or 'M' if you have such device.