1 /* SPDX-License-Identifier: GPL-2.0 */
3  * ci.h - common structures, functions, and macros of the ChipIdea driver
5  * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
17 #include <linux/usb/otg-fsm.h>
18 #include <linux/usb/otg.h>
76  * struct ci_hw_ep - endpoint representation
127  * struct ci_role_driver - host/gadget role driver
145  * struct hw_bank - hardware register mapping representation
165  * struct ci_hdrc - chipidea device representation
172  * @is_otg: if the device is otg-capable
173  * @fsm: otg finite state machine
174  * @otg_fsm_hrtimer: hrtimer for otg fsm timers
175  * @hr_timeouts: time out list for active otg fsm timers
176  * @enabled_otg_timer_bits: bits of enabled otg timers
194  * @remote_wakeup: host-enabled remote wakeup
211  * @rev: The revision number for controller
222 	struct usb_otg			otg;  member
266 	enum ci_revision		rev;  member
272 	BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);  in ci_role()
273 	return ci->roles[ci->role];  in ci_role()
281 		return -EINVAL;  in ci_role_start()
283 	if (!ci->roles[role])  in ci_role_start()
284 		return -ENXIO;  in ci_role_start()
286 	ret = ci->roles[role]->start(ci);  in ci_role_start()
290 	ci->role = role;  in ci_role_start()
292 	if (ci->usb_phy) {  in ci_role_start()
294 			usb_phy_set_event(ci->usb_phy, USB_EVENT_ID);  in ci_role_start()
297 			usb_phy_set_event(ci->usb_phy, USB_EVENT_NONE);  in ci_role_start()
305 	enum ci_role role = ci->role;  in ci_role_stop()
310 	ci->role = CI_ROLE_END;  in ci_role_stop()
312 	ci->roles[role]->stop(ci);  in ci_role_stop()
314 	if (ci->usb_phy)  in ci_role_stop()
315 		usb_phy_set_event(ci->usb_phy, USB_EVENT_NONE);  in ci_role_stop()
320 	if (ci->role == CI_ROLE_HOST)  in ci_role_to_usb_role()
322 	else if (ci->role == CI_ROLE_GADGET && ci->vbus_active)  in ci_role_to_usb_role()
348 	return ioread32(ci->hw_bank.abs + offset) & mask;  in hw_read_id_reg()
362 		data = (ioread32(ci->hw_bank.abs + offset) & ~mask)  in hw_write_id_reg()
365 	iowrite32(data, ci->hw_bank.abs + offset);  in hw_write_id_reg()
378 	return ioread32(ci->hw_bank.regmap[reg]) & mask;  in hw_read()
395 	if (ci->imx28_write_fix)  in __hw_write()
412 		data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)  in hw_write()
415 	__hw_write(ci, data, ci->hw_bank.regmap[reg]);  in hw_write()
429 	u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;  in hw_test_and_clear()
431 	__hw_write(ci, val, ci->hw_bank.regmap[reg]);  in hw_test_and_clear()
454  * ci_otg_is_fsm_mode: runtime check if otg controller
455  * is in otg fsm mode.
462 	struct usb_otg_caps *otg_caps = &ci->platdata->ci_otg_caps;  in ci_otg_is_fsm_mode()
464 	return ci->is_otg && ci->roles[CI_ROLE_HOST] &&  in ci_otg_is_fsm_mode()
465 		ci->roles[CI_ROLE_GADGET] && (otg_caps->srp_support ||  in ci_otg_is_fsm_mode()
466 		otg_caps->hnp_support || otg_caps->adp_support);  in ci_otg_is_fsm_mode()