usb/cdns3/cdnsp-gadget.h

1 /* SPDX-License-Identifier: GPL-2.0 */
15 #include <linux/io-64-nonatomic-lo-hi.h>
19 /* Max number slots - only 1 is allowed. */
43  * struct cdnsp_cap_regs - CDNSP Registers.
46  * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
47  * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
48  * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
49  * @hcc_params: HCCPARAMS - Capability Parameters
50  * @db_off: DBOFF - Doorbell array offset
51  * @run_regs_off: RTSOFF - Runtime register space offset
63 	/* Reserved up to (CAPLENGTH - 0x1C) */
67 /* bits 7:0 - how long is the Capabilities register. */
72 /* HCSPARAMS1 - hcs_params1 - bitmasks */
80 /* HCCPARAMS - hcc_params - bitmasks */
81 /* 1: device controller can use 64-bit address pointers. */
83 /* 1: device controller uses 64-byte Device Context structures. */
85 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15. */
92 /* db_off bitmask - bits 0:1 reserved. */
95 /* run_regs_off bitmask - bits 0:4 reserved. */
99  * struct cdnsp_op_regs - Device Controller Operational Registers.
100  * @command: USBCMD - Controller command register.
101  * @status: USBSTS - Controller status register.
102  * @page_size: This indicates the page size that the device controller supports.
103  *             If bit n is set, the controller supports a page size of 2^(n+12),
104  *             up to a 128MB page size. 4K is the minimum page size.
105  * @dnctrl: DNCTRL - Device notification control register.
106  * @cmd_ring: CRP - 64-bit Command Ring Pointer.
107  * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer.
108  * @config_reg: CONFIG - Configure Register
109  * @port_reg_base: PORTSCn - base address for Port Status and Control
123 	/* rsvd: offset 0x20-2F. */
127 	/* rsvd: offset 0x3C-3FF. */
137  * struct cdnsp_port_regs - Port Registers.
138  * @portsc: PORTSC - Port Status and Control Register.
139  * @portpmsc: PORTPMSC - Port Power Managements Status and Control Register.
140  * @portli: PORTLI - Port Link Info register.
152  * These bits are also sticky - meaning they're in the AUX well and they aren't
170 /* USBCMD - USB command - bitmasks. */
171 /* Run/Stop, controller execution - do not write unless controller is halted.*/
174  * Reset device controller - resets internal controller state machine and all
178 /* Event Interrupt Enable - a '1' allows interrupts from the controller. */
181  * Device System Error Interrupt Enable - get out-of-band signal for
189  * Enable Wrap Event - '1' means device controller generates an event
200 /* USBSTS - USB status - bitmasks */
201 /* controller not running - set to 1 when run/stop bit is cleared. */
208 /* event interrupt - clear this prior to clearing any IP flags in IR set.*/
212 /* save state status - '1' means device controller is saving state. */
214 /* restore state status - '1' means controllers is restoring state. */
223 /* CRCR - Command Ring Control Register - cmd_ring bitmasks. */
226 /* stop ring immediately - abort the currently executing command. */
236 /* Command Ring pointer - bit mask for the lower 32 bits. */
239 /* CONFIG - Configure Register - config_reg bitmasks. */
240 /* bits 0:7 - maximum number of device slots enabled. */
245 /* PORTSC - Port Status and Control Register - port_reg_base bitmasks */
253  * Port Link State - bits 5:8
275  * 0 - undefined speed - port hasn't be initialized by a reset yet
276  * 1 - full speed
277  * 2 - Reserved (Low Speed not supported
278  * 3 - high speed
279  * 4 - super speed
280  * 5 - super speed
281  * 6-15 reserved
295 /* Port Link State Write Strobe - set this when changing link state */
301 /* 1: reset change - 1 to 0 transition of PORT_RESET */
304  * port link status change - set on some port link state transitions:
306  * ----------------------------------------------------------------------------
307  * - U3 to Resume		Wakeup signaling from a device
308  * - Resume to Recovery to U0	USB 3.0 device resume
309  * - Resume to U0		USB 2.0 device resume
310  * - U3 to Recovery to U0	Software resume of USB 3.0 device complete
311  * - U3 to U0			Software resume of USB 2.0 device complete
312  * - U2 to U0			L1 resume of USB 2.1 device complete
313  * - U0 to U0			L1 entry rejection by USB 2.1 device
314  * - U0 to disabled		L1 entry error with USB 2.1 device
315  * - Any state to inactive	Error on USB 3.0 port
318 /* Port configure error change - port failed to configure its link partner. */
329 /* PORTPMSCUSB3 - Port Power Management Status and Control - bitmasks. */
337 /* PORTPMSCUSB2 - Port Power Management Status and Control - bitmasks. */
357  * struct cdnsp_intr_reg - Interrupt Register Set.
358  * @irq_pending: IMAN - Interrupt Management Register. Used to enable
360  * @irq_control: IMOD - Interrupt Moderation Register.
366  * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
368  * multiple segments of the same size. The controller places events on the ring
382 /* IMAN - Interrupt Management Register - irq_pending bitmasks l. */
389 /* IMOD - Interrupter Moderation Register - irq_control bitmasks. */
396 /* Counter used to count down the time to the next interrupt - HW use only */
406  * Dequeue ERST Segment Index (DESI) - Segment number (or alias)
410 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced. */
416  * @microframe_index: MFINDEX - current microframe number.
420  * "Software should read and write these registers using only Dword (32 bit)
452 /* Extended capability IDs - ID 0 reserved */
497 			 (readl(&(pdev)->rev_cap->ep_supported) & \
501  * struct cdnsp_rev_cap - controller capabilities.
505  * @tx_buff_size: Tx buffer sizes.
533  *         Bits 0 - 7: Endpoint target.
534  *         Bits 8 - 15: RsvdZ.
535  *         Bits 16 - 31: Stream ID.
549  * @size: Size of the context data.
550  * @ctx_size: context data structure size - 64 or 32 bits.
561 	int size;  member
574  * Slot Context - This assumes the controller uses 32-byte context
575  * structures. If the controller uses 64-byte contexts, there is an additional
594 /* Device speed - values defined by PORTSC Device Speed field - 20:23. */
597 /* Index of the last valid endpoint context in this device context - 27:31. */
600 #define LAST_CTX_TO_EP_NUM(p)	(((p) >> 27) - 1)
609 /* USB device address - assigned by the controller. */
624  * @ep_info2: Information on endpoint type, max packet size, max burst size,
627  * @deq: 64-bit ring dequeue pointer address. If the endpoint only
634  * Endpoint Context - This assumes the controller uses 32-byte context
635  * structures. If the controller uses 64-byte contexts, there is an additional
644 	/* offset 0x14 - 0x1f reserved for controller internal use. */
650  * Endpoint State - bits 0:2:
651  * 0 - disabled
652  * 1 - running
653  * 2 - halted due to halt condition
654  * 3 - stopped
655  * 4 - TRB error
656  * 5-7 - reserved
664 #define GET_EP_CTX_STATE(ctx)	(le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
666 /* Mult - Max number of burst within an interval, in EP companion desc. */
671 /* Interval - period between requests to an endpoint - 125u increments. */
693 /* bit 7 is Device Initiate Disable - for disabling stream selection. */
741  * @stream_ring: 64-bit stream ring address, cycle state, and stream type.
742  * @reserved: offset 0x14 - 0x1f reserved for controller internal use.
749 /* Stream Context Types - bits 3:1 of stream ctx deq ptr. */
793  * struct cdnsp_ep - extended device side representation of USB endpoint.
797  * @number: Endpoint number (1 - 15).
802  * @buffering: Number of on-chip buffers related to endpoint.
803  * @buffering_period; Number of on-chip buffers related to periodic endpoint.
848  * @dev_context_ptr: Array of 64-bit DMA addresses for device contexts.
858  * @buffer: 64-bit buffer address, or immediate data.
874 /* Completion Code - only applicable for some types of TRBs */
918  * @segment_ptr: 64-bit segment pointer.
932  * struct cdnsp_event_cmd - Command completion event TRB.
945 /* Address device - disable SetAddress. */
948 /* Configure Endpoint - Deconfigure. */
969 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB. */
987 /* Port ID - bits 31:24. */
993 /* transfer_len bitmasks - bits 0:16. */
995 /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31). */
1003 /* Interrupter Target - which MSI-X vector to target the completion event at. */
1007  * Total burst count field, Rsvdz on controller with Extended TBC
1013 /* Cycle bit - indicates TRB ownership by driver or driver.*/
1030 /* 0 - NRDY during data stage, 1 - NRDY during status stage (only control). */
1085 /* Transfer Ring No-op (not for the command ring). */
1109 /* Force Header Command - generate a transaction or link management packet. */
1111 /* No-op Command - not for transfer rings. */
1113 /* TRB IDs 24-31 reserved. */
1124 /* MFINDEX Wrap Event - microframe counter wrapped. */
1126 /* TRB IDs 40-47 reserved. */
1129 /* TRB IDs 49-53 reserved. */
1143  * The command ring is 64-byte aligned, so it must also be greater than 16.
1154 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
1155 					((addr) & (TRB_MAX_BUFF_SIZE - 1)))
1158  * struct cdnsp_segment - segment related data.
1171 	/* Max packet sized bounce buffer for td-fragmant alignment */
1179  * struct cdnsp_td - Transfer Descriptor object.
1180  * @td_list: Used for binding TD with ep_ring->td_list.
1187  * @drbl - TD has been added to HW scheduler - only for stream capable
1202  * struct cdnsp_dequeue_state - New dequeue pointer for Transfer Ring.
1226  * struct cdnsp_ring - information describing transfer, command or event ring.
1239  * @stream_active: Stream is active - PRIME packet has been detected.
1245  * @type: Ring type - event, transfer, or command ring.
1246  * @last_td_was_short - TD is short TD.
1272  * struct cdnsp_erst_entry - even ring segment table entry object.
1273  * @seg_addr: 64-bit event ring segment address.
1284  * struct cdnsp_erst - even ring segment table for event ring.
1296  * struct cdnsp_request - extended device side representation of usb_request
1324  * struct cdnsp_port - holds information about detected ports.
1344  * struct cdnsp_device - represent USB device.
1358  * @hcs_params1: Cached register copies of read-only HCSPARAMS1
1359  * @hcc_params: Cached register copies of read-only HCCPARAMS1
1366  * @setup_speed - Speed detected for current SETUP packet.
1388  * @usb2_port - Port USB 2.0.
1389  * @usb3_port - Port USB 3.0.
1390  * @active_port - Current selected Port.
1410 	/* Cached register copies of read-only CDNSP data */
1469  * Registers with 64-bit address pointers should be written to with
1470  * dword accesses by writing the low dword first (ptr[0]), then the high dword
1471  * (ptr[1]) second. controller implementations that do not support 64-bit
1472  * address pointers will ignore the high dword, and write order is irrelevant.
1581  * next_request - gets the next request on the given list