150 			       UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp);  in ufs_mtk_cfg_unipro_cg()
156 			       UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp);  in ufs_mtk_cfg_unipro_cg()
159 			       UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), &tmp);  in ufs_mtk_cfg_unipro_cg()
162 			       UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), tmp);  in ufs_mtk_cfg_unipro_cg()
165 			       UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp);  in ufs_mtk_cfg_unipro_cg()
170 			       UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp);  in ufs_mtk_cfg_unipro_cg()
173 			       UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), &tmp);  in ufs_mtk_cfg_unipro_cg()
176 			       UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), tmp);  in ufs_mtk_cfg_unipro_cg()
793 	ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_LOCALVERINFO), &ver);  in ufs_mtk_get_controller_version()
1102 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), true);  in ufs_mtk_pre_pwr_change()
1103 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), UFS_HS_G1);  in ufs_mtk_pre_pwr_change()
1105 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), true);  in ufs_mtk_pre_pwr_change()
1106 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), UFS_HS_G1);  in ufs_mtk_pre_pwr_change()
1108 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),  in ufs_mtk_pre_pwr_change()
1110 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),  in ufs_mtk_pre_pwr_change()
1112 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),  in ufs_mtk_pre_pwr_change()
1115 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXHSADAPTTYPE),  in ufs_mtk_pre_pwr_change()
1199 	ret = ufshcd_dme_get(hba, UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp);  in ufs_mtk_pre_link()
1205 	ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp);  in ufs_mtk_pre_link()
1510 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 6);  in ufs_mtk_apply_dev_quirks()
1511 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 10);  in ufs_mtk_apply_dev_quirks()
1521 			ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 8);  in ufs_mtk_apply_dev_quirks()