Lines Matching refs:UIC_ARG_MIB_SEL

247 		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD, i),  in exynosauto_ufs_pre_link()
249 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD_EN, i), 0x0); in exynosauto_ufs_pre_link()
251 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE2, i), in exynosauto_ufs_pre_link()
253 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE1, i), in exynosauto_ufs_pre_link()
255 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE0, i), in exynosauto_ufs_pre_link()
258 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, i), 0x79); in exynosauto_ufs_pre_link()
259 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x84, i), 0x1); in exynosauto_ufs_pre_link()
260 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, i), 0xf6); in exynosauto_ufs_pre_link()
264 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD, i), in exynosauto_ufs_pre_link()
267 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD_EN, i), in exynosauto_ufs_pre_link()
270 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE2, i), in exynosauto_ufs_pre_link()
272 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE1, i), in exynosauto_ufs_pre_link()
274 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE0, i), in exynosauto_ufs_pre_link()
278 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x04, i), 0x1); in exynosauto_ufs_pre_link()
326 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x297, i), 0x17); in exynos7_ufs_pre_link()
328 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x362, i), 0xff); in exynos7_ufs_pre_link()
329 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x363, i), 0x00); in exynos7_ufs_pre_link()
335 UIC_ARG_MIB_SEL(TX_HIBERN8_CONTROL, i), 0x0); in exynos7_ufs_pre_link()
356 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x28b, i), 0x83); in exynos7_ufs_post_link()
357 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x29a, i), 0x07); in exynos7_ufs_post_link()
358 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x277, i), in exynos7_ufs_post_link()
587 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_FILLER_ENABLE, i), in exynos_ufs_config_phy_time_attr()
589 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_LINERESET_VAL, i), in exynos_ufs_config_phy_time_attr()
591 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_07_00, i), in exynos_ufs_config_phy_time_attr()
593 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_15_08, i), in exynos_ufs_config_phy_time_attr()
595 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_GRAN_NVAL_07_00, i), in exynos_ufs_config_phy_time_attr()
597 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_GRAN_NVAL_10_08, i), in exynos_ufs_config_phy_time_attr()
599 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_OV_SLEEP_CNT_TIMER, i), in exynos_ufs_config_phy_time_attr()
601 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_OV_STALL_CNT_TIMER, i), in exynos_ufs_config_phy_time_attr()
606 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_LINERESET_P_VAL, i), in exynos_ufs_config_phy_time_attr()
608 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HIGH_Z_CNT_07_00, i), in exynos_ufs_config_phy_time_attr()
610 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HIGH_Z_CNT_11_08, i), in exynos_ufs_config_phy_time_attr()
612 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_BASE_NVAL_07_00, i), in exynos_ufs_config_phy_time_attr()
614 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_BASE_NVAL_15_08, i), in exynos_ufs_config_phy_time_attr()
616 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_GRAN_NVAL_07_00, i), in exynos_ufs_config_phy_time_attr()
618 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_GRAN_NVAL_10_08, i), in exynos_ufs_config_phy_time_attr()
620 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_OV_SLEEP_CNT_TIMER, i), in exynos_ufs_config_phy_time_attr()
623 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_MIN_ACTIVATETIME, i), in exynos_ufs_config_phy_time_attr()
640 UIC_ARG_MIB_SEL(RX_HS_G1_SYNC_LENGTH_CAP, i), in exynos_ufs_config_phy_cap_attr()
643 UIC_ARG_MIB_SEL(RX_HS_G2_SYNC_LENGTH_CAP, i), in exynos_ufs_config_phy_cap_attr()
646 UIC_ARG_MIB_SEL(RX_HS_G3_SYNC_LENGTH_CAP, i), in exynos_ufs_config_phy_cap_attr()
649 UIC_ARG_MIB_SEL(RX_HS_G1_PREP_LENGTH_CAP, i), in exynos_ufs_config_phy_cap_attr()
652 UIC_ARG_MIB_SEL(RX_HS_G2_PREP_LENGTH_CAP, i), in exynos_ufs_config_phy_cap_attr()
655 UIC_ARG_MIB_SEL(RX_HS_G3_PREP_LENGTH_CAP, i), in exynos_ufs_config_phy_cap_attr()
662 UIC_ARG_MIB_SEL(RX_ADV_GRANULARITY_CAP, i), 0); in exynos_ufs_config_phy_cap_attr()
666 UIC_ARG_MIB_SEL( in exynos_ufs_config_phy_cap_attr()
672 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAP, i), in exynos_ufs_config_phy_cap_attr()
679 UIC_ARG_MIB_SEL(RX_ADV_GRANULARITY_CAP, in exynos_ufs_config_phy_cap_attr()
685 UIC_ARG_MIB_SEL( in exynos_ufs_config_phy_cap_attr()
691 UIC_ARG_MIB_SEL(RX_ADV_HIBERN8TIME_CAP, in exynos_ufs_config_phy_cap_attr()
769 UIC_ARG_MIB_SEL(RX_SYNC_MASK_LENGTH, i), mask); in exynos_ufs_config_sync_pattern_mask()
1745 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xAA, i), in fsd_ufs_pre_link()
1747 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8F, i), 0x3F); in fsd_ufs_pre_link()
1751 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x12, i), in fsd_ufs_pre_link()
1753 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x5C, i), 0x38); in fsd_ufs_pre_link()
1754 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0F, i), 0x0); in fsd_ufs_pre_link()
1755 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x65, i), 0x1); in fsd_ufs_pre_link()
1756 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x69, i), 0x1); in fsd_ufs_pre_link()
1757 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x21, i), 0x0); in fsd_ufs_pre_link()
1758 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x22, i), 0x0); in fsd_ufs_pre_link()
1781 ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0x8F, 4), in fsd_ufs_post_link()
1800 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x35, i), 0x05); in fsd_ufs_post_link()
1801 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x73, i), 0x01); in fsd_ufs_post_link()
1802 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x41, i), 0x02); in fsd_ufs_post_link()
1803 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x42, i), 0xAC); in fsd_ufs_post_link()
1850 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD, i), in gs101_ufs_pre_link()
1852 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD_EN, i), 0x0); in gs101_ufs_pre_link()
1853 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE2, i), in gs101_ufs_pre_link()
1855 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE1, i), in gs101_ufs_pre_link()
1857 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE0, i), in gs101_ufs_pre_link()
1859 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, i), 0x69); in gs101_ufs_pre_link()
1860 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x84, i), 0x1); in gs101_ufs_pre_link()
1861 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, i), 0xf6); in gs101_ufs_pre_link()
1865 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD, i), in gs101_ufs_pre_link()
1867 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD_EN, i), in gs101_ufs_pre_link()
1869 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE2, i), in gs101_ufs_pre_link()
1871 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE1, i), in gs101_ufs_pre_link()
1873 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE0, i), in gs101_ufs_pre_link()
1875 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x04, i), 1); in gs101_ufs_pre_link()
1876 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x7F, i), 0); in gs101_ufs_pre_link()