397 	wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
399 	wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
404 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
1327 	wr_reg16(info, TCR, value);  in set_break()
2064 	wr_reg16(info, SSR, status); /* clear pending */  in isr_serial()
2204 		wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */  in isr_txeom()
2205 		wr_reg16(info, TCR, val); /* clear reset bit */  in isr_txeom()
2634 			wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);  in rx_enable()
2687 			wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));  in wait_mgsl_event()
2750 			wr_reg16(info, SCR,  in wait_mgsl_event()
2786 	wr_reg16(info, TCR, val);  in set_interface()
3755 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)  in wr_reg16()  function
3804 	wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));  in enable_loopback()
3843 		wr_reg16(info, BDR, (unsigned short)div);  in set_rate()
3853 	wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */  in rx_stop()
3854 	wr_reg16(info, RCR, val);                  /* clear reset bit */  in rx_stop()
3859 	wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);  in rx_stop()
3874 	wr_reg16(info, SSR, IRQ_RXOVER);  in rx_start()
3878 	wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */  in rx_start()
3879 	wr_reg16(info, RCR, val);                  /* clear reset bit */  in rx_start()
3886 		wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));  in rx_start()
3894 		wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));  in rx_start()
3910 	wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));  in rx_start()
3919 		wr_reg16(info, TCR,  in tx_start()
3940 			wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));  in tx_start()
3945 			wr_reg16(info, SSR, IRQ_TXIDLE);  in tx_start()
3964 	wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */  in tx_stop()
3969 	wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));  in tx_stop()
4050 	wr_reg16(info, TCR, val);  in async_mode()
4087 	wr_reg16(info, RCR, val);  in async_mode()
4133 	wr_reg16(info, SCR, val);  in async_mode()
4212 	wr_reg16(info, TCR, val);  in sync_mode()
4275 	wr_reg16(info, RCR, val);  in sync_mode()
4326 		wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));  in sync_mode()
4357 	wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);  in sync_mode()
4384 	wr_reg16(info, TCR, tcr);  in tx_set_idle()
4846 		wr_reg16(info, TIR, patterns[i]);  in register_test()
4847 		wr_reg16(info, BDR, patterns[(i+1)%count]);  in register_test()
4874 	wr_reg16(info, TCR,  in irq_test()
4878 	wr_reg16(info, TDR, 0);  in irq_test()