tty/serial/zs.h

1 /* SPDX-License-Identifier: GPL-2.0 */
38  * Per-SCC state for locking and the interrupt handler.
53 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
86 #define RES_Rx_CRC	0x40	/* Reset Rx CRC Checker */
90 /* Write Register 1 (Tx/Rx/Ext Int Enable and WAIT/DMA Commands) */
95 #define RxINT_DISAB	0	/* Rx Int Disable */
96 #define RxINT_FCERR	0x8	/* Rx Int on First Character Only or Error */
97 #define RxINT_ALL	0x10	/* Int on all Rx Characters or error */
108 #define RxENABLE	0x1	/* Rx Enable */
110 #define ADD_SM		0x4	/* Address Search Mode (SDLC) */
111 #define RxCRC_ENAB	0x8	/* Rx CRC Enable */
112 #define ENT_HM		0x10	/* Enter Hunt Mode */
114 #define Rx5		0x0	/* Rx 5 Bits/Character */
115 #define Rx7		0x40	/* Rx 7 Bits/Character */
116 #define Rx6		0x80	/* Rx 6 Bits/Character */
117 #define Rx8		0xc0	/* Rx 8 Bits/Character */
132 #define SDLC		0x20	/* SDLC Mode (01111110 Sync Flag) */
133 #define EXTSYNC		0x30	/* External Sync Mode */
135 #define X1CLK		0x0	/* x1 clock mode */
136 #define X16CLK		0x40	/* x16 clock mode */
137 #define X32CLK		0x80	/* x32 clock mode */
138 #define X64CLK		0xc0	/* x64 clock mode */
144 #define SDLC_CRC	0x4	/* SDLC/CRC-16 */
154 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
156 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
174 #define LOOPMODE	2	/* SDLC Loop mode */
178 #define NRZ		0	/* NRZ mode */
179 #define NRZI		0x20	/* NRZI mode */
184 /* Write Register 11 (Clock Mode Control) */
210 #define SEARCH		0x20	/* Enter search mode */
215 #define SFMM		0xc0	/* Set FM mode */
216 #define SNRZI		0xe0	/* Set NRZI mode */
229 #define Rx_CH_AV	0x1	/* Rx Character Available */
240 /* Residue Data for 8 Rx bits/char programmed */
249 /* Special Rx Condition Interrupts */
251 #define Rx_OVR		0x20	/* Rx Overrun Error */
255 /* Read Register 2 (Interrupt Vector (WR2) -- channel A).  */
257 /* Read Register 2 (Modified Interrupt Vector -- channel B).  */
259 /* Read Register 3 (Interrupt Pending Bits -- channel A only).  */
262 #define CHBRxIP		0x4	/* Channel B Rx IP */
265 #define CHARxIP		0x20	/* Channel A Rx IP */