tty/serial/zs.h

1 /* SPDX-License-Identifier: GPL-2.0 */
29 	int		tx_stopped;		/* Output is suspended.  */
38  * Per-SCC state for locking and the interrupt handler.
53 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
79 #define RES_EXT_INT	0x10	/* Reset Ext. Status Interrupts */
81 #define RES_RxINT_FC	0x20	/* Reset RxINT on First Character */
82 #define RES_Tx_P	0x28	/* Reset TxINT Pending */
83 #define ERR_RES		0x30	/* Error Reset */
84 #define RES_H_IUS	0x38	/* Reset highest IUS */
86 #define RES_Rx_CRC	0x40	/* Reset Rx CRC Checker */
87 #define RES_Tx_CRC	0x80	/* Reset Tx CRC Checker */
88 #define RES_EOM_L	0xC0	/* Reset EOM latch */
90 /* Write Register 1 (Tx/Rx/Ext Int Enable and WAIT/DMA Commands) */
91 #define EXT_INT_ENAB	0x1	/* Ext Int Enable */
144 #define SDLC_CRC	0x4	/* SDLC/CRC-16 */
154 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
156 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
167 #define NORESET		0	/* No reset on write to R9 */
168 #define CHRB		0x40	/* Reset channel B */
169 #define CHRA		0x80	/* Reset channel A */
170 #define FHWRES		0xc0	/* Force hardware reset */
185 #define TRxCXT		0	/* TRxC = Xtal output */
187 #define TRxCBR		2	/* TRxC = BR Generator Output */
188 #define TRxCDP		3	/* TRxC = DPLL output */
192 #define TCBR		0x10	/* Transmit clock = BR Generator output */
193 #define TCDPLL		0x18	/* Transmit clock = DPLL output */
196 #define RCBR		0x40	/* Receive clock = BR Generator output */
197 #define RCDPLL		0x60	/* Receive clock = DPLL output */
211 #define RMC		0x40	/* Reset missing clock */
255 /* Read Register 2 (Interrupt Vector (WR2) -- channel A).  */
257 /* Read Register 2 (Modified Interrupt Vector -- channel B).  */
259 /* Read Register 3 (Interrupt Pending Bits -- channel A only).  */
260 #define CHBEXT		0x1	/* Channel B Ext/Stat IP */
263 #define CHAEXT		0x8	/* Channel A Ext/Stat IP */