tty/serial/sunzilog.h

1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
58 #define	RES_Tx_CRC	0x80	/* Reset Tx CRC Checker */
63 #define	EXT_INT_ENAB	0x1	/* Ext Int Enable */
64 #define	TxINT_ENAB	0x2	/* Tx Int Enable */
75 #define	WT_RDY_ENAB	0x80	/* Wait/Ready Enable */
81 #define	RxENAB  	0x1	/* Rx Enable */
84 #define	RxCRC_ENAB	0x8	/* Rx CRC Enable */
95 #define	PAR_ENAB	0x1	/* Parity Enable */
98 #define	SYNC_ENAB	0	/* Sync Modes Enable */
116 #define	TxCRC_ENAB	0x1	/* Tx CRC Enable */
118 #define	SDLC_CRC	0x4	/* SDLC/CRC-16 */
119 #define	TxENAB		0x8	/* Tx Enable */
121 #define	Tx5		0x0	/* Tx 5 bits (or less)/character */
122 #define	Tx7		0x20	/* Tx 7 bits/character */
123 #define	Tx6		0x40	/* Tx 6 bits/character */
124 #define	Tx8		0x60	/* Tx 8 bits/character */
128 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
130 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
133 #define	AUTO_TxFLAG	1	/* Automatic Tx SDLC Flag */
139 #define	EXT_RD_EN	0x40	/* Extended read register enable */
147 #define	MIE	8	/* Master Interrupt Enable */
188 #define	BRENAB 	1	/* Baud rate generator enable */
202 #define	WR7pEN	1	/* WR7' Enable (ESCC only) */
204 #define	FIFOEN	4	/* FIFO Enable (ESCC only) */
208 #define	TxUIE	0x40	/* Tx Underrun/EOM IE */
215 #define	Tx_BUF_EMP	0x4	/* Tx Buffer empty */
219 #define	TxEOM		0x40	/* Tx underrun */
239 /* Read Register 2 (channel b only) - Interrupt vector */
252 #define	CHBTxIP	0x2		/* Channel B Tx IP */
255 #define	CHATxIP	0x10		/* Channel A Tx IP */
277 #define ZS_CLEARERR(channel)    do { sbus_writeb(ERR_RES, &channel->control); \
280 #define ZS_CLEARSTAT(channel)   do { sbus_writeb(RES_EXT_INT, &channel->control); \
283 #define ZS_CLEARFIFO(channel)   do { sbus_readb(&channel->data); \
285 				     sbus_readb(&channel->data); \
287 				     sbus_readb(&channel->data); \