Lines Matching +full:pin +full:- +full:count

1 /* SPDX-License-Identifier: GPL-2.0 */
20 SCFDR, /* FIFO Data Count Register */
24 SCTFDR, /* Transmit FIFO Data Count Register */
25 SCRFDR, /* Receive FIFO Data Count Register */
32 HSRTRGR, /* Rx FIFO Data Count Trigger Register */
33 HSTTRGR, /* Tx FIFO Data Count Trigger Register */
42 #define SCSMR_CSYNC BIT(7) /* - Clocked synchronous mode */
43 #define SCSMR_ASYNC 0 /* - Asynchronous mode */
44 #define SCSMR_CHR BIT(6) /* 7-bit Character Length */
69 /* Serial Control Register, HSCIF-only bits */
111 #define SCFCR_RTRG1 BIT(7) /* Receive FIFO Data Count Trigger */
113 #define SCFCR_TTRG1 BIT(5) /* Transmit FIFO Data Count Trigger */
125 #define SCSPTR_RTSIO BIT(7) /* Serial Port RTS# Pin Input/Output */
126 #define SCSPTR_RTSDT BIT(6) /* Serial Port RTS# Pin Data */
127 #define SCSPTR_CTSIO BIT(5) /* Serial Port CTS# Pin Input/Output */
128 #define SCSPTR_CTSDT BIT(4) /* Serial Port CTS# Pin Data */
129 #define SCSPTR_SCKIO BIT(3) /* Serial Port Clock Pin Input/Output */
130 #define SCSPTR_SCKDT BIT(2) /* Serial Port Clock Pin Data */
142 #define SCPCR_RTSC BIT(4) /* Serial Port RTS# Pin / Output Pin */
143 #define SCPCR_CTSC BIT(3) /* Serial Port CTS# Pin / Input Pin */
144 #define SCPCR_SCKC BIT(2) /* Serial Port SCK Pin / Output Pin */
145 #define SCPCR_RXDC BIT(1) /* Serial Port RXD Pin / Input Pin */
146 #define SCPCR_TXDC BIT(0) /* Serial Port TXD Pin / Output Pin */
149 #define SCPDR_RTSD BIT(4) /* Serial Port RTS# Output Pin Data */
150 #define SCPDR_CTSD BIT(3) /* Serial Port CTS# Input Pin Data */
151 #define SCPDR_SCKD BIT(2) /* Serial Port SCK Output Pin Data */
152 #define SCPDR_RXDD BIT(1) /* Serial Port RXD Input Pin Data */
153 #define SCPDR_TXDD BIT(0) /* Serial Port TXD Output Pin Data */
164 #define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
165 #define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_DR | SCIF_RDF)
166 #define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
167 #define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
168 #define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
169 #define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
171 #define SCxSR_ERRORS(port) (to_sci_port(port)->params->error_mask)
174 (((port)->type == PORT_SCI) ? SCI_RDxF_CLEAR : SCIF_RDxF_CLEAR)
176 (to_sci_port(port)->params->error_clear)
178 (((port)->type == PORT_SCI) ? SCI_TDxE_CLEAR : SCIF_TDxE_CLEAR)
180 (((port)->type == PORT_SCI) ? SCI_BREAK_CLEAR : SCIF_BREAK_CLEAR)