Lines Matching +full:ctrl +full:- +full:gpios
1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 * Copyright (C) 2002 - 2011 Paul Mundt
9 * based off of the old drivers/char/sh-sci.c by:
26 #include <linux/dma-mapping.h>
58 #include "sh-sci.h"
60 /* Offsets into the sci_port->irqs array */
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
88 #define SCI_SR(x) BIT((x) - 1)
89 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
95 #define min_sr(_port) ffs((_port)->sampling_rate_mask)
96 #define max_sr(_port) fls((_port)->sampling_rate_mask)
100 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
101 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
125 struct mctrl_gpios *gpios; member
268 * Common SH-2(A) SCIF definitions for ports with FIFO data
323 * - Break out of interrupts are different: ERI, BRI, RXI, TXI, TEI, DRI,
324 * TEI-DRI, RXI-EDGE and TXI-EDGE.
325 * - SCSMR register does not have CM bit (BIT(7)) ie it does not support synchronous mode.
326 * - SCFCR register does not have SCFCR_MCE bit.
327 * - SCSPTR register has only bits SCSPTR_SPB2DT and SCSPTR_SPB2IO.
352 * Common SH-3 SCIF definitions.
374 * Common SH-4(A) SCIF(B) definitions.
454 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
478 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
505 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
528 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
540 if (reg->size == 8) in sci_serial_in()
541 return ioread8(p->membase + (reg->offset << p->regshift)); in sci_serial_in()
542 else if (reg->size == 16) in sci_serial_in()
543 return ioread16(p->membase + (reg->offset << p->regshift)); in sci_serial_in()
554 if (reg->size == 8) in sci_serial_out()
555 iowrite8(value, p->membase + (reg->offset << p->regshift)); in sci_serial_out()
556 else if (reg->size == 16) in sci_serial_out()
557 iowrite16(value, p->membase + (reg->offset << p->regshift)); in sci_serial_out()
566 if (!sci_port->port.dev) in sci_port_enable()
569 pm_runtime_get_sync(sci_port->port.dev); in sci_port_enable()
572 clk_prepare_enable(sci_port->clks[i]); in sci_port_enable()
573 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]); in sci_port_enable()
575 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK]; in sci_port_enable()
582 if (!sci_port->port.dev) in sci_port_disable()
585 for (i = SCI_NUM_CLKS; i-- > 0; ) in sci_port_disable()
586 clk_disable_unprepare(sci_port->clks[i]); in sci_port_disable()
588 pm_runtime_put_sync(sci_port->port.dev); in sci_port_disable()
595 * special-casing the port type, we check the port initialization in port_rx_irq_mask()
600 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); in port_rx_irq_mask()
606 unsigned short ctrl; in sci_start_tx() local
609 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { in sci_start_tx()
611 if (s->chan_tx) in sci_start_tx()
619 if (s->chan_tx && !kfifo_is_empty(&port->state->port.xmit_fifo) && in sci_start_tx()
620 dma_submit_error(s->cookie_tx)) { in sci_start_tx()
621 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) in sci_start_tx()
623 disable_irq_nosync(s->irqs[SCIx_TXI_IRQ]); in sci_start_tx()
625 s->cookie_tx = 0; in sci_start_tx()
626 schedule_work(&s->work_tx); in sci_start_tx()
630 if (!s->chan_tx || s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE || in sci_start_tx()
631 port->type == PORT_SCIFA || port->type == PORT_SCIFB) { in sci_start_tx()
633 ctrl = sci_serial_in(port, SCSCR); in sci_start_tx()
640 if (port->type == PORT_SCI) in sci_start_tx()
641 ctrl |= SCSCR_TE; in sci_start_tx()
643 sci_serial_out(port, SCSCR, ctrl | SCSCR_TIE); in sci_start_tx()
649 unsigned short ctrl; in sci_stop_tx() local
652 ctrl = sci_serial_in(port, SCSCR); in sci_stop_tx()
654 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) in sci_stop_tx()
655 ctrl &= ~SCSCR_TDRQE; in sci_stop_tx()
657 ctrl &= ~SCSCR_TIE; in sci_stop_tx()
659 sci_serial_out(port, SCSCR, ctrl); in sci_stop_tx()
662 if (to_sci_port(port)->chan_tx && in sci_stop_tx()
663 !dma_submit_error(to_sci_port(port)->cookie_tx)) { in sci_stop_tx()
664 dmaengine_terminate_async(to_sci_port(port)->chan_tx); in sci_stop_tx()
665 to_sci_port(port)->cookie_tx = -EINVAL; in sci_stop_tx()
672 unsigned short ctrl; in sci_start_rx() local
674 ctrl = sci_serial_in(port, SCSCR) | port_rx_irq_mask(port); in sci_start_rx()
676 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) in sci_start_rx()
677 ctrl &= ~SCSCR_RDRQE; in sci_start_rx()
679 sci_serial_out(port, SCSCR, ctrl); in sci_start_rx()
684 unsigned short ctrl; in sci_stop_rx() local
686 ctrl = sci_serial_in(port, SCSCR); in sci_stop_rx()
688 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) in sci_stop_rx()
689 ctrl &= ~SCSCR_RDRQE; in sci_stop_rx()
691 ctrl &= ~port_rx_irq_mask(port); in sci_stop_rx()
693 sci_serial_out(port, SCSCR, ctrl); in sci_stop_rx()
698 if (port->type == PORT_SCI) { in sci_clear_SCxSR()
701 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) { in sci_clear_SCxSR()
761 * Use port-specific handler if provided. in sci_init_pins()
763 if (s->cfg->ops && s->cfg->ops->init_pins) { in sci_init_pins()
764 s->cfg->ops->init_pins(port, cflag); in sci_init_pins()
768 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { in sci_init_pins()
770 u16 ctrl = sci_serial_in(port, SCPCR); in sci_init_pins() local
773 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC); in sci_init_pins()
774 if (to_sci_port(port)->has_rtscts) { in sci_init_pins()
776 if (!(port->mctrl & TIOCM_RTS)) { in sci_init_pins()
777 ctrl |= SCPCR_RTSC; in sci_init_pins()
779 } else if (!s->autorts) { in sci_init_pins()
780 ctrl |= SCPCR_RTSC; in sci_init_pins()
784 ctrl &= ~SCPCR_RTSC; in sci_init_pins()
787 ctrl &= ~SCPCR_CTSC; in sci_init_pins()
790 sci_serial_out(port, SCPCR, ctrl); in sci_init_pins()
791 } else if (sci_getreg(port, SCSPTR)->size && s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE) { in sci_init_pins()
796 if (!(port->mctrl & TIOCM_RTS)) in sci_init_pins()
798 else if (!s->autorts) in sci_init_pins()
809 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; in sci_txfill()
813 if (reg->size) in sci_txfill()
817 if (reg->size) in sci_txfill()
825 return port->fifosize - sci_txfill(port); in sci_txroom()
831 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; in sci_rxfill()
835 if (reg->size) in sci_rxfill()
839 if (reg->size) in sci_rxfill()
851 struct tty_port *tport = &port->state->port; in sci_transmit_chars()
854 unsigned short ctrl; in sci_transmit_chars() local
859 ctrl = sci_serial_in(port, SCSCR); in sci_transmit_chars()
860 if (kfifo_is_empty(&tport->xmit_fifo)) in sci_transmit_chars()
861 ctrl &= ~SCSCR_TIE; in sci_transmit_chars()
863 ctrl |= SCSCR_TIE; in sci_transmit_chars()
864 sci_serial_out(port, SCSCR, ctrl); in sci_transmit_chars()
873 if (port->x_char) { in sci_transmit_chars()
874 c = port->x_char; in sci_transmit_chars()
875 port->x_char = 0; in sci_transmit_chars()
876 } else if (stopped || !kfifo_get(&tport->xmit_fifo, &c)) { in sci_transmit_chars()
877 if (port->type == PORT_SCI && in sci_transmit_chars()
878 kfifo_is_empty(&tport->xmit_fifo)) { in sci_transmit_chars()
879 ctrl = sci_serial_in(port, SCSCR); in sci_transmit_chars()
880 ctrl &= ~SCSCR_TE; in sci_transmit_chars()
881 sci_serial_out(port, SCSCR, ctrl); in sci_transmit_chars()
889 port->icount.tx++; in sci_transmit_chars()
890 } while (--count > 0); in sci_transmit_chars()
894 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in sci_transmit_chars()
896 if (kfifo_is_empty(&tport->xmit_fifo)) { in sci_transmit_chars()
897 if (port->type == PORT_SCI) { in sci_transmit_chars()
898 ctrl = sci_serial_in(port, SCSCR); in sci_transmit_chars()
899 ctrl &= ~SCSCR_TIE; in sci_transmit_chars()
900 ctrl |= SCSCR_TEIE; in sci_transmit_chars()
901 sci_serial_out(port, SCSCR, ctrl); in sci_transmit_chars()
910 struct tty_port *tport = &port->state->port; in sci_receive_chars()
927 if (port->type == PORT_SCI) { in sci_receive_chars()
937 if (port->type == PORT_SCIF || in sci_receive_chars()
938 port->type == PORT_HSCIF) { in sci_receive_chars()
946 count--; i--; in sci_receive_chars()
953 port->icount.frame++; in sci_receive_chars()
956 port->icount.parity++; in sci_receive_chars()
968 port->icount.rx += count; in sci_receive_chars()
986 struct tty_port *tport = &port->state->port; in sci_handle_errors()
990 if (status & s->params->overrun_mask) { in sci_handle_errors()
991 port->icount.overrun++; in sci_handle_errors()
1000 port->icount.frame++; in sci_handle_errors()
1008 port->icount.parity++; in sci_handle_errors()
1022 struct tty_port *tport = &port->state->port; in sci_handle_fifo_overrun()
1028 reg = sci_getreg(port, s->params->overrun_reg); in sci_handle_fifo_overrun()
1029 if (!reg->size) in sci_handle_fifo_overrun()
1032 status = sci_serial_in(port, s->params->overrun_reg); in sci_handle_fifo_overrun()
1033 if (status & s->params->overrun_mask) { in sci_handle_fifo_overrun()
1034 status &= ~s->params->overrun_mask; in sci_handle_fifo_overrun()
1035 sci_serial_out(port, s->params->overrun_reg, status); in sci_handle_fifo_overrun()
1037 port->icount.overrun++; in sci_handle_fifo_overrun()
1051 struct tty_port *tport = &port->state->port; in sci_handle_breaks()
1057 port->icount.brk++; in sci_handle_breaks()
1076 if (rx_trig >= port->fifosize) in scif_set_rtrg()
1077 rx_trig = port->fifosize - 1; in scif_set_rtrg()
1082 if (sci_getreg(port, HSRTRGR)->size) { in scif_set_rtrg()
1087 switch (port->type) { in scif_set_rtrg()
1133 if (sci_getreg(port, HSRTRGR)->size) in scif_rtrg_enabled()
1143 struct uart_port *port = &s->port; in rx_fifo_timer_fn()
1145 dev_dbg(port->dev, "Rx timed out\n"); in rx_fifo_timer_fn()
1155 return sprintf(buf, "%d\n", sci->rx_trigger); in rx_fifo_trigger_show()
1171 sci->rx_trigger = scif_set_rtrg(port, r); in rx_fifo_trigger_store()
1172 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) in rx_fifo_trigger_store()
1188 if (port->type == PORT_HSCIF) in rx_fifo_timeout_show()
1189 v = sci->hscif_tot >> HSSCR_TOT_SHIFT; in rx_fifo_timeout_show()
1191 v = sci->rx_fifo_timeout; in rx_fifo_timeout_show()
1210 if (port->type == PORT_HSCIF) { in rx_fifo_timeout_store()
1212 return -EINVAL; in rx_fifo_timeout_store()
1213 sci->hscif_tot = r << HSSCR_TOT_SHIFT; in rx_fifo_timeout_store()
1215 sci->rx_fifo_timeout = r; in rx_fifo_timeout_store()
1218 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0); in rx_fifo_timeout_store()
1231 struct uart_port *port = &s->port; in sci_dma_tx_complete()
1232 struct tty_port *tport = &port->state->port; in sci_dma_tx_complete()
1235 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); in sci_dma_tx_complete()
1239 uart_xmit_advance(port, s->tx_dma_len); in sci_dma_tx_complete()
1241 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in sci_dma_tx_complete()
1244 if (!kfifo_is_empty(&tport->xmit_fifo)) { in sci_dma_tx_complete()
1245 s->cookie_tx = 0; in sci_dma_tx_complete()
1246 schedule_work(&s->work_tx); in sci_dma_tx_complete()
1248 s->cookie_tx = -EINVAL; in sci_dma_tx_complete()
1249 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || in sci_dma_tx_complete()
1250 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { in sci_dma_tx_complete()
1251 u16 ctrl = sci_serial_in(port, SCSCR); in sci_dma_tx_complete() local
1252 sci_serial_out(port, SCSCR, ctrl & ~SCSCR_TIE); in sci_dma_tx_complete()
1253 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { in sci_dma_tx_complete()
1255 dmaengine_pause(s->chan_tx_saved); in sci_dma_tx_complete()
1256 enable_irq(s->irqs[SCIx_TXI_IRQ]); in sci_dma_tx_complete()
1267 struct uart_port *port = &s->port; in sci_dma_rx_push()
1268 struct tty_port *tport = &port->state->port; in sci_dma_rx_push()
1273 port->icount.buf_overrun++; in sci_dma_rx_push()
1275 port->icount.rx += copied; in sci_dma_rx_push()
1284 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) in sci_dma_rx_find_active()
1285 if (s->active_rx == s->cookie_rx[i]) in sci_dma_rx_find_active()
1288 return -1; in sci_dma_rx_find_active()
1296 s->chan_rx = NULL; in sci_dma_rx_chan_invalidate()
1297 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) in sci_dma_rx_chan_invalidate()
1298 s->cookie_rx[i] = -EINVAL; in sci_dma_rx_chan_invalidate()
1299 s->active_rx = 0; in sci_dma_rx_chan_invalidate()
1304 struct dma_chan *chan = s->chan_rx_saved; in sci_dma_rx_release()
1305 struct uart_port *port = &s->port; in sci_dma_rx_release()
1309 s->chan_rx_saved = NULL; in sci_dma_rx_release()
1314 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0], in sci_dma_rx_release()
1315 sg_dma_address(&s->sg_rx[0])); in sci_dma_rx_release()
1330 struct uart_port *port = &s->port; in sci_dma_rx_reenable_irq()
1335 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || in sci_dma_rx_reenable_irq()
1336 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { in sci_dma_rx_reenable_irq()
1337 enable_irq(s->irqs[SCIx_RXI_IRQ]); in sci_dma_rx_reenable_irq()
1338 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) in sci_dma_rx_reenable_irq()
1339 scif_set_rtrg(port, s->rx_trigger); in sci_dma_rx_reenable_irq()
1349 struct dma_chan *chan = s->chan_rx; in sci_dma_rx_complete()
1350 struct uart_port *port = &s->port; in sci_dma_rx_complete()
1355 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line, in sci_dma_rx_complete()
1356 s->active_rx); in sci_dma_rx_complete()
1358 hrtimer_cancel(&s->rx_timer); in sci_dma_rx_complete()
1364 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx); in sci_dma_rx_complete()
1367 tty_flip_buffer_push(&port->state->port); in sci_dma_rx_complete()
1369 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1, in sci_dma_rx_complete()
1375 desc->callback = sci_dma_rx_complete; in sci_dma_rx_complete()
1376 desc->callback_param = s; in sci_dma_rx_complete()
1377 s->cookie_rx[active] = dmaengine_submit(desc); in sci_dma_rx_complete()
1378 if (dma_submit_error(s->cookie_rx[active])) in sci_dma_rx_complete()
1381 s->active_rx = s->cookie_rx[!active]; in sci_dma_rx_complete()
1386 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n", in sci_dma_rx_complete()
1387 __func__, s->cookie_rx[active], active, s->active_rx); in sci_dma_rx_complete()
1389 start_hrtimer_us(&s->rx_timer, s->rx_timeout); in sci_dma_rx_complete()
1399 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); in sci_dma_rx_complete()
1404 struct dma_chan *chan = s->chan_tx_saved; in sci_dma_tx_release()
1406 cancel_work_sync(&s->work_tx); in sci_dma_tx_release()
1407 s->chan_tx_saved = s->chan_tx = NULL; in sci_dma_tx_release()
1408 s->cookie_tx = -EINVAL; in sci_dma_tx_release()
1410 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE, in sci_dma_tx_release()
1417 struct dma_chan *chan = s->chan_rx; in sci_dma_rx_submit()
1418 struct uart_port *port = &s->port; in sci_dma_rx_submit()
1423 struct scatterlist *sg = &s->sg_rx[i]; in sci_dma_rx_submit()
1432 desc->callback = sci_dma_rx_complete; in sci_dma_rx_submit()
1433 desc->callback_param = s; in sci_dma_rx_submit()
1434 s->cookie_rx[i] = dmaengine_submit(desc); in sci_dma_rx_submit()
1435 if (dma_submit_error(s->cookie_rx[i])) in sci_dma_rx_submit()
1440 s->active_rx = s->cookie_rx[0]; in sci_dma_rx_submit()
1455 return -EAGAIN; in sci_dma_rx_submit()
1462 struct dma_chan *chan = s->chan_tx; in sci_dma_tx_work_fn()
1463 struct uart_port *port = &s->port; in sci_dma_tx_work_fn()
1464 struct tty_port *tport = &port->state->port; in sci_dma_tx_work_fn()
1477 s->tx_dma_len = kfifo_out_linear(&tport->xmit_fifo, &tail, in sci_dma_tx_work_fn()
1479 buf = s->tx_dma_addr + tail; in sci_dma_tx_work_fn()
1480 if (!s->tx_dma_len) { in sci_dma_tx_work_fn()
1486 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len, in sci_dma_tx_work_fn()
1491 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n"); in sci_dma_tx_work_fn()
1495 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len, in sci_dma_tx_work_fn()
1498 desc->callback = sci_dma_tx_complete; in sci_dma_tx_work_fn()
1499 desc->callback_param = s; in sci_dma_tx_work_fn()
1500 s->cookie_tx = dmaengine_submit(desc); in sci_dma_tx_work_fn()
1501 if (dma_submit_error(s->cookie_tx)) { in sci_dma_tx_work_fn()
1503 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); in sci_dma_tx_work_fn()
1508 dev_dbg(port->dev, "%s: %p: %u, cookie %d\n", in sci_dma_tx_work_fn()
1509 __func__, tport->xmit_buf, tail, s->cookie_tx); in sci_dma_tx_work_fn()
1516 s->chan_tx = NULL; in sci_dma_tx_work_fn()
1525 struct dma_chan *chan = s->chan_rx; in sci_dma_rx_timer_fn()
1526 struct uart_port *port = &s->port; in sci_dma_rx_timer_fn()
1533 dev_dbg(port->dev, "DMA Rx timed out\n"); in sci_dma_rx_timer_fn()
1543 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); in sci_dma_rx_timer_fn()
1546 dev_dbg(port->dev, "Cookie %d #%d has already completed\n", in sci_dma_rx_timer_fn()
1547 s->active_rx, active); in sci_dma_rx_timer_fn()
1561 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); in sci_dma_rx_timer_fn()
1564 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped"); in sci_dma_rx_timer_fn()
1569 dmaengine_terminate_async(s->chan_rx); in sci_dma_rx_timer_fn()
1570 read = sg_dma_len(&s->sg_rx[active]) - state.residue; in sci_dma_rx_timer_fn()
1573 count = sci_dma_rx_push(s, s->rx_buf[active], read); in sci_dma_rx_timer_fn()
1575 tty_flip_buffer_push(&port->state->port); in sci_dma_rx_timer_fn()
1578 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || in sci_dma_rx_timer_fn()
1579 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) in sci_dma_rx_timer_fn()
1596 chan = dma_request_chan(port->dev, dir == DMA_MEM_TO_DEV ? "tx" : "rx"); in sci_request_dma_chan()
1598 dev_dbg(port->dev, "dma_request_chan failed\n"); in sci_request_dma_chan()
1604 cfg.dst_addr = port->mapbase + in sci_request_dma_chan()
1605 (sci_getreg(port, SCxTDR)->offset << port->regshift); in sci_request_dma_chan()
1607 cfg.src_addr = port->mapbase + in sci_request_dma_chan()
1608 (sci_getreg(port, SCxRDR)->offset << port->regshift); in sci_request_dma_chan()
1613 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret); in sci_request_dma_chan()
1624 struct tty_port *tport = &port->state->port; in sci_request_dma()
1627 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line); in sci_request_dma()
1636 if (!port->dev->of_node) in sci_request_dma()
1639 s->cookie_tx = -EINVAL; in sci_request_dma()
1645 if (!of_property_present(port->dev->of_node, "dmas")) in sci_request_dma()
1649 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); in sci_request_dma()
1652 s->tx_dma_addr = dma_map_single(chan->device->dev, in sci_request_dma()
1653 tport->xmit_buf, in sci_request_dma()
1656 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) { in sci_request_dma()
1657 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n"); in sci_request_dma()
1660 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n", in sci_request_dma()
1662 tport->xmit_buf, &s->tx_dma_addr); in sci_request_dma()
1664 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn); in sci_request_dma()
1665 s->chan_tx_saved = s->chan_tx = chan; in sci_request_dma()
1670 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); in sci_request_dma()
1676 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize); in sci_request_dma()
1677 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2, in sci_request_dma()
1680 dev_warn(port->dev, in sci_request_dma()
1687 struct scatterlist *sg = &s->sg_rx[i]; in sci_request_dma()
1690 s->rx_buf[i] = buf; in sci_request_dma()
1692 sg_dma_len(sg) = s->buf_len_rx; in sci_request_dma()
1694 buf += s->buf_len_rx; in sci_request_dma()
1695 dma += s->buf_len_rx; in sci_request_dma()
1698 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in sci_request_dma()
1699 s->rx_timer.function = sci_dma_rx_timer_fn; in sci_request_dma()
1701 s->chan_rx_saved = s->chan_rx = chan; in sci_request_dma()
1703 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || in sci_request_dma()
1704 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) in sci_request_dma()
1713 if (s->chan_tx_saved) in sci_free_dma()
1715 if (s->chan_rx_saved) in sci_free_dma()
1728 s->tx_dma_len = 0; in sci_flush_buffer()
1729 if (s->chan_tx) { in sci_flush_buffer()
1730 dmaengine_terminate_async(s->chan_tx); in sci_flush_buffer()
1731 s->cookie_tx = -EINVAL; in sci_flush_buffer()
1752 if (s->chan_rx) { in sci_rx_interrupt()
1757 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || in sci_rx_interrupt()
1758 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { in sci_rx_interrupt()
1759 disable_irq_nosync(s->irqs[SCIx_RXI_IRQ]); in sci_rx_interrupt()
1760 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { in sci_rx_interrupt()
1776 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n", in sci_rx_interrupt()
1777 jiffies, s->rx_timeout); in sci_rx_interrupt()
1778 start_hrtimer_us(&s->rx_timer, s->rx_timeout); in sci_rx_interrupt()
1786 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) { in sci_rx_interrupt()
1788 scif_set_rtrg(port, s->rx_trigger); in sci_rx_interrupt()
1790 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP( in sci_rx_interrupt()
1791 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000)); in sci_rx_interrupt()
1819 unsigned short ctrl; in sci_tx_end_interrupt() local
1821 if (port->type != PORT_SCI) in sci_tx_end_interrupt()
1825 ctrl = sci_serial_in(port, SCSCR); in sci_tx_end_interrupt()
1826 ctrl &= ~(SCSCR_TE | SCSCR_TEIE); in sci_tx_end_interrupt()
1827 sci_serial_out(port, SCSCR, ctrl); in sci_tx_end_interrupt()
1853 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) { in sci_er_interrupt()
1867 if (port->type == PORT_SCI) { in sci_er_interrupt()
1875 if (!s->chan_rx) in sci_er_interrupt()
1882 if (!s->chan_tx) in sci_er_interrupt()
1897 if (s->params->overrun_reg == SCxSR) in sci_mpxed_interrupt()
1899 else if (sci_getreg(port, s->params->overrun_reg)->size) in sci_mpxed_interrupt()
1900 orer_status = sci_serial_in(port, s->params->overrun_reg); in sci_mpxed_interrupt()
1906 !s->chan_tx) in sci_mpxed_interrupt()
1913 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && in sci_mpxed_interrupt()
1922 if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] && in sci_mpxed_interrupt()
1927 if (orer_status & s->params->overrun_mask) { in sci_mpxed_interrupt()
1983 struct uart_port *up = &port->port; in sci_request_irq()
1992 if (port->irqs[w] == port->irqs[i]) in sci_request_irq()
1999 irq = up->irq; in sci_request_irq()
2001 irq = port->irqs[i]; in sci_request_irq()
2012 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", in sci_request_irq()
2013 dev_name(up->dev), desc->desc); in sci_request_irq()
2014 if (!port->irqstr[j]) { in sci_request_irq()
2015 ret = -ENOMEM; in sci_request_irq()
2019 ret = request_irq(irq, desc->handler, up->irqflags, in sci_request_irq()
2020 port->irqstr[j], port); in sci_request_irq()
2022 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); in sci_request_irq()
2030 while (--i >= 0) in sci_request_irq()
2031 free_irq(port->irqs[i], port); in sci_request_irq()
2034 while (--j >= 0) in sci_request_irq()
2035 kfree(port->irqstr[j]); in sci_request_irq()
2049 int irq = port->irqs[i]; in sci_free_irq()
2060 if (port->irqs[j] == irq) in sci_free_irq()
2065 free_irq(port->irqs[i], port); in sci_free_irq()
2066 kfree(port->irqstr[i]); in sci_free_irq()
2085 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { in sci_set_rts()
2098 } else if (sci_getreg(port, SCSPTR)->size) { in sci_set_rts()
2099 u16 ctrl = sci_serial_in(port, SCSPTR); in sci_set_rts() local
2103 ctrl &= ~SCSPTR_RTSDT; in sci_set_rts()
2105 ctrl |= SCSPTR_RTSDT; in sci_set_rts()
2106 sci_serial_out(port, SCSPTR, ctrl); in sci_set_rts()
2112 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { in sci_get_cts()
2115 } else if (sci_getreg(port, SCSPTR)->size) { in sci_get_cts()
2127 * handled via the ->init_pins() op, which is a bit of a one-way street,
2128 * lacking any ability to defer pin control -- this will later be
2146 if (reg->size) in sci_set_mctrl()
2151 mctrl_gpio_set(s->gpios, mctrl); in sci_set_mctrl()
2153 if (!s->has_rtscts) in sci_set_mctrl()
2158 if (s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE) in sci_set_mctrl()
2164 } else if (s->autorts) { in sci_set_mctrl()
2165 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { in sci_set_mctrl()
2172 if (s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE) in sci_set_mctrl()
2184 struct mctrl_gpios *gpios = s->gpios; in sci_get_mctrl() local
2187 mctrl_gpio_get(gpios, &mctrl); in sci_get_mctrl()
2193 if (s->autorts) { in sci_get_mctrl()
2196 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) { in sci_get_mctrl()
2199 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)) in sci_get_mctrl()
2201 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)) in sci_get_mctrl()
2209 mctrl_gpio_enable_ms(to_sci_port(port)->gpios); in sci_enable_ms()
2218 if (!sci_getreg(port, SCSPTR)->size) { in sci_break_ctl()
2230 if (break_state == -1) { in sci_break_ctl()
2248 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); in sci_startup()
2267 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); in sci_shutdown()
2269 s->autorts = false; in sci_shutdown()
2270 mctrl_gpio_disable_ms(to_sci_port(port)->gpios); in sci_shutdown()
2281 scr & (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot)); in sci_shutdown()
2285 if (s->chan_rx_saved) { in sci_shutdown()
2286 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__, in sci_shutdown()
2287 port->line); in sci_shutdown()
2288 hrtimer_cancel(&s->rx_timer); in sci_shutdown()
2292 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) in sci_shutdown()
2293 del_timer_sync(&s->rx_fifo_timer); in sci_shutdown()
2301 unsigned long freq = s->clk_rates[SCI_SCK]; in sci_sck_calc()
2305 if (s->port.type != PORT_HSCIF) in sci_sck_calc()
2309 err = DIV_ROUND_CLOSEST(freq, sr) - bps; in sci_sck_calc()
2314 *srr = sr - 1; in sci_sck_calc()
2320 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err, in sci_sck_calc()
2332 if (s->port.type != PORT_HSCIF) in sci_brg_calc()
2339 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps; in sci_brg_calc()
2345 *srr = sr - 1; in sci_brg_calc()
2351 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps, in sci_brg_calc()
2361 unsigned long freq = s->clk_rates[SCI_FCK]; in sci_scbrr_calc()
2365 if (s->port.type != PORT_HSCIF) in sci_scbrr_calc()
2379 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - in sci_scbrr_calc()
2380 * (|D - 0.5| / N * (1 + F))| in sci_scbrr_calc()
2392 * err = freq / (br * prediv) - bps in sci_scbrr_calc()
2404 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps; in sci_scbrr_calc()
2409 *brr = br - 1; in sci_scbrr_calc()
2410 *srr = sr - 1; in sci_scbrr_calc()
2419 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps, in sci_scbrr_calc()
2430 sci_serial_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */ in sci_reset()
2433 if (reg->size) in sci_reset()
2439 if (sci_getreg(port, SCLSR)->size) { in sci_reset()
2445 if (s->rx_trigger > 1) { in sci_reset()
2446 if (s->rx_fifo_timeout) { in sci_reset()
2448 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0); in sci_reset()
2450 if (port->type == PORT_SCIFA || in sci_reset()
2451 port->type == PORT_SCIFB) in sci_reset()
2454 scif_set_rtrg(port, s->rx_trigger); in sci_reset()
2469 int best_clk = -1; in sci_set_termios()
2472 if ((termios->c_cflag & CSIZE) == CS7) { in sci_set_termios()
2475 termios->c_cflag &= ~CSIZE; in sci_set_termios()
2476 termios->c_cflag |= CS8; in sci_set_termios()
2478 if (termios->c_cflag & PARENB) in sci_set_termios()
2480 if (termios->c_cflag & PARODD) in sci_set_termios()
2482 if (termios->c_cflag & CSTOPB) in sci_set_termios()
2486 * earlyprintk comes here early on with port->uartclk set to zero. in sci_set_termios()
2489 * the baud rate is not programmed during earlyprintk - it is assumed in sci_set_termios()
2493 if (!port->uartclk) { in sci_set_termios()
2499 max_freq = max(max_freq, s->clk_rates[i]); in sci_set_termios()
2511 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA && in sci_set_termios()
2512 port->type != PORT_SCIFB) { in sci_set_termios()
2526 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) { in sci_set_termios()
2527 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1, in sci_set_termios()
2542 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) { in sci_set_termios()
2543 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1, in sci_set_termios()
2570 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", in sci_set_termios()
2571 s->clks[best_clk], baud, min_err); in sci_set_termios()
2579 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) { in sci_set_termios()
2588 uart_update_timeout(port, termios->c_cflag, baud); in sci_set_termios()
2591 bits = tty_get_frame_size(termios->c_cflag); in sci_set_termios()
2593 if (sci_getreg(port, SEMR)->size) in sci_set_termios()
2597 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) in sci_set_termios()
2609 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot); in sci_set_termios()
2612 if (sci_getreg(port, HSSRR)->size) { in sci_set_termios()
2617 int last_stop = bits * 2 - 1; in sci_set_termios()
2627 int shift = clamp(deviation / 2, -8, 7); in sci_set_termios()
2637 udelay((1000000 + (baud - 1)) / baud); in sci_set_termios()
2640 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0); in sci_set_termios()
2643 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot); in sci_set_termios()
2647 sci_init_pins(port, termios->c_cflag); in sci_set_termios()
2649 port->status &= ~UPSTAT_AUTOCTS; in sci_set_termios()
2650 s->autorts = false; in sci_set_termios()
2652 if (reg->size) { in sci_set_termios()
2653 unsigned short ctrl = sci_serial_in(port, SCFCR); in sci_set_termios() local
2655 if ((port->flags & UPF_HARD_FLOW) && in sci_set_termios()
2656 (termios->c_cflag & CRTSCTS)) { in sci_set_termios()
2658 port->status |= UPSTAT_AUTOCTS; in sci_set_termios()
2660 s->autorts = true; in sci_set_termios()
2668 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); in sci_set_termios()
2670 sci_serial_out(port, SCFCR, ctrl); in sci_set_termios()
2672 if (port->flags & UPF_HARD_FLOW) { in sci_set_termios()
2674 sci_set_mctrl(port, port->mctrl); in sci_set_termios()
2682 if (port->type != PORT_SCI) in sci_set_termios()
2684 scr_val |= SCSCR_RE | (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)); in sci_set_termios()
2685 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot); in sci_set_termios()
2687 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) { in sci_set_termios()
2698 s->rx_frame = (10000 * bits) / (baud / 100); in sci_set_termios()
2700 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame; in sci_set_termios()
2703 if ((termios->c_cflag & CREAD) != 0) in sci_set_termios()
2710 if (UART_ENABLE_MS(port, termios->c_cflag)) in sci_set_termios()
2731 switch (port->type) { in sci_type()
2756 if (port->membase) in sci_remap_port()
2759 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { in sci_remap_port()
2760 port->membase = ioremap(port->mapbase, sport->reg_size); in sci_remap_port()
2761 if (unlikely(!port->membase)) { in sci_remap_port()
2762 dev_err(port->dev, "can't remap port#%d\n", port->line); in sci_remap_port()
2763 return -ENXIO; in sci_remap_port()
2771 port->membase = (void __iomem *)(uintptr_t)port->mapbase; in sci_remap_port()
2781 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { in sci_release_port()
2782 iounmap(port->membase); in sci_release_port()
2783 port->membase = NULL; in sci_release_port()
2786 release_mem_region(port->mapbase, sport->reg_size); in sci_release_port()
2795 res = request_mem_region(port->mapbase, sport->reg_size, in sci_request_port()
2796 dev_name(port->dev)); in sci_request_port()
2798 dev_err(port->dev, "request_mem_region failed."); in sci_request_port()
2799 return -EBUSY; in sci_request_port()
2816 port->type = sport->cfg->type; in sci_config_port()
2823 if (ser->baud_base < 2400) in sci_verify_port()
2825 return -EINVAL; in sci_verify_port()
2866 if (sci_port->cfg->type == PORT_HSCIF) in sci_init_clocks()
2892 sci_port->clks[i] = clk; in sci_init_clocks()
2902 if (cfg->regtype != SCIx_PROBE_REGTYPE) in sci_probe_regmap()
2903 return &sci_port_params[cfg->regtype]; in sci_probe_regmap()
2905 switch (cfg->type) { in sci_probe_regmap()
2920 * The SH-4 is a bit of a misnomer here, although that's in sci_probe_regmap()
2942 struct uart_port *port = &sci_port->port; in sci_init_single()
2947 sci_port->cfg = p; in sci_init_single()
2949 port->ops = &sci_uart_ops; in sci_init_single()
2950 port->iotype = UPIO_MEM; in sci_init_single()
2951 port->line = index; in sci_init_single()
2952 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE); in sci_init_single()
2956 return -ENOMEM; in sci_init_single()
2958 port->mapbase = res->start; in sci_init_single()
2959 sci_port->reg_size = resource_size(res); in sci_init_single()
2961 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) { in sci_init_single()
2963 sci_port->irqs[i] = platform_get_irq_optional(dev, i); in sci_init_single()
2965 sci_port->irqs[i] = platform_get_irq(dev, i); in sci_init_single()
2972 if (p->type == PORT_SCI) in sci_init_single()
2973 swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]); in sci_init_single()
2978 * In the non-muxed case, up to 6 interrupt signals might be generated in sci_init_single()
2982 if (sci_port->irqs[0] < 0) in sci_init_single()
2983 return -ENXIO; in sci_init_single()
2985 if (sci_port->irqs[1] < 0) in sci_init_single()
2986 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++) in sci_init_single()
2987 sci_port->irqs[i] = sci_port->irqs[0]; in sci_init_single()
2989 sci_port->params = sci_probe_regmap(p); in sci_init_single()
2990 if (unlikely(sci_port->params == NULL)) in sci_init_single()
2991 return -EINVAL; in sci_init_single()
2993 switch (p->type) { in sci_init_single()
2995 sci_port->rx_trigger = 48; in sci_init_single()
2998 sci_port->rx_trigger = 64; in sci_init_single()
3001 sci_port->rx_trigger = 32; in sci_init_single()
3004 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) in sci_init_single()
3006 sci_port->rx_trigger = 1; in sci_init_single()
3008 sci_port->rx_trigger = 8; in sci_init_single()
3011 sci_port->rx_trigger = 1; in sci_init_single()
3015 sci_port->rx_fifo_timeout = 0; in sci_init_single()
3016 sci_port->hscif_tot = 0; in sci_init_single()
3022 sci_port->sampling_rate_mask = p->sampling_rate in sci_init_single()
3023 ? SCI_SR(p->sampling_rate) in sci_init_single()
3024 : sci_port->params->sampling_rate_mask; in sci_init_single()
3027 ret = sci_init_clocks(sci_port, &dev->dev); in sci_init_single()
3031 port->dev = &dev->dev; in sci_init_single()
3033 pm_runtime_enable(&dev->dev); in sci_init_single()
3036 port->type = p->type; in sci_init_single()
3037 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; in sci_init_single()
3038 port->fifosize = sci_port->params->fifosize; in sci_init_single()
3040 if (port->type == PORT_SCI && !dev->dev.of_node) { in sci_init_single()
3041 if (sci_port->reg_size >= 0x20) in sci_init_single()
3042 port->regshift = 2; in sci_init_single()
3044 port->regshift = 1; in sci_init_single()
3049 * for the multi-IRQ ports, which is where we are primarily in sci_init_single()
3054 port->irq = sci_port->irqs[SCIx_RXI_IRQ]; in sci_init_single()
3055 port->irqflags = 0; in sci_init_single()
3062 pm_runtime_disable(port->port.dev); in sci_cleanup_single()
3079 struct sci_port *sci_port = &sci_ports[co->index]; in serial_console_write()
3080 struct uart_port *port = &sci_port->port; in serial_console_write()
3081 unsigned short bits, ctrl, ctrl_temp; in serial_console_write() local
3085 if (port->sysrq) in serial_console_write()
3093 ctrl = sci_serial_in(port, SCSCR); in serial_console_write()
3095 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | in serial_console_write()
3096 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)); in serial_console_write()
3097 sci_serial_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot); in serial_console_write()
3107 sci_serial_out(port, SCSCR, ctrl); in serial_console_write()
3126 if (co->index < 0 || co->index >= SCI_NPORTS) in serial_console_setup()
3127 return -ENODEV; in serial_console_setup()
3129 sci_port = &sci_ports[co->index]; in serial_console_setup()
3130 port = &sci_port->port; in serial_console_setup()
3135 if (!port->ops) in serial_console_setup()
3136 return -ENODEV; in serial_console_setup()
3154 .index = -1,
3179 .index = -1,
3184 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); in sci_probe_earlyprintk()
3187 return -EEXIST; in sci_probe_earlyprintk()
3189 early_serial_console.index = pdev->id; in sci_probe_earlyprintk()
3191 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true); in sci_probe_earlyprintk()
3206 return -EINVAL; in sci_probe_earlyprintk()
3229 unsigned int type = port->port.type; /* uart_remove_... clears it */ in sci_remove()
3231 sci_ports_in_use &= ~BIT(port->port.line); in sci_remove()
3232 uart_remove_one_port(&sci_uart_driver, &port->port); in sci_remove()
3236 if (port->port.fifosize > 1) in sci_remove()
3237 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); in sci_remove()
3239 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout); in sci_remove()
3248 /* SoC-specific types */
3250 .compatible = "renesas,scif-r7s72100",
3254 .compatible = "renesas,scif-r7s9210",
3258 .compatible = "renesas,scif-r9a07g044",
3262 .compatible = "renesas,scif-r9a09g057",
3265 /* Family-specific types */
3267 .compatible = "renesas,rcar-gen1-scif",
3270 .compatible = "renesas,rcar-gen2-scif",
3273 .compatible = "renesas,rcar-gen3-scif",
3276 .compatible = "renesas,rcar-gen4-scif",
3309 struct device_node *np = pdev->dev.of_node; in sci_parse_dt()
3317 return ERR_PTR(-EINVAL); in sci_parse_dt()
3319 data = of_device_get_match_data(&pdev->dev); in sci_parse_dt()
3321 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); in sci_parse_dt()
3323 return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc), in sci_parse_dt()
3324 "failed to get reset ctrl\n")); in sci_parse_dt()
3328 dev_err(&pdev->dev, "failed to deassert reset %d\n", ret); in sci_parse_dt()
3332 ret = devm_add_action_or_reset(&pdev->dev, sci_reset_control_assert, rstc); in sci_parse_dt()
3334 dev_err(&pdev->dev, "failed to register assert devm action, %d\n", in sci_parse_dt()
3339 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); in sci_parse_dt()
3341 return ERR_PTR(-ENOMEM); in sci_parse_dt()
3348 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); in sci_parse_dt()
3349 return ERR_PTR(-EINVAL); in sci_parse_dt()
3352 dev_err(&pdev->dev, "serial%d out of range\n", id); in sci_parse_dt()
3353 return ERR_PTR(-EINVAL); in sci_parse_dt()
3359 p->type = SCI_OF_TYPE(data); in sci_parse_dt()
3360 p->regtype = SCI_OF_REGTYPE(data); in sci_parse_dt()
3362 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts"); in sci_parse_dt()
3376 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n", in sci_probe_single()
3378 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); in sci_probe_single()
3379 return -EINVAL; in sci_probe_single()
3383 return -EBUSY; in sci_probe_single()
3399 sciport->gpios = mctrl_gpio_init(&sciport->port, 0); in sci_probe_single()
3400 if (IS_ERR(sciport->gpios)) in sci_probe_single()
3401 return PTR_ERR(sciport->gpios); in sci_probe_single()
3403 if (sciport->has_rtscts) { in sci_probe_single()
3404 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) || in sci_probe_single()
3405 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) { in sci_probe_single()
3406 dev_err(&dev->dev, "Conflicting RTS/CTS config\n"); in sci_probe_single()
3407 return -EINVAL; in sci_probe_single()
3409 sciport->port.flags |= UPF_HARD_FLOW; in sci_probe_single()
3412 ret = uart_add_one_port(&sci_uart_driver, &sciport->port); in sci_probe_single()
3438 if (dev->dev.of_node) { in sci_probe()
3443 p = dev->dev.platform_data; in sci_probe()
3445 dev_err(&dev->dev, "no platform data supplied\n"); in sci_probe()
3446 return -EINVAL; in sci_probe()
3449 dev_id = dev->id; in sci_probe()
3459 if (sp->port.fifosize > 1) { in sci_probe()
3460 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger); in sci_probe()
3464 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB || in sci_probe()
3465 sp->port.type == PORT_HSCIF) { in sci_probe()
3466 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout); in sci_probe()
3468 if (sp->port.fifosize > 1) { in sci_probe()
3469 device_remove_file(&dev->dev, in sci_probe()
3489 uart_suspend_port(&sci_uart_driver, &sport->port); in sci_suspend()
3499 uart_resume_port(&sci_uart_driver, &sport->port); in sci_resume()
3510 .name = "sh-sci",
3541 if (!device->port.membase) in early_console_setup()
3542 return -ENODEV; in early_console_setup()
3544 device->port.type = type; in early_console_setup()
3545 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port)); in early_console_setup()
3553 device->con->write = serial_console_write; in early_console_setup()
3598 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
3599 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
3600 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a09g057", rzv2hscif_early_console_setup);
3610 MODULE_ALIAS("platform:sh-sci");