107 	struct uart_port			uport;  member
159 	return readl(tup->uport.membase + (reg << tup->uport.regshift));  in tegra_uart_read()
165 	writel(val, tup->uport.membase + (reg << tup->uport.regshift));  in tegra_uart_write()
170 	return container_of(u, struct tegra_uart_port, uport);  in to_tegra_uport()
372 		dev_err(tup->uport.dev,  in tegra_check_rate_in_range()
400 			dev_err(tup->uport.dev,  in tegra_set_baudrate()
414 	uart_port_lock_irqsave(&tup->uport, &flags);  in tegra_set_baudrate()
427 	uart_port_unlock_irqrestore(&tup->uport, flags);  in tegra_set_baudrate()
445 			tup->uport.icount.overrun++;  in tegra_uart_decode_rx_error()
446 			dev_dbg(tup->uport.dev, "Got overrun errors\n");  in tegra_uart_decode_rx_error()
450 			tup->uport.icount.parity++;  in tegra_uart_decode_rx_error()
451 			dev_dbg(tup->uport.dev, "Got Parity errors\n");  in tegra_uart_decode_rx_error()
454 			tup->uport.icount.frame++;  in tegra_uart_decode_rx_error()
455 			dev_dbg(tup->uport.dev, "Got frame errors\n");  in tegra_uart_decode_rx_error()
463 			if (tup->uport.ignore_status_mask & UART_LSR_BI)  in tegra_uart_decode_rx_error()
466 			tup->uport.icount.brk++;  in tegra_uart_decode_rx_error()
467 			dev_dbg(tup->uport.dev, "Got Break\n");  in tegra_uart_decode_rx_error()
469 		uart_insert_char(&tup->uport, lsr, UART_LSR_OE, 0, flag);  in tegra_uart_decode_rx_error()
496 		if (WARN_ON_ONCE(!uart_fifo_get(&tup->uport, &ch)))  in tegra_uart_fill_tx_fifo()
517 	struct tty_port *tport = &tup->uport.state->port;  in tegra_uart_tx_dma_complete()
525 	uart_port_lock_irqsave(&tup->uport, &flags);  in tegra_uart_tx_dma_complete()
526 	uart_xmit_advance(&tup->uport, count);  in tegra_uart_tx_dma_complete()
529 		uart_write_wakeup(&tup->uport);  in tegra_uart_tx_dma_complete()
531 	uart_port_unlock_irqrestore(&tup->uport, flags);  in tegra_uart_tx_dma_complete()
537 	struct tty_port *tport = &tup->uport.state->port;  in tegra_uart_start_tx_dma()
546 	dma_sync_single_for_device(tup->uport.dev, tx_phys_addr,  in tegra_uart_start_tx_dma()
553 		dev_err(tup->uport.dev, "Not able to get desc for Tx\n");  in tegra_uart_start_tx_dma()
568 	struct tty_port *tport = &tup->uport.state->port;  in tegra_uart_start_next_tx()
631 	uart_xmit_advance(&tup->uport, count);  in tegra_uart_stop_tx()
637 	struct tty_port *tport = &tup->uport.state->port;  in tegra_uart_handle_tx_pio()
642 		uart_write_wakeup(&tup->uport);  in tegra_uart_handle_tx_pio()
662 		tup->uport.icount.rx++;  in tegra_uart_handle_rx_pio()
664 		if (uart_handle_sysrq_char(&tup->uport, ch))  in tegra_uart_handle_rx_pio()
667 		if (tup->uport.ignore_status_mask & UART_LSR_DR)  in tegra_uart_handle_rx_pio()
684 	tup->uport.icount.rx += count;  in tegra_uart_copy_rx_to_tty()
686 	if (tup->uport.ignore_status_mask & UART_LSR_DR)  in tegra_uart_copy_rx_to_tty()
689 	dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys,  in tegra_uart_copy_rx_to_tty()
695 		dev_err(tup->uport.dev, "RxData copy to tty layer failed\n");  in tegra_uart_copy_rx_to_tty()
697 	dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,  in tegra_uart_copy_rx_to_tty()
703 	struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port);  in do_handle_rx_pio()
704 	struct tty_port *port = &tup->uport.state->port;  in do_handle_rx_pio()
716 	struct tty_port *port = &tup->uport.state->port;  in tegra_uart_rx_buffer_push()
731 	struct uart_port *u = &tup->uport;  in tegra_uart_rx_dma_complete()
741 		dev_dbg(tup->uport.dev, "RX DMA is in progress\n");  in tegra_uart_rx_dma_complete()
801 		dev_err(tup->uport.dev, "Not able to get desc for Rx\n");  in tegra_uart_start_rx_dma()
824 		tup->uport.icount.rng++;  in tegra_uart_handle_modem_signal_change()
826 		tup->uport.icount.dsr++;  in tegra_uart_handle_modem_signal_change()
829 		uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD);  in tegra_uart_handle_modem_signal_change()
832 		uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS);  in tegra_uart_handle_modem_signal_change()
838 	struct uart_port *u = &tup->uport;  in tegra_uart_isr()
915 	struct tty_port *port = &tup->uport.state->port;  in tegra_uart_stop_rx()
943 	unsigned long fifo_empty_time = tup->uport.fifosize * char_time;  in tegra_uart_hw_deinit()
957 			dev_err(tup->uport.dev,  in tegra_uart_hw_deinit()
970 					dev_err(tup->uport.dev,  in tegra_uart_hw_deinit()
978 	uart_port_lock_irqsave(&tup->uport, &flags);  in tegra_uart_hw_deinit()
982 	uart_port_unlock_irqrestore(&tup->uport, flags);  in tegra_uart_hw_deinit()
1007 		dev_err(tup->uport.dev, "could not enable clk\n");  in tegra_uart_hw_init()
1058 			dev_err(tup->uport.dev,  in tegra_uart_hw_init()
1080 		dev_err(tup->uport.dev, "Failed to set baud rate\n");  in tegra_uart_hw_init()
1125 		dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE,  in tegra_uart_dma_channel_free()
1133 		dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys,  in tegra_uart_dma_channel_free()
1150 	dma_chan = dma_request_chan(tup->uport.dev, dma_to_memory ? "rx" : "tx");  in tegra_uart_dma_channel_allocate()
1153 		dev_err(tup->uport.dev,  in tegra_uart_dma_channel_allocate()
1159 		dma_buf = dma_alloc_coherent(tup->uport.dev,  in tegra_uart_dma_channel_allocate()
1163 			dev_err(tup->uport.dev,  in tegra_uart_dma_channel_allocate()
1168 		dma_sync_single_for_device(tup->uport.dev, dma_phys,  in tegra_uart_dma_channel_allocate()
1171 		dma_sconfig.src_addr = tup->uport.mapbase;  in tegra_uart_dma_channel_allocate()
1178 		dma_buf = tup->uport.state->port.xmit_buf;  in tegra_uart_dma_channel_allocate()
1179 		dma_phys = dma_map_single(tup->uport.dev,  in tegra_uart_dma_channel_allocate()
1181 		if (dma_mapping_error(tup->uport.dev, dma_phys)) {  in tegra_uart_dma_channel_allocate()
1182 			dev_err(tup->uport.dev, "dma_map_single tx failed\n");  in tegra_uart_dma_channel_allocate()
1186 		dma_sconfig.dst_addr = tup->uport.mapbase;  in tegra_uart_dma_channel_allocate()
1196 		dev_err(tup->uport.dev,  in tegra_uart_dma_channel_allocate()
1352 		dev_err(tup->uport.dev, "Failed to set baud rate\n");  in tegra_uart_set_termios()
1383 	tup->uport.ignore_status_mask = 0;  in tegra_uart_set_termios()
1386 		tup->uport.ignore_status_mask |= UART_LSR_DR;  in tegra_uart_set_termios()
1388 		tup->uport.ignore_status_mask |= UART_LSR_BI;  in tegra_uart_set_termios()
1440 	tup->uport.line = port;  in tegra_uart_parse_dt()
1581 	u = &tup->uport;  in tegra_uart_probe()
1622 	struct uart_port *u = &tup->uport;  in tegra_uart_remove()
1631 	struct uart_port *u = &tup->uport;  in tegra_uart_suspend()
1639 	struct uart_port *u = &tup->uport;  in tegra_uart_resume()