119 	struct geni_se se;  member
201 	port->se.base = uport->membase;  in qcom_geni_serial_request_port()
412 		geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);  in qcom_geni_serial_poll_init()
612 		geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr,  in qcom_geni_serial_stop_tx_dma()
618 	geni_se_cancel_m_cmd(&port->se);  in qcom_geni_serial_stop_tx_dma()
623 		geni_se_abort_m_cmd(&port->se);  in qcom_geni_serial_stop_tx_dma()
653 	ret = geni_se_tx_dma_prep(&port->se, tail, xmit_size,  in qcom_geni_serial_start_tx_dma()
703 	geni_se_cancel_m_cmd(&port->se);  in __qcom_geni_serial_cancel_tx_cmd()
706 		geni_se_abort_m_cmd(&port->se);  in __qcom_geni_serial_cancel_tx_cmd()
768 	geni_se_cancel_s_cmd(&port->se);  in qcom_geni_serial_stop_rx_fifo()
793 	geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);  in qcom_geni_serial_start_rx_fifo()
812 	geni_se_cancel_s_cmd(&port->se);  in qcom_geni_serial_stop_rx_dma()
829 		geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr,  in qcom_geni_serial_stop_rx_dma()
843 	geni_se_setup_s_cmd(&port->se, UART_START_READ, UART_PARAM_RFR_OPEN);  in qcom_geni_serial_start_rx_dma()
845 	ret = geni_se_rx_dma_prep(&port->se, port->rx_buf,  in qcom_geni_serial_start_rx_dma()
866 	geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr, DMA_RX_BUF_SIZE);  in qcom_geni_serial_handle_rx_dma()
878 	ret = geni_se_rx_dma_prep(&port->se, port->rx_buf,  in qcom_geni_serial_handle_rx_dma()
998 	geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr, port->tx_remaining);  in qcom_geni_serial_handle_tx_dma()
1099 	port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);  in setup_fifos()
1100 	port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);  in setup_fifos()
1101 	port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);  in setup_fifos()
1147 	proto = geni_se_read_proto(&port->se);  in qcom_geni_serial_port_setup()
1180 	geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,  in qcom_geni_serial_port_setup()
1182 	geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2);  in qcom_geni_serial_port_setup()
1183 	geni_se_select_mode(&port->se, port->dev_data->mode);  in qcom_geni_serial_port_setup()
1294 	ver = geni_se_get_qup_hw_version(&port->se);  in qcom_geni_serial_set_termios()
1298 	clk_rate = get_clk_div_rate(port->se.clk, baud,  in qcom_geni_serial_set_termios()
1301 		dev_err(port->se.dev,  in qcom_geni_serial_set_termios()
1307 	dev_dbg(port->se.dev, "desired_rate = %u, clk_rate = %lu, clk_div = %u\n",  in qcom_geni_serial_set_termios()
1322 	port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core;  in qcom_geni_serial_set_termios()
1323 	port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud);  in qcom_geni_serial_set_termios()
1324 	geni_icc_set_bw(&port->se);  in qcom_geni_serial_set_termios()
1461 static void __init qcom_geni_serial_enable_early_read(struct geni_se *se,  in qcom_geni_serial_enable_early_read()  argument
1464 	geni_se_setup_s_cmd(se, UART_START_READ, 0);  in qcom_geni_serial_enable_early_read()
1468 static inline void qcom_geni_serial_enable_early_read(struct geni_se *se,  in qcom_geni_serial_enable_early_read()  argument
1484 	struct geni_se se;  in qcom_geni_serial_earlycon_setup()  local
1491 	memset(&se, 0, sizeof(se));  in qcom_geni_serial_earlycon_setup()
1492 	se.base = uport->membase;  in qcom_geni_serial_earlycon_setup()
1493 	if (geni_se_read_proto(&se) != GENI_SE_UART)  in qcom_geni_serial_earlycon_setup()
1508 	geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,  in qcom_geni_serial_earlycon_setup()
1510 	geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);  in qcom_geni_serial_earlycon_setup()
1511 	geni_se_select_mode(&se, GENI_SE_FIFO);  in qcom_geni_serial_earlycon_setup()
1523 	qcom_geni_serial_enable_early_read(&se, dev->con);  in qcom_geni_serial_earlycon_setup()
1585 		geni_icc_enable(&port->se);  in qcom_geni_serial_pm()
1588 		geni_se_resources_on(&port->se);  in qcom_geni_serial_pm()
1591 		geni_se_resources_off(&port->se);  in qcom_geni_serial_pm()
1593 		geni_icc_disable(&port->se);  in qcom_geni_serial_pm()
1675 	port->se.dev = &pdev->dev;  in qcom_geni_serial_probe()
1676 	port->se.wrapper = dev_get_drvdata(pdev->dev.parent);  in qcom_geni_serial_probe()
1677 	port->se.clk = devm_clk_get(&pdev->dev, "se");  in qcom_geni_serial_probe()
1678 	if (IS_ERR(port->se.clk)) {  in qcom_geni_serial_probe()
1679 		ret = PTR_ERR(port->se.clk);  in qcom_geni_serial_probe()
1700 	ret = geni_icc_get(&port->se, NULL);  in qcom_geni_serial_probe()
1703 	port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;  in qcom_geni_serial_probe()
1704 	port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;  in qcom_geni_serial_probe()
1707 	ret = geni_icc_set_bw(&port->se);  in qcom_geni_serial_probe()
1793 		geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ACTIVE_ONLY);  in qcom_geni_serial_suspend()
1794 		geni_icc_set_bw(&port->se);  in qcom_geni_serial_suspend()
1808 		geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS);  in qcom_geni_serial_resume()
1809 		geni_icc_set_bw(&port->se);  in qcom_geni_serial_resume()