tty/serial/pmac_zilog.h

1 /* SPDX-License-Identifier: GPL-2.0 */
25 	 * of "escc" node (ie. ch-a or ch-b)
64 	if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A)  in pmz_get_port_A()
66 	return uap->mate;  in pmz_get_port_A()
78 		writeb(reg, port->control_reg);  in read_zsreg()
79 	return readb(port->control_reg);  in read_zsreg()
85 		writeb(reg, port->control_reg);  in write_zsreg()
86 	writeb(value, port->control_reg);  in write_zsreg()
91 	return readb(port->data_reg);  in read_zsdata()
96 	writeb(data, port->data_reg);  in write_zsdata()
101 	(void)readb(port->control_reg);  in zssync()
108 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
144 #define	RES_Rx_CRC	0x40	/* Reset Rx CRC Checker */
150 #define	EXT_INT_ENAB	0x1	/* Ext Int Enable */
151 #define	TxINT_ENAB	0x2	/* Tx Int Enable */
154 #define	RxINT_DISAB	0	/* Rx Int Disable */
155 #define	RxINT_FCERR	0x8	/* Rx Int on First Character Only or Error */
156 #define	INT_ALL_Rx	0x10	/* Int on all Rx Characters or error */
162 #define	WT_RDY_ENAB	0x80	/* Enable W/Req pin */
168 #define	RxENABLE	0x1	/* Rx Enable */
171 #define	RxCRC_ENAB	0x8	/* Rx CRC Enable */
174 #define	Rx5		0x0	/* Rx 5 Bits/Character */
175 #define	Rx7		0x40	/* Rx 7 Bits/Character */
176 #define	Rx6		0x80	/* Rx 6 Bits/Character */
177 #define	Rx8		0xc0	/* Rx 8 Bits/Character */
182 #define	PAR_ENAB	0x1	/* Parity Enable */
185 #define	SYNC_ENAB	0	/* Sync Modes Enable */
204 #define	TxCRC_ENAB	0x1	/* Tx CRC Enable */
206 #define	SDLC_CRC	0x4	/* SDLC/CRC-16 */
207 #define	TxENABLE	0x8	/* Tx Enable */
216 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
218 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
221 #define	ENEXREAD	0x40	/* Enable read of some write registers */
229 #define	MIE	8	/* Master Interrupt Enable */
269 #define	BRENAB	1	/* Baud rate generator enable */
283 #define	EN85C30	1	/* Enable some 85c30-enhanced registers */
285 #define	ENSTFIFO 4	/* Enable status FIFO (SDLC) */
294 #define	Rx_CH_AV	0x1	/* Rx Character Available */
305 /* Residue Data for 8 Rx bits/char programmed */
314 /* Special Rx Condition Interrupts */
316 #define	Rx_OVR		0x20	/* Rx Overrun Error */
320 /* Read Register 2 (channel b only) - Interrupt vector */
334 #define	CHBRxIP	0x4		/* Channel B Rx IP */
337 #define	CHARxIP	0x20		/* Channel A Rx IP */
361 #define ZS_IS_CONS(UP)			((UP)->flags & PMACZILOG_FLAG_IS_CONS)
362 #define ZS_IS_KGDB(UP)			((UP)->flags & PMACZILOG_FLAG_IS_KGDB)
363 #define ZS_IS_CHANNEL_A(UP)		((UP)->flags & PMACZILOG_FLAG_IS_CHANNEL_A)
364 #define ZS_REGS_HELD(UP)		((UP)->flags & PMACZILOG_FLAG_REGS_HELD)
365 #define ZS_TX_STOPPED(UP)		((UP)->flags & PMACZILOG_FLAG_TX_STOPPED)
366 #define ZS_TX_ACTIVE(UP)		((UP)->flags & PMACZILOG_FLAG_TX_ACTIVE)
367 #define ZS_WANTS_MODEM_STATUS(UP)	((UP)->flags & PMACZILOG_FLAG_MODEM_STATUS)
368 #define ZS_IS_IRDA(UP)			((UP)->flags & PMACZILOG_FLAG_IS_IRDA)
369 #define ZS_IS_INTMODEM(UP)		((UP)->flags & PMACZILOG_FLAG_IS_INTMODEM)
370 #define ZS_IS_OPEN(UP)			((UP)->flags & PMACZILOG_FLAG_IS_OPEN)
371 #define ZS_IS_EXTCLK(UP)		((UP)->flags & PMACZILOG_FLAG_IS_EXTCLK)