tty/serial/pmac_zilog.h

1 /* SPDX-License-Identifier: GPL-2.0 */
25 	 * of "escc" node (ie. ch-a or ch-b)
64 	if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A)  in pmz_get_port_A()
66 	return uap->mate;  in pmz_get_port_A()
78 		writeb(reg, port->control_reg);  in read_zsreg()
79 	return readb(port->control_reg);  in read_zsreg()
85 		writeb(reg, port->control_reg);  in write_zsreg()
86 	writeb(value, port->control_reg);  in write_zsreg()
91 	return readb(port->data_reg);  in read_zsdata()
96 	writeb(data, port->data_reg);  in write_zsdata()
101 	(void)readb(port->control_reg);  in zssync()
108 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
137 #define	RES_EXT_INT	0x10	/* Reset Ext. Status Interrupts */
139 #define	RES_RxINT_FC	0x20	/* Reset RxINT on First Character */
140 #define	RES_Tx_P	0x28	/* Reset TxINT Pending */
141 #define	ERR_RES		0x30	/* Error Reset */
142 #define	RES_H_IUS	0x38	/* Reset highest IUS */
144 #define	RES_Rx_CRC	0x40	/* Reset Rx CRC Checker */
145 #define	RES_Tx_CRC	0x80	/* Reset Tx CRC Checker */
146 #define	RES_EOM_L	0xC0	/* Reset EOM latch */
150 #define	EXT_INT_ENAB	0x1	/* Ext Int Enable */
206 #define	SDLC_CRC	0x4	/* SDLC/CRC-16 */
216 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
218 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
231 #define	NORESET	0	/* No reset on write to R9 */
232 #define	CHRB	0x40	/* Reset channel B */
233 #define	CHRA	0x80	/* Reset channel A */
234 #define	FHWRES	0xc0	/* Force hardware reset */
249 #define	TRxCXT	0	/* TRxC = Xtal output */
251 #define	TRxCBR	2	/* TRxC = BR Generator Output */
252 #define	TRxCDP	3	/* TRxC = DPLL output */
256 #define	TCBR	0x10	/* Transmit clock = BR Generator output */
257 #define	TCDPLL	0x18	/* Transmit clock = DPLL output */
260 #define	RCBR	0x40	/* Receive clock = BR Generator output */
261 #define	RCDPLL	0x60	/* Receive clock = DPLL output */
275 #define	RMC	0x40	/* Reset missing clock */
283 #define	EN85C30	1	/* Enable some 85c30-enhanced registers */
320 /* Read Register 2 (channel b only) - Interrupt vector */
332 #define	CHBEXT	0x1		/* Channel B Ext/Stat IP */
335 #define	CHAEXT	0x8		/* Channel A Ext/Stat IP */
361 #define ZS_IS_CONS(UP)			((UP)->flags & PMACZILOG_FLAG_IS_CONS)
362 #define ZS_IS_KGDB(UP)			((UP)->flags & PMACZILOG_FLAG_IS_KGDB)
363 #define ZS_IS_CHANNEL_A(UP)		((UP)->flags & PMACZILOG_FLAG_IS_CHANNEL_A)
364 #define ZS_REGS_HELD(UP)		((UP)->flags & PMACZILOG_FLAG_REGS_HELD)
365 #define ZS_TX_STOPPED(UP)		((UP)->flags & PMACZILOG_FLAG_TX_STOPPED)
366 #define ZS_TX_ACTIVE(UP)		((UP)->flags & PMACZILOG_FLAG_TX_ACTIVE)
367 #define ZS_WANTS_MODEM_STATUS(UP)	((UP)->flags & PMACZILOG_FLAG_MODEM_STATUS)
368 #define ZS_IS_IRDA(UP)			((UP)->flags & PMACZILOG_FLAG_IS_IRDA)
369 #define ZS_IS_INTMODEM(UP)		((UP)->flags & PMACZILOG_FLAG_IS_INTMODEM)
370 #define ZS_IS_OPEN(UP)			((UP)->flags & PMACZILOG_FLAG_IS_OPEN)
371 #define ZS_IS_EXTCLK(UP)		((UP)->flags & PMACZILOG_FLAG_IS_EXTCLK)