1063 	struct mvebu_uart_clock_base *uart_clock_base =  in mvebu_uart_clock_prepare()  local
1089 	if (uart_clock_base->configured) {  in mvebu_uart_clock_prepare()
1094 	parent_clock_idx = uart_clock_base->parent_idx;  in mvebu_uart_clock_prepare()
1095 	parent_clock_rate = uart_clock_base->parent_rates[parent_clock_idx];  in mvebu_uart_clock_prepare()
1097 	val = readl(uart_clock_base->reg1);  in mvebu_uart_clock_prepare()
1099 	if (uart_clock_base->div > CLK_TBG_DIV1_MAX) {  in mvebu_uart_clock_prepare()
1101 		d2 = uart_clock_base->div / CLK_TBG_DIV1_MAX;  in mvebu_uart_clock_prepare()
1103 		d1 = uart_clock_base->div;  in mvebu_uart_clock_prepare()
1117 	prev_clock_rate = uart_clock_base->parent_rates[prev_clock_idx];  in mvebu_uart_clock_prepare()
1145 	writel(val, uart_clock_base->reg1);  in mvebu_uart_clock_prepare()
1149 		val = readl(uart_clock_base->reg2);  in mvebu_uart_clock_prepare()
1158 		writel(val, uart_clock_base->reg2);  in mvebu_uart_clock_prepare()
1161 	uart_clock_base->configured = true;  in mvebu_uart_clock_prepare()
1171 	struct mvebu_uart_clock_base *uart_clock_base =  in mvebu_uart_clock_enable()  local
1178 	val = readl(uart_clock_base->reg1);  in mvebu_uart_clock_enable()
1185 	writel(val, uart_clock_base->reg1);  in mvebu_uart_clock_enable()
1195 	struct mvebu_uart_clock_base *uart_clock_base =  in mvebu_uart_clock_disable()  local
1202 	val = readl(uart_clock_base->reg1);  in mvebu_uart_clock_disable()
1209 	writel(val, uart_clock_base->reg1);  in mvebu_uart_clock_disable()
1217 	struct mvebu_uart_clock_base *uart_clock_base =  in mvebu_uart_clock_is_enabled()  local
1221 	val = readl(uart_clock_base->reg1);  in mvebu_uart_clock_is_enabled()
1232 	struct mvebu_uart_clock_base *uart_clock_base =  in mvebu_uart_clock_save_context()  local
1237 	uart_clock->pm_context_reg1 = readl(uart_clock_base->reg1);  in mvebu_uart_clock_save_context()
1238 	uart_clock->pm_context_reg2 = readl(uart_clock_base->reg2);  in mvebu_uart_clock_save_context()
1247 	struct mvebu_uart_clock_base *uart_clock_base =  in mvebu_uart_clock_restore_context()  local
1252 	writel(uart_clock->pm_context_reg1, uart_clock_base->reg1);  in mvebu_uart_clock_restore_context()
1253 	writel(uart_clock->pm_context_reg2, uart_clock_base->reg2);  in mvebu_uart_clock_restore_context()
1261 	struct mvebu_uart_clock_base *uart_clock_base =  in mvebu_uart_clock_recalc_rate()  local
1264 	return parent_rate / uart_clock_base->div;  in mvebu_uart_clock_recalc_rate()
1271 	struct mvebu_uart_clock_base *uart_clock_base =  in mvebu_uart_clock_round_rate()  local
1274 	return *parent_rate / uart_clock_base->div;  in mvebu_uart_clock_round_rate()
1326 	struct mvebu_uart_clock_base *uart_clock_base;  in mvebu_uart_clock_probe()  local
1335 		     ARRAY_SIZE(uart_clock_base->clocks));  in mvebu_uart_clock_probe()
1337 		     ARRAY_SIZE(uart_clock_base->parent_rates));  in mvebu_uart_clock_probe()
1339 	uart_clock_base = devm_kzalloc(dev,  in mvebu_uart_clock_probe()
1340 				       sizeof(*uart_clock_base),  in mvebu_uart_clock_probe()
1342 	if (!uart_clock_base)  in mvebu_uart_clock_probe()
1359 	uart_clock_base->reg1 = devm_ioremap(dev, res->start,  in mvebu_uart_clock_probe()
1361 	if (!uart_clock_base->reg1)  in mvebu_uart_clock_probe()
1378 	uart_clock_base->reg2 = devm_ioremap(dev, res->start,  in mvebu_uart_clock_probe()
1380 	if (!uart_clock_base->reg2)  in mvebu_uart_clock_probe()
1392 		hw_clk_data->hws[i] = &uart_clock_base->clocks[i].clk_hw;  in mvebu_uart_clock_probe()
1393 		uart_clock_base->clocks[i].clock_idx = i;  in mvebu_uart_clock_probe()
1415 		uart_clock_base->parent_rates[i] = rate;  in mvebu_uart_clock_probe()
1471 	uart_clock_base->parent_idx = parent_clk_idx;  in mvebu_uart_clock_probe()
1472 	uart_clock_base->div = div;  in mvebu_uart_clock_probe()
1479 				&uart_clock_base->clocks[i],  in mvebu_uart_clock_probe()