Lines Matching refs:membase
191 st = readl(port->membase + UART_STAT); in mvebu_uart_tx_empty()
213 unsigned int ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_stop_tx()
216 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_stop_tx()
225 writel(c, port->membase + UART_TSH(port)); in mvebu_uart_start_tx()
227 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_start_tx()
229 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_start_tx()
236 ctl = readl(port->membase + UART_CTRL(port)); in mvebu_uart_stop_rx()
238 writel(ctl, port->membase + UART_CTRL(port)); in mvebu_uart_stop_rx()
240 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_stop_rx()
242 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_stop_rx()
251 ctl = readl(port->membase + UART_CTRL(port)); in mvebu_uart_break_ctl()
256 writel(ctl, port->membase + UART_CTRL(port)); in mvebu_uart_break_ctl()
269 ch = readl(port->membase + UART_RBR(port)); in mvebu_uart_rx_chars()
283 ret = readl(port->membase + UART_STAT); in mvebu_uart_rx_chars()
285 writel(ret, port->membase + UART_STAT); in mvebu_uart_rx_chars()
327 status = readl(port->membase + UART_STAT); in mvebu_uart_rx_chars()
338 !(readl(port->membase + UART_STAT) & STAT_TX_FIFO_FUL), in mvebu_uart_tx_chars()
339 writel(ch, port->membase + UART_TSH(port)), in mvebu_uart_tx_chars()
346 unsigned int st = readl(port->membase + UART_STAT); in mvebu_uart_isr()
361 unsigned int st = readl(port->membase + UART_STAT); in mvebu_uart_rx_isr()
373 unsigned int st = readl(port->membase + UART_STAT); in mvebu_uart_tx_isr()
388 port->membase + UART_CTRL(port)); in mvebu_uart_startup()
392 ret = readl(port->membase + UART_STAT); in mvebu_uart_startup()
394 writel(ret, port->membase + UART_STAT); in mvebu_uart_startup()
396 writel(CTRL_BRK_INT, port->membase + UART_CTRL(port)); in mvebu_uart_startup()
398 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_startup()
400 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_startup()
443 writel(0, port->membase + UART_INTR(port)); in mvebu_uart_shutdown()
518 brdv = readl(port->membase + UART_BRDV); in mvebu_uart_baud_rate_set()
521 writel(brdv, port->membase + UART_BRDV); in mvebu_uart_baud_rate_set()
524 osamp = readl(port->membase + UART_OSAMP); in mvebu_uart_baud_rate_set()
529 writel(osamp, port->membase + UART_OSAMP); in mvebu_uart_baud_rate_set()
611 unsigned int st = readl(port->membase + UART_STAT); in mvebu_uart_get_poll_char()
616 return readl(port->membase + UART_RBR(port)); in mvebu_uart_get_poll_char()
624 st = readl(port->membase + UART_STAT); in mvebu_uart_put_poll_char()
632 writel(c, port->membase + UART_TSH(port)); in mvebu_uart_put_poll_char()
665 st = readl(port->membase + UART_STAT); in mvebu_uart_putc()
671 writel(c, port->membase + UART_STD_TSH); in mvebu_uart_putc()
674 st = readl(port->membase + UART_STAT); in mvebu_uart_putc()
693 if (!device->port.membase) in mvebu_uart_early_console_setup()
709 readl_poll_timeout_atomic(port->membase + UART_STAT, val, in wait_for_xmitr()
717 readl_poll_timeout_atomic(port->membase + UART_STAT, val, in wait_for_xmite()
724 writel(ch, port->membase + UART_TSH(port)); in mvebu_uart_console_putchar()
740 ier = readl(port->membase + UART_CTRL(port)) & CTRL_BRK_INT; in mvebu_uart_console_write()
741 intr = readl(port->membase + UART_INTR(port)) & in mvebu_uart_console_write()
743 writel(0, port->membase + UART_CTRL(port)); in mvebu_uart_console_write()
744 writel(0, port->membase + UART_INTR(port)); in mvebu_uart_console_write()
751 writel(ier, port->membase + UART_CTRL(port)); in mvebu_uart_console_write()
754 ctl = intr | readl(port->membase + UART_INTR(port)); in mvebu_uart_console_write()
755 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_console_write()
775 if (!port->mapbase || !port->membase) { in mvebu_uart_console_setup()
828 mvuart->pm_regs.rbr = readl(port->membase + UART_RBR(port)); in mvebu_uart_suspend()
829 mvuart->pm_regs.tsh = readl(port->membase + UART_TSH(port)); in mvebu_uart_suspend()
830 mvuart->pm_regs.ctrl = readl(port->membase + UART_CTRL(port)); in mvebu_uart_suspend()
831 mvuart->pm_regs.intr = readl(port->membase + UART_INTR(port)); in mvebu_uart_suspend()
832 mvuart->pm_regs.stat = readl(port->membase + UART_STAT); in mvebu_uart_suspend()
834 mvuart->pm_regs.brdv = readl(port->membase + UART_BRDV); in mvebu_uart_suspend()
836 mvuart->pm_regs.osamp = readl(port->membase + UART_OSAMP); in mvebu_uart_suspend()
849 writel(mvuart->pm_regs.rbr, port->membase + UART_RBR(port)); in mvebu_uart_resume()
850 writel(mvuart->pm_regs.tsh, port->membase + UART_TSH(port)); in mvebu_uart_resume()
851 writel(mvuart->pm_regs.ctrl, port->membase + UART_CTRL(port)); in mvebu_uart_resume()
852 writel(mvuart->pm_regs.intr, port->membase + UART_INTR(port)); in mvebu_uart_resume()
853 writel(mvuart->pm_regs.stat, port->membase + UART_STAT); in mvebu_uart_resume()
855 writel(mvuart->pm_regs.brdv, port->membase + UART_BRDV); in mvebu_uart_resume()
857 writel(mvuart->pm_regs.osamp, port->membase + UART_OSAMP); in mvebu_uart_resume()
919 port->membase = devm_platform_get_and_ioremap_resource(pdev, 0, ®); in mvebu_uart_probe()
920 if (IS_ERR(port->membase)) in mvebu_uart_probe()
921 return PTR_ERR(port->membase); in mvebu_uart_probe()
979 writel(CTRL_SOFT_RST, port->membase + UART_CTRL(port)); in mvebu_uart_probe()
981 writel(0, port->membase + UART_CTRL(port)); in mvebu_uart_probe()