Lines Matching +full:tbg +full:- +full:a +full:- +full:s
1 // SPDX-License-Identifier: GPL-2.0+
4 * Marvell Armada-3700 Serial Driver
11 #include <linux/clk-provider.h>
77 * error in Marvell's documentation. Hence following CLK_DIS macros are swapped.
106 #define MVEBU_UART_TYPE "mvebu-uart"
134 /* Driver data, a structure for each UART port */
165 return (struct mvebu_uart *)port->private_data; in to_mvuart()
168 #define IS_EXTENDED(port) (to_mvuart(port)->data->is_ext)
170 #define UART_RBR(port) (to_mvuart(port)->data->regs.rbr)
171 #define UART_TSH(port) (to_mvuart(port)->data->regs.tsh)
172 #define UART_CTRL(port) (to_mvuart(port)->data->regs.ctrl)
173 #define UART_INTR(port) (to_mvuart(port)->data->regs.intr)
175 #define CTRL_TX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_tx_rdy_int)
176 #define CTRL_RX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_rx_rdy_int)
177 #define STAT_TX_RDY(port) (to_mvuart(port)->data->flags.stat_tx_rdy)
178 #define STAT_RX_RDY(port) (to_mvuart(port)->data->flags.stat_rx_rdy)
191 st = readl(port->membase + UART_STAT); in mvebu_uart_tx_empty()
213 unsigned int ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_stop_tx()
216 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_stop_tx()
225 writel(c, port->membase + UART_TSH(port)); in mvebu_uart_start_tx()
227 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_start_tx()
229 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_start_tx()
236 ctl = readl(port->membase + UART_CTRL(port)); in mvebu_uart_stop_rx()
238 writel(ctl, port->membase + UART_CTRL(port)); in mvebu_uart_stop_rx()
240 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_stop_rx()
242 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_stop_rx()
251 ctl = readl(port->membase + UART_CTRL(port)); in mvebu_uart_break_ctl()
252 if (brk == -1) in mvebu_uart_break_ctl()
256 writel(ctl, port->membase + UART_CTRL(port)); in mvebu_uart_break_ctl()
262 struct tty_port *tport = &port->state->port; in mvebu_uart_rx_chars()
269 ch = readl(port->membase + UART_RBR(port)); in mvebu_uart_rx_chars()
272 port->icount.rx++; in mvebu_uart_rx_chars()
275 port->icount.parity++; in mvebu_uart_rx_chars()
283 ret = readl(port->membase + UART_STAT); in mvebu_uart_rx_chars()
285 writel(ret, port->membase + UART_STAT); in mvebu_uart_rx_chars()
289 port->icount.brk++; in mvebu_uart_rx_chars()
296 port->icount.overrun++; in mvebu_uart_rx_chars()
299 port->icount.frame++; in mvebu_uart_rx_chars()
304 if (status & port->ignore_status_mask & STAT_PAR_ERR) in mvebu_uart_rx_chars()
307 status &= port->read_status_mask; in mvebu_uart_rx_chars()
312 status &= ~port->ignore_status_mask; in mvebu_uart_rx_chars()
327 status = readl(port->membase + UART_STAT); in mvebu_uart_rx_chars()
337 uart_port_tx_limited(port, ch, port->fifosize, in mvebu_uart_tx_chars()
338 !(readl(port->membase + UART_STAT) & STAT_TX_FIFO_FUL), in mvebu_uart_tx_chars()
339 writel(ch, port->membase + UART_TSH(port)), in mvebu_uart_tx_chars()
346 unsigned int st = readl(port->membase + UART_STAT); in mvebu_uart_isr()
361 unsigned int st = readl(port->membase + UART_STAT); in mvebu_uart_rx_isr()
373 unsigned int st = readl(port->membase + UART_STAT); in mvebu_uart_tx_isr()
388 port->membase + UART_CTRL(port)); in mvebu_uart_startup()
392 ret = readl(port->membase + UART_STAT); in mvebu_uart_startup()
394 writel(ret, port->membase + UART_STAT); in mvebu_uart_startup()
396 writel(CTRL_BRK_INT, port->membase + UART_CTRL(port)); in mvebu_uart_startup()
398 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_startup()
400 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_startup()
402 if (!mvuart->irq[UART_TX_IRQ]) { in mvebu_uart_startup()
404 ret = devm_request_irq(port->dev, mvuart->irq[UART_IRQ_SUM], in mvebu_uart_startup()
405 mvebu_uart_isr, port->irqflags, in mvebu_uart_startup()
406 dev_name(port->dev), port); in mvebu_uart_startup()
408 dev_err(port->dev, "unable to request IRQ %d\n", in mvebu_uart_startup()
409 mvuart->irq[UART_IRQ_SUM]); in mvebu_uart_startup()
414 ret = devm_request_irq(port->dev, mvuart->irq[UART_RX_IRQ], in mvebu_uart_startup()
415 mvebu_uart_rx_isr, port->irqflags, in mvebu_uart_startup()
416 dev_name(port->dev), port); in mvebu_uart_startup()
418 dev_err(port->dev, "unable to request IRQ %d\n", in mvebu_uart_startup()
419 mvuart->irq[UART_RX_IRQ]); in mvebu_uart_startup()
423 ret = devm_request_irq(port->dev, mvuart->irq[UART_TX_IRQ], in mvebu_uart_startup()
424 mvebu_uart_tx_isr, port->irqflags, in mvebu_uart_startup()
425 dev_name(port->dev), in mvebu_uart_startup()
428 dev_err(port->dev, "unable to request IRQ %d\n", in mvebu_uart_startup()
429 mvuart->irq[UART_TX_IRQ]); in mvebu_uart_startup()
430 devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ], in mvebu_uart_startup()
443 writel(0, port->membase + UART_INTR(port)); in mvebu_uart_shutdown()
445 if (!mvuart->irq[UART_TX_IRQ]) { in mvebu_uart_shutdown()
446 devm_free_irq(port->dev, mvuart->irq[UART_IRQ_SUM], port); in mvebu_uart_shutdown()
448 devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ], port); in mvebu_uart_shutdown()
449 devm_free_irq(port->dev, mvuart->irq[UART_TX_IRQ], port); in mvebu_uart_shutdown()
459 if (!port->uartclk) in mvebu_uart_baud_rate_set()
464 * > d1 * d2 ("TBG divisors"): can divide only TBG clock from 1 to 6 in mvebu_uart_baud_rate_set()
466 * > M ("fractional divisor"): allows a better accuracy (from 1 to 63) in mvebu_uart_baud_rate_set()
472 * baudrate = tbg / (d1 * d2 * d * 16) in mvebu_uart_baud_rate_set()
476 * baudrate = 10 * tbg / (d1*d2 * d * (3 * (m1 + m2) + 2 * (m3 + m4))) in mvebu_uart_baud_rate_set()
494 * Member port->uartclk is either xtal clock rate or TBG clock rate in mvebu_uart_baud_rate_set()
501 d_divisor = DIV_ROUND_CLOSEST(port->uartclk, baud * m_divisor); in mvebu_uart_baud_rate_set()
509 d_divisor = DIV_ROUND_CLOSEST(port->uartclk, baud * m_divisor); in mvebu_uart_baud_rate_set()
518 brdv = readl(port->membase + UART_BRDV); in mvebu_uart_baud_rate_set()
521 writel(brdv, port->membase + UART_BRDV); in mvebu_uart_baud_rate_set()
524 osamp = readl(port->membase + UART_OSAMP); in mvebu_uart_baud_rate_set()
529 writel(osamp, port->membase + UART_OSAMP); in mvebu_uart_baud_rate_set()
531 return DIV_ROUND_CLOSEST(port->uartclk, d_divisor * m_divisor); in mvebu_uart_baud_rate_set()
543 port->read_status_mask = STAT_RX_RDY(port) | STAT_OVR_ERR | in mvebu_uart_set_termios()
546 if (termios->c_iflag & INPCK) in mvebu_uart_set_termios()
547 port->read_status_mask |= STAT_FRM_ERR | STAT_PAR_ERR; in mvebu_uart_set_termios()
549 port->ignore_status_mask = 0; in mvebu_uart_set_termios()
550 if (termios->c_iflag & IGNPAR) in mvebu_uart_set_termios()
551 port->ignore_status_mask |= in mvebu_uart_set_termios()
554 if ((termios->c_cflag & CREAD) == 0) in mvebu_uart_set_termios()
555 port->ignore_status_mask |= STAT_RX_RDY(port) | STAT_BRK_ERR; in mvebu_uart_set_termios()
561 * rate. If port->uartclk is not available, then in mvebu_uart_set_termios()
565 min_baud = DIV_ROUND_UP(port->uartclk, BRDV_BAUD_MAX * in mvebu_uart_set_termios()
567 max_baud = port->uartclk / 80; in mvebu_uart_set_termios()
578 termios->c_iflag &= INPCK | IGNPAR; in mvebu_uart_set_termios()
579 termios->c_iflag |= old->c_iflag & ~(INPCK | IGNPAR); in mvebu_uart_set_termios()
580 termios->c_cflag &= CREAD | CBAUD; in mvebu_uart_set_termios()
581 termios->c_cflag |= old->c_cflag & ~(CREAD | CBAUD); in mvebu_uart_set_termios()
582 termios->c_cflag |= CS8; in mvebu_uart_set_termios()
587 uart_update_timeout(port, termios->c_cflag, baud); in mvebu_uart_set_termios()
611 unsigned int st = readl(port->membase + UART_STAT); in mvebu_uart_get_poll_char()
616 return readl(port->membase + UART_RBR(port)); in mvebu_uart_get_poll_char()
624 st = readl(port->membase + UART_STAT); in mvebu_uart_put_poll_char()
632 writel(c, port->membase + UART_TSH(port)); in mvebu_uart_put_poll_char()
665 st = readl(port->membase + UART_STAT); in mvebu_uart_putc()
671 writel(c, port->membase + UART_STD_TSH); in mvebu_uart_putc()
674 st = readl(port->membase + UART_STAT); in mvebu_uart_putc()
681 const char *s, in mvebu_uart_putc_early_write() argument
684 struct earlycon_device *dev = con->data; in mvebu_uart_putc_early_write()
686 uart_console_write(&dev->port, s, n, mvebu_uart_putc); in mvebu_uart_putc_early_write()
693 if (!device->port.membase) in mvebu_uart_early_console_setup()
694 return -ENODEV; in mvebu_uart_early_console_setup()
696 device->con->write = mvebu_uart_putc_early_write; in mvebu_uart_early_console_setup()
702 OF_EARLYCON_DECLARE(ar3700_uart, "marvell,armada-3700-uart",
709 readl_poll_timeout_atomic(port->membase + UART_STAT, val, in wait_for_xmitr()
717 readl_poll_timeout_atomic(port->membase + UART_STAT, val, in wait_for_xmite()
724 writel(ch, port->membase + UART_TSH(port)); in mvebu_uart_console_putchar()
727 static void mvebu_uart_console_write(struct console *co, const char *s, in mvebu_uart_console_write() argument
730 struct uart_port *port = &mvebu_uart_ports[co->index]; in mvebu_uart_console_write()
740 ier = readl(port->membase + UART_CTRL(port)) & CTRL_BRK_INT; in mvebu_uart_console_write()
741 intr = readl(port->membase + UART_INTR(port)) & in mvebu_uart_console_write()
743 writel(0, port->membase + UART_CTRL(port)); in mvebu_uart_console_write()
744 writel(0, port->membase + UART_INTR(port)); in mvebu_uart_console_write()
746 uart_console_write(port, s, count, mvebu_uart_console_putchar); in mvebu_uart_console_write()
751 writel(ier, port->membase + UART_CTRL(port)); in mvebu_uart_console_write()
754 ctl = intr | readl(port->membase + UART_INTR(port)); in mvebu_uart_console_write()
755 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_console_write()
770 if (co->index < 0 || co->index >= MVEBU_NR_UARTS) in mvebu_uart_console_setup()
771 return -EINVAL; in mvebu_uart_console_setup()
773 port = &mvebu_uart_ports[co->index]; in mvebu_uart_console_setup()
775 if (!port->mapbase || !port->membase) { in mvebu_uart_console_setup()
776 pr_debug("console on ttyMV%i not present\n", co->index); in mvebu_uart_console_setup()
777 return -ENODEV; in mvebu_uart_console_setup()
794 .index = -1,
823 struct uart_port *port = mvuart->port; in mvebu_uart_suspend()
828 mvuart->pm_regs.rbr = readl(port->membase + UART_RBR(port)); in mvebu_uart_suspend()
829 mvuart->pm_regs.tsh = readl(port->membase + UART_TSH(port)); in mvebu_uart_suspend()
830 mvuart->pm_regs.ctrl = readl(port->membase + UART_CTRL(port)); in mvebu_uart_suspend()
831 mvuart->pm_regs.intr = readl(port->membase + UART_INTR(port)); in mvebu_uart_suspend()
832 mvuart->pm_regs.stat = readl(port->membase + UART_STAT); in mvebu_uart_suspend()
834 mvuart->pm_regs.brdv = readl(port->membase + UART_BRDV); in mvebu_uart_suspend()
836 mvuart->pm_regs.osamp = readl(port->membase + UART_OSAMP); in mvebu_uart_suspend()
846 struct uart_port *port = mvuart->port; in mvebu_uart_resume()
849 writel(mvuart->pm_regs.rbr, port->membase + UART_RBR(port)); in mvebu_uart_resume()
850 writel(mvuart->pm_regs.tsh, port->membase + UART_TSH(port)); in mvebu_uart_resume()
851 writel(mvuart->pm_regs.ctrl, port->membase + UART_CTRL(port)); in mvebu_uart_resume()
852 writel(mvuart->pm_regs.intr, port->membase + UART_INTR(port)); in mvebu_uart_resume()
853 writel(mvuart->pm_regs.stat, port->membase + UART_STAT); in mvebu_uart_resume()
855 writel(mvuart->pm_regs.brdv, port->membase + UART_BRDV); in mvebu_uart_resume()
857 writel(mvuart->pm_regs.osamp, port->membase + UART_OSAMP); in mvebu_uart_resume()
878 &pdev->dev); in mvebu_uart_probe()
884 /* Assume that all UART ports have a DT alias or none has */ in mvebu_uart_probe()
885 id = of_alias_get_id(pdev->dev.of_node, "serial"); in mvebu_uart_probe()
886 if (!pdev->dev.of_node || id < 0) in mvebu_uart_probe()
887 pdev->id = uart_num_counter++; in mvebu_uart_probe()
889 pdev->id = id; in mvebu_uart_probe()
891 if (pdev->id >= MVEBU_NR_UARTS) { in mvebu_uart_probe()
892 dev_err(&pdev->dev, "cannot have more than %d UART ports\n", in mvebu_uart_probe()
894 return -EINVAL; in mvebu_uart_probe()
897 port = &mvebu_uart_ports[pdev->id]; in mvebu_uart_probe()
899 spin_lock_init(&port->lock); in mvebu_uart_probe()
901 port->dev = &pdev->dev; in mvebu_uart_probe()
902 port->type = PORT_MVEBU; in mvebu_uart_probe()
903 port->ops = &mvebu_uart_ops; in mvebu_uart_probe()
904 port->regshift = 0; in mvebu_uart_probe()
906 port->fifosize = 32; in mvebu_uart_probe()
907 port->iotype = UPIO_MEM32; in mvebu_uart_probe()
908 port->flags = UPF_FIXED_PORT; in mvebu_uart_probe()
909 port->line = pdev->id; in mvebu_uart_probe()
914 * array so called ->irq[]. in mvebu_uart_probe()
916 port->irq = 0; in mvebu_uart_probe()
917 port->irqflags = 0; in mvebu_uart_probe()
919 port->membase = devm_platform_get_and_ioremap_resource(pdev, 0, ®); in mvebu_uart_probe()
920 if (IS_ERR(port->membase)) in mvebu_uart_probe()
921 return PTR_ERR(port->membase); in mvebu_uart_probe()
922 port->mapbase = reg->start; in mvebu_uart_probe()
924 mvuart = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_uart), in mvebu_uart_probe()
927 return -ENOMEM; in mvebu_uart_probe()
930 mvuart->data = (struct mvebu_uart_driver_data *)match->data; in mvebu_uart_probe()
931 mvuart->port = port; in mvebu_uart_probe()
933 port->private_data = mvuart; in mvebu_uart_probe()
937 mvuart->clk = devm_clk_get(&pdev->dev, NULL); in mvebu_uart_probe()
938 if (IS_ERR(mvuart->clk)) { in mvebu_uart_probe()
939 if (PTR_ERR(mvuart->clk) == -EPROBE_DEFER) in mvebu_uart_probe()
940 return PTR_ERR(mvuart->clk); in mvebu_uart_probe()
943 dev_err(&pdev->dev, "unable to get UART clock\n"); in mvebu_uart_probe()
944 return PTR_ERR(mvuart->clk); in mvebu_uart_probe()
947 if (!clk_prepare_enable(mvuart->clk)) in mvebu_uart_probe()
948 port->uartclk = clk_get_rate(mvuart->clk); in mvebu_uart_probe()
958 mvuart->irq[UART_IRQ_SUM] = irq; in mvebu_uart_probe()
962 * only make use of uart-rx and uart-tx interrupts, do not use in mvebu_uart_probe()
963 * uart-sum of UART0 port. in mvebu_uart_probe()
965 irq = platform_get_irq_byname(pdev, "uart-rx"); in mvebu_uart_probe()
969 mvuart->irq[UART_RX_IRQ] = irq; in mvebu_uart_probe()
971 irq = platform_get_irq_byname(pdev, "uart-tx"); in mvebu_uart_probe()
975 mvuart->irq[UART_TX_IRQ] = irq; in mvebu_uart_probe()
979 writel(CTRL_SOFT_RST, port->membase + UART_CTRL(port)); in mvebu_uart_probe()
981 writel(0, port->membase + UART_CTRL(port)); in mvebu_uart_probe()
1013 .compatible = "marvell,armada-3700-uart",
1017 .compatible = "marvell,armada-3700-uart-ext",
1026 .name = "mvebu-uart",
1035 /* This code is based on clk-fixed-factor.c driver and modified. */
1058 struct mvebu_uart_clock_base, clocks[uart_clock->clock_idx])
1078 * otherwise kernel's boot log stops working - we need to ensure that in mvebu_uart_clock_prepare()
1079 * UART baudrate does not change during this setup. It is a one time in mvebu_uart_clock_prepare()
1084 * UART_BRDV (reg1) needs to be protected by a lock. in mvebu_uart_clock_prepare()
1089 if (uart_clock_base->configured) { in mvebu_uart_clock_prepare()
1094 parent_clock_idx = uart_clock_base->parent_idx; in mvebu_uart_clock_prepare()
1095 parent_clock_rate = uart_clock_base->parent_rates[parent_clock_idx]; in mvebu_uart_clock_prepare()
1097 val = readl(uart_clock_base->reg1); in mvebu_uart_clock_prepare()
1099 if (uart_clock_base->div > CLK_TBG_DIV1_MAX) { in mvebu_uart_clock_prepare()
1101 d2 = uart_clock_base->div / CLK_TBG_DIV1_MAX; in mvebu_uart_clock_prepare()
1103 d1 = uart_clock_base->div; in mvebu_uart_clock_prepare()
1116 /* Note that uart_clock_base->parent_rates[i] may not be available */ in mvebu_uart_clock_prepare()
1117 prev_clock_rate = uart_clock_base->parent_rates[prev_clock_idx]; in mvebu_uart_clock_prepare()
1132 /* Do not use XTAL, select TBG clock and TBG d1 * d2 divisors */ in mvebu_uart_clock_prepare()
1141 /* Use XTAL, TBG bits are then ignored */ in mvebu_uart_clock_prepare()
1145 writel(val, uart_clock_base->reg1); in mvebu_uart_clock_prepare()
1149 val = readl(uart_clock_base->reg2); in mvebu_uart_clock_prepare()
1158 writel(val, uart_clock_base->reg2); in mvebu_uart_clock_prepare()
1161 uart_clock_base->configured = true; in mvebu_uart_clock_prepare()
1178 val = readl(uart_clock_base->reg1); in mvebu_uart_clock_enable()
1180 if (uart_clock->clock_idx == 0) in mvebu_uart_clock_enable()
1185 writel(val, uart_clock_base->reg1); in mvebu_uart_clock_enable()
1202 val = readl(uart_clock_base->reg1); in mvebu_uart_clock_disable()
1204 if (uart_clock->clock_idx == 0) in mvebu_uart_clock_disable()
1209 writel(val, uart_clock_base->reg1); in mvebu_uart_clock_disable()
1221 val = readl(uart_clock_base->reg1); in mvebu_uart_clock_is_enabled()
1223 if (uart_clock->clock_idx == 0) in mvebu_uart_clock_is_enabled()
1237 uart_clock->pm_context_reg1 = readl(uart_clock_base->reg1); in mvebu_uart_clock_save_context()
1238 uart_clock->pm_context_reg2 = readl(uart_clock_base->reg2); in mvebu_uart_clock_save_context()
1252 writel(uart_clock->pm_context_reg1, uart_clock_base->reg1); in mvebu_uart_clock_restore_context()
1253 writel(uart_clock->pm_context_reg2, uart_clock_base->reg2); in mvebu_uart_clock_restore_context()
1264 return parent_rate / uart_clock_base->div; in mvebu_uart_clock_recalc_rate()
1274 return *parent_rate / uart_clock_base->div; in mvebu_uart_clock_round_rate()
1282 * mvebu_uart_clock_round_rate returns values that ensure this call is a in mvebu_uart_clock_set_rate()
1308 uart_clock->clk_hw.init = &init; in mvebu_uart_clock_register()
1316 return devm_clk_hw_register(dev, &uart_clock->clk_hw); in mvebu_uart_clock_register()
1322 static const char *const parent_clk_names[] = { "TBG-A-P", "TBG-B-P", in mvebu_uart_clock_probe()
1323 "TBG-A-S", "TBG-B-S", in mvebu_uart_clock_probe()
1328 struct device *dev = &pdev->dev; in mvebu_uart_clock_probe()
1335 ARRAY_SIZE(uart_clock_base->clocks)); in mvebu_uart_clock_probe()
1337 ARRAY_SIZE(uart_clock_base->parent_rates)); in mvebu_uart_clock_probe()
1343 return -ENOMEM; in mvebu_uart_clock_probe()
1348 return -ENOENT; in mvebu_uart_clock_probe()
1357 * by a lock shared between clock and UART driver. in mvebu_uart_clock_probe()
1359 uart_clock_base->reg1 = devm_ioremap(dev, res->start, in mvebu_uart_clock_probe()
1361 if (!uart_clock_base->reg1) in mvebu_uart_clock_probe()
1362 return -ENOMEM; in mvebu_uart_clock_probe()
1367 return -ENOENT; in mvebu_uart_clock_probe()
1375 * conflicts with UART2 driver. Access to UART_BRDV is protected by a in mvebu_uart_clock_probe()
1378 uart_clock_base->reg2 = devm_ioremap(dev, res->start, in mvebu_uart_clock_probe()
1380 if (!uart_clock_base->reg2) in mvebu_uart_clock_probe()
1381 return -ENOMEM; in mvebu_uart_clock_probe()
1388 return -ENOMEM; in mvebu_uart_clock_probe()
1390 hw_clk_data->num = ARRAY_SIZE(uart_clk_names); in mvebu_uart_clock_probe()
1392 hw_clk_data->hws[i] = &uart_clock_base->clocks[i].clk_hw; in mvebu_uart_clock_probe()
1393 uart_clock_base->clocks[i].clock_idx = i; in mvebu_uart_clock_probe()
1396 parent_clk_idx = -1; in mvebu_uart_clock_probe()
1401 if (PTR_ERR(parent_clks[i]) == -EPROBE_DEFER) in mvebu_uart_clock_probe()
1402 return -EPROBE_DEFER; in mvebu_uart_clock_probe()
1403 dev_warn(dev, "Couldn't get the parent clock %s: %ld\n", in mvebu_uart_clock_probe()
1410 dev_warn(dev, "Couldn't enable parent clock %s: %d\n", in mvebu_uart_clock_probe()
1415 uart_clock_base->parent_rates[i] = rate; in mvebu_uart_clock_probe()
1419 * Calculate the smallest TBG d1 and d2 divisors that in mvebu_uart_clock_probe()
1437 * When UART clock uses XTAL clock as a source then it in mvebu_uart_clock_probe()
1448 * Choose TBG clock source with the smallest divisors. Use XTAL in mvebu_uart_clock_probe()
1449 * clock source only in case TBG is not available as XTAL cannot in mvebu_uart_clock_probe()
1452 if (parent_clk_idx == -1 || in mvebu_uart_clock_probe()
1466 if (parent_clk_idx == -1) { in mvebu_uart_clock_probe()
1468 return -ENOENT; in mvebu_uart_clock_probe()
1471 uart_clock_base->parent_idx = parent_clk_idx; in mvebu_uart_clock_probe()
1472 uart_clock_base->div = div; in mvebu_uart_clock_probe()
1474 dev_notice(dev, "Using parent clock %s as base UART clock\n", in mvebu_uart_clock_probe()
1479 &uart_clock_base->clocks[i], in mvebu_uart_clock_probe()
1494 { .compatible = "marvell,armada-3700-uart-clock", },
1501 .name = "mvebu-uart-clock",