61 #define MSM_UART_CR				0x0010  macro
420 	msm_write(port, MSM_UART_CR_CMD_RESET_TX_READY, MSM_UART_CR);  in msm_wait_for_xmitr()
477 		msm_write(port, MSM_UART_CR_CMD_RESET_TX, MSM_UART_CR);  in msm_complete_tx_dma()
478 		msm_write(port, MSM_UART_CR_TX_ENABLE, MSM_UART_CR);  in msm_complete_tx_dma()
582 		msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR);  in msm_complete_rx_dma()
671 	msm_write(uart, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);  in msm_start_rx_dma()
672 	msm_write(uart, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);  in msm_start_rx_dma()
694 	msm_write(uart, MSM_UART_CR_CMD_RESET_RX, MSM_UART_CR);  in msm_start_rx_dma()
695 	msm_write(uart, MSM_UART_CR_RX_ENABLE, MSM_UART_CR);  in msm_start_rx_dma()
697 	msm_write(uart, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);  in msm_start_rx_dma()
699 	msm_write(uart, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);  in msm_start_rx_dma()
737 		msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR);  in msm_handle_rx_dm()
790 		msm_write(port, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);  in msm_handle_rx_dm()
792 	msm_write(port, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);  in msm_handle_rx_dm()
811 		msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR);  in msm_handle_rx()
947 	msm_write(port, MSM_UART_CR_CMD_RESET_CTS, MSM_UART_CR);  in msm_handle_delta_cts()
966 		msm_write(port, MSM_UART_CR_CMD_RESET_RXBREAK_START, MSM_UART_CR);  in msm_uart_irq()
972 			msm_write(port, val, MSM_UART_CR);  in msm_uart_irq()
974 			msm_write(port, val, MSM_UART_CR);  in msm_uart_irq()
1013 	msm_write(port, MSM_UART_CR_CMD_RESET_RX, MSM_UART_CR);  in msm_reset()
1014 	msm_write(port, MSM_UART_CR_CMD_RESET_TX, MSM_UART_CR);  in msm_reset()
1015 	msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR);  in msm_reset()
1016 	msm_write(port, MSM_UART_CR_CMD_RESET_BREAK_INT, MSM_UART_CR);  in msm_reset()
1017 	msm_write(port, MSM_UART_CR_CMD_RESET_CTS, MSM_UART_CR);  in msm_reset()
1018 	msm_write(port, MSM_UART_CR_CMD_RESET_RFR, MSM_UART_CR);  in msm_reset()
1037 		msm_write(port, MSM_UART_CR_CMD_RESET_RFR, MSM_UART_CR);  in msm_set_mctrl()
1047 		msm_write(port, MSM_UART_CR_CMD_START_BREAK, MSM_UART_CR);  in msm_break_ctl()
1049 		msm_write(port, MSM_UART_CR_CMD_STOP_BREAK, MSM_UART_CR);  in msm_break_ctl()
1170 	msm_write(port, MSM_UART_CR_CMD_PROTECTION_EN, MSM_UART_CR);  in msm_set_baud_rate()
1174 	msm_write(port, MSM_UART_CR_TX_ENABLE | MSM_UART_CR_RX_ENABLE, MSM_UART_CR);  in msm_set_baud_rate()
1183 		msm_write(port, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);  in msm_set_baud_rate()
1185 		msm_write(port, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);  in msm_set_baud_rate()
1477 			msm_write(port, MSM_UART_CR_CMD_FORCE_STALE, MSM_UART_CR);  in msm_poll_get_char_dm()
1481 			msm_write(port, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);  in msm_poll_get_char_dm()
1483 			msm_write(port, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);  in msm_poll_get_char_dm()