178 	out_be32(&PSC(port)->sicr, val);  in mpc52xx_psc_set_sicr()
427 	out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);  in mpc512x_psc_fifo_init()
428 	out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);  in mpc512x_psc_fifo_init()
429 	out_be32(&FIFO_512x(port)->txalarm, 1);  in mpc512x_psc_fifo_init()
430 	out_be32(&FIFO_512x(port)->tximr, 0);  in mpc512x_psc_fifo_init()
432 	out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);  in mpc512x_psc_fifo_init()
433 	out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);  in mpc512x_psc_fifo_init()
434 	out_be32(&FIFO_512x(port)->rxalarm, 1);  in mpc512x_psc_fifo_init()
435 	out_be32(&FIFO_512x(port)->rximr, 0);  in mpc512x_psc_fifo_init()
437 	out_be32(&FIFO_512x(port)->tximr, MPC512x_PSC_FIFO_ALARM);  in mpc512x_psc_fifo_init()
438 	out_be32(&FIFO_512x(port)->rximr, MPC512x_PSC_FIFO_ALARM);  in mpc512x_psc_fifo_init()
477 	out_be32(&FIFO_512x(port)->rximr, rx_fifo_imr);  in mpc512x_psc_stop_rx()
486 	out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);  in mpc512x_psc_start_tx()
495 	out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);  in mpc512x_psc_stop_tx()
500 	out_be32(&FIFO_512x(port)->rxisr, in_be32(&FIFO_512x(port)->rxisr));  in mpc512x_psc_rx_clr_irq()
505 	out_be32(&FIFO_512x(port)->txisr, in_be32(&FIFO_512x(port)->txisr));  in mpc512x_psc_tx_clr_irq()
523 	out_be32(&FIFO_512x(port)->tximr, 0);  in mpc512x_psc_cw_disable_ints()
524 	out_be32(&FIFO_512x(port)->rximr, 0);  in mpc512x_psc_cw_disable_ints()
529 	out_be32(&FIFO_512x(port)->tximr,  in mpc512x_psc_cw_restore_ints()
531 	out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f);  in mpc512x_psc_cw_restore_ints()
768 	out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);  in mpc5125_psc_fifo_init()
769 	out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);  in mpc5125_psc_fifo_init()
770 	out_be32(&FIFO_5125(port)->txalarm, 1);  in mpc5125_psc_fifo_init()
771 	out_be32(&FIFO_5125(port)->tximr, 0);  in mpc5125_psc_fifo_init()
773 	out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);  in mpc5125_psc_fifo_init()
774 	out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);  in mpc5125_psc_fifo_init()
775 	out_be32(&FIFO_5125(port)->rxalarm, 1);  in mpc5125_psc_fifo_init()
776 	out_be32(&FIFO_5125(port)->rximr, 0);  in mpc5125_psc_fifo_init()
778 	out_be32(&FIFO_5125(port)->tximr, MPC512x_PSC_FIFO_ALARM);  in mpc5125_psc_fifo_init()
779 	out_be32(&FIFO_5125(port)->rximr, MPC512x_PSC_FIFO_ALARM);  in mpc5125_psc_fifo_init()
815 	out_be32(&FIFO_5125(port)->rximr, rx_fifo_imr);  in mpc5125_psc_stop_rx()
824 	out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr);  in mpc5125_psc_start_tx()
833 	out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr);  in mpc5125_psc_stop_tx()
838 	out_be32(&FIFO_5125(port)->rxisr, in_be32(&FIFO_5125(port)->rxisr));  in mpc5125_psc_rx_clr_irq()
843 	out_be32(&FIFO_5125(port)->txisr, in_be32(&FIFO_5125(port)->txisr));  in mpc5125_psc_tx_clr_irq()
861 	out_be32(&FIFO_5125(port)->tximr, 0);  in mpc5125_psc_cw_disable_ints()
862 	out_be32(&FIFO_5125(port)->rximr, 0);  in mpc5125_psc_cw_disable_ints()
867 	out_be32(&FIFO_5125(port)->tximr,  in mpc5125_psc_cw_restore_ints()
869 	out_be32(&FIFO_5125(port)->rximr, port->read_status_mask & 0x7f);  in mpc5125_psc_cw_restore_ints()
951 	out_be32(&PSC_5125(port)->sicr, val);  in mpc5125_psc_set_sicr()