tty/serial/ip22zilog.h

1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
65 #define	RES_Rx_CRC	0x40	/* Reset Rx CRC Checker */
75 #define	RxINT_DISAB	0	/* Rx Int Disable */
76 #define	RxINT_FCERR	0x8	/* Rx Int on First Character Only or Error */
77 #define	INT_ALL_Rx	0x10	/* Int on all Rx Characters or error */
89 #define	RxENAB  	0x1	/* Rx Enable */
91 #define	ADD_SM		0x4	/* Address Search Mode (SDLC) */
92 #define	RxCRC_ENAB	0x8	/* Rx CRC Enable */
93 #define	ENT_HM		0x10	/* Enter Hunt Mode */
95 #define	Rx5		0x0	/* Rx 5 Bits/Character */
96 #define	Rx7		0x40	/* Rx 7 Bits/Character */
97 #define	Rx6		0x80	/* Rx 6 Bits/Character */
98 #define	Rx8		0xc0	/* Rx 8 Bits/Character */
113 #define	SDLC		0x20	/* SDLC Mode (01111110 Sync Flag) */
114 #define	EXTSYNC		0x30	/* External Sync Mode */
116 #define	X1CLK		0x0	/* x1 clock mode */
117 #define	X16CLK		0x40	/* x16 clock mode */
118 #define	X32CLK		0x80	/* x32 clock mode */
119 #define	X64CLK		0xC0	/* x64 clock mode */
126 #define	SDLC_CRC	0x4	/* SDLC/CRC-16 */
136 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
138 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
155 #define	LOOPMODE 2	/* SDLC Loop mode */
159 #define	NRZ	0	/* NRZ mode */
160 #define	NRZI	0x20	/* NRZI mode */
165 /* Write Register 11 (Clock Mode control) */
191 #define	SEARCH	0x20	/* Enter search mode */
196 #define	SFMM	0xc0	/* Set FM mode */
197 #define	SNRZI	0xe0	/* Set NRZI mode */
209 #define	Rx_CH_AV	0x1	/* Rx Character Available */
220 /* Residue Data for 8 Rx bits/char programmed */
229 /* Special Rx Condition Interrupts */
231 #define	Rx_OVR		0x20	/* Rx Overrun Error */
235 /* Read Register 2 (channel b only) - Interrupt vector */
249 #define	CHBRxIP	0x4		/* Channel B Rx IP */
252 #define	CHARxIP	0x20		/* Channel A Rx IP */
269 #define ZS_CLEARERR(channel)    do { writeb(ERR_RES, &channel->control); \
272 #define ZS_CLEARSTAT(channel)   do { writeb(RES_EXT_INT, &channel->control); \
275 #define ZS_CLEARFIFO(channel)   do { readb(&channel->data); \
277 				     readb(&channel->data); \
279 				     readb(&channel->data); \