tty/serial/ip22zilog.h

1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
58 #define	RES_EXT_INT	0x10	/* Reset Ext. Status Interrupts */
60 #define	RES_RxINT_FC	0x20	/* Reset RxINT on First Character */
61 #define	RES_Tx_P	0x28	/* Reset TxINT Pending */
62 #define	ERR_RES		0x30	/* Error Reset */
63 #define	RES_H_IUS	0x38	/* Reset highest IUS */
65 #define	RES_Rx_CRC	0x40	/* Reset Rx CRC Checker */
66 #define	RES_Tx_CRC	0x80	/* Reset Tx CRC Checker */
67 #define	RES_EOM_L	0xC0	/* Reset EOM latch */
71 #define	EXT_INT_ENAB	0x1	/* Ext Int Enable */
126 #define	SDLC_CRC	0x4	/* SDLC/CRC-16 */
136 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
138 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
148 #define	NORESET	0	/* No reset on write to R9 */
149 #define	CHRB	0x40	/* Reset channel B */
150 #define	CHRA	0x80	/* Reset channel A */
151 #define	FHWRES	0xc0	/* Force hardware reset */
166 #define	TRxCXT	0	/* TRxC = Xtal output */
168 #define	TRxCBR	2	/* TRxC = BR Generator Output */
169 #define	TRxCDP	3	/* TRxC = DPLL output */
173 #define	TCBR	0x10	/* Transmit clock = BR Generator output */
174 #define	TCDPLL	0x18	/* Transmit clock = DPLL output */
177 #define	RCBR	0x40	/* Receive clock = BR Generator output */
178 #define	RCDPLL	0x60	/* Receive clock = DPLL output */
192 #define	RMC	0x40	/* Reset missing clock */
235 /* Read Register 2 (channel b only) - Interrupt vector */
247 #define	CHBEXT	0x1		/* Channel B Ext/Stat IP */
250 #define	CHAEXT	0x8		/* Channel A Ext/Stat IP */
269 #define ZS_CLEARERR(channel)    do { writeb(ERR_RES, &channel->control); \
272 #define ZS_CLEARSTAT(channel)   do { writeb(RES_EXT_INT, &channel->control); \
275 #define ZS_CLEARFIFO(channel)   do { readb(&channel->data); \
277 				     readb(&channel->data); \
279 				     readb(&channel->data); \