Lines Matching refs:sport
273 static inline void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset) in imx_uart_writel() argument
275 writel(val, sport->port.membase + offset); in imx_uart_writel()
278 static inline u32 imx_uart_readl(struct imx_port *sport, u32 offset) in imx_uart_readl() argument
280 return readl(sport->port.membase + offset); in imx_uart_readl()
283 static inline unsigned imx_uart_uts_reg(struct imx_port *sport) in imx_uart_uts_reg() argument
285 return sport->devdata->uts_reg; in imx_uart_uts_reg()
288 static inline int imx_uart_is_imx1(struct imx_port *sport) in imx_uart_is_imx1() argument
290 return sport->devdata->devtype == IMX1_UART; in imx_uart_is_imx1()
297 static void imx_uart_ucrs_save(struct imx_port *sport, in imx_uart_ucrs_save() argument
301 ucr->ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_ucrs_save()
302 ucr->ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_ucrs_save()
303 ucr->ucr3 = imx_uart_readl(sport, UCR3); in imx_uart_ucrs_save()
306 static void imx_uart_ucrs_restore(struct imx_port *sport, in imx_uart_ucrs_restore() argument
310 imx_uart_writel(sport, ucr->ucr1, UCR1); in imx_uart_ucrs_restore()
311 imx_uart_writel(sport, ucr->ucr2, UCR2); in imx_uart_ucrs_restore()
312 imx_uart_writel(sport, ucr->ucr3, UCR3); in imx_uart_ucrs_restore()
317 static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2) in imx_uart_rts_active() argument
321 mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS); in imx_uart_rts_active()
325 static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2) in imx_uart_rts_inactive() argument
330 mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS); in imx_uart_rts_inactive()
339 static void imx_uart_soft_reset(struct imx_port *sport) in imx_uart_soft_reset() argument
355 ubir = imx_uart_readl(sport, UBIR); in imx_uart_soft_reset()
356 ubmr = imx_uart_readl(sport, UBMR); in imx_uart_soft_reset()
357 uts = imx_uart_readl(sport, IMX21_UTS); in imx_uart_soft_reset()
359 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_soft_reset()
360 imx_uart_writel(sport, ucr2 & ~UCR2_SRST, UCR2); in imx_uart_soft_reset()
362 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) in imx_uart_soft_reset()
366 imx_uart_writel(sport, ubir, UBIR); in imx_uart_soft_reset()
367 imx_uart_writel(sport, ubmr, UBMR); in imx_uart_soft_reset()
368 imx_uart_writel(sport, uts, IMX21_UTS); in imx_uart_soft_reset()
370 sport->idle_counter = 0; in imx_uart_soft_reset()
373 static void imx_uart_disable_loopback_rs485(struct imx_port *sport) in imx_uart_disable_loopback_rs485() argument
378 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)); in imx_uart_disable_loopback_rs485()
380 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); in imx_uart_disable_loopback_rs485()
386 struct imx_port *sport = to_imx_port(port); in imx_uart_start_rx() local
389 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_start_rx()
390 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_start_rx()
394 if (sport->dma_is_enabled) { in imx_uart_start_rx()
402 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_start_rx()
403 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_start_rx()
404 imx_uart_disable_loopback_rs485(sport); in imx_uart_start_rx()
410 struct imx_port *sport = to_imx_port(port); in imx_uart_stop_tx() local
413 if (sport->tx_state == OFF) in imx_uart_stop_tx()
420 if (sport->dma_is_txing) in imx_uart_stop_tx()
423 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_stop_tx()
424 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1); in imx_uart_stop_tx()
426 ucr4 = imx_uart_readl(sport, UCR4); in imx_uart_stop_tx()
427 usr2 = imx_uart_readl(sport, USR2); in imx_uart_stop_tx()
434 imx_uart_writel(sport, ucr4, UCR4); in imx_uart_stop_tx()
438 if (sport->tx_state == SEND) { in imx_uart_stop_tx()
439 sport->tx_state = WAIT_AFTER_SEND; in imx_uart_stop_tx()
442 start_hrtimer_ms(&sport->trigger_stop_tx, in imx_uart_stop_tx()
450 if (sport->tx_state == WAIT_AFTER_RTS || in imx_uart_stop_tx()
451 sport->tx_state == WAIT_AFTER_SEND) { in imx_uart_stop_tx()
454 hrtimer_try_to_cancel(&sport->trigger_start_tx); in imx_uart_stop_tx()
456 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_stop_tx()
458 imx_uart_rts_active(sport, &ucr2); in imx_uart_stop_tx()
460 imx_uart_rts_inactive(sport, &ucr2); in imx_uart_stop_tx()
461 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_stop_tx()
466 sport->tx_state = OFF; in imx_uart_stop_tx()
469 sport->tx_state = OFF; in imx_uart_stop_tx()
475 struct imx_port *sport = to_imx_port(port); in imx_uart_stop_rx_with_loopback_ctrl() local
478 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_stop_rx_with_loopback_ctrl()
479 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_stop_rx_with_loopback_ctrl()
480 ucr4 = imx_uart_readl(sport, UCR4); in imx_uart_stop_rx_with_loopback_ctrl()
482 if (sport->dma_is_enabled) { in imx_uart_stop_rx_with_loopback_ctrl()
489 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_stop_rx_with_loopback_ctrl()
490 imx_uart_writel(sport, ucr4, UCR4); in imx_uart_stop_rx_with_loopback_ctrl()
495 sport->have_rtscts && !sport->have_rtsgpio && loopback) { in imx_uart_stop_rx_with_loopback_ctrl()
496 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)); in imx_uart_stop_rx_with_loopback_ctrl()
498 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); in imx_uart_stop_rx_with_loopback_ctrl()
504 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_stop_rx_with_loopback_ctrl()
520 struct imx_port *sport = to_imx_port(port); in imx_uart_enable_ms() local
522 mod_timer(&sport->timer, jiffies); in imx_uart_enable_ms()
524 mctrl_gpio_enable_ms(sport->gpios); in imx_uart_enable_ms()
527 static void imx_uart_dma_tx(struct imx_port *sport);
530 static inline void imx_uart_transmit_buffer(struct imx_port *sport) in imx_uart_transmit_buffer() argument
532 struct tty_port *tport = &sport->port.state->port; in imx_uart_transmit_buffer()
535 if (sport->port.x_char) { in imx_uart_transmit_buffer()
537 imx_uart_writel(sport, sport->port.x_char, URTX0); in imx_uart_transmit_buffer()
538 sport->port.icount.tx++; in imx_uart_transmit_buffer()
539 sport->port.x_char = 0; in imx_uart_transmit_buffer()
544 uart_tx_stopped(&sport->port)) { in imx_uart_transmit_buffer()
545 imx_uart_stop_tx(&sport->port); in imx_uart_transmit_buffer()
549 if (sport->dma_is_enabled) { in imx_uart_transmit_buffer()
555 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_transmit_buffer()
557 if (sport->dma_is_txing) { in imx_uart_transmit_buffer()
559 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_transmit_buffer()
561 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_transmit_buffer()
562 imx_uart_dma_tx(sport); in imx_uart_transmit_buffer()
568 while (!(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL) && in imx_uart_transmit_buffer()
569 uart_fifo_get(&sport->port, &c)) in imx_uart_transmit_buffer()
570 imx_uart_writel(sport, c, URTX0); in imx_uart_transmit_buffer()
573 uart_write_wakeup(&sport->port); in imx_uart_transmit_buffer()
576 imx_uart_stop_tx(&sport->port); in imx_uart_transmit_buffer()
581 struct imx_port *sport = data; in imx_uart_dma_tx_callback() local
582 struct tty_port *tport = &sport->port.state->port; in imx_uart_dma_tx_callback()
583 struct scatterlist *sgl = &sport->tx_sgl[0]; in imx_uart_dma_tx_callback()
587 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_dma_tx_callback()
589 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_dma_tx_callback()
591 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_dma_tx_callback()
593 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_dma_tx_callback()
595 uart_xmit_advance(&sport->port, sport->tx_bytes); in imx_uart_dma_tx_callback()
597 dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); in imx_uart_dma_tx_callback()
599 sport->dma_is_txing = 0; in imx_uart_dma_tx_callback()
602 uart_write_wakeup(&sport->port); in imx_uart_dma_tx_callback()
605 !uart_tx_stopped(&sport->port)) in imx_uart_dma_tx_callback()
606 imx_uart_dma_tx(sport); in imx_uart_dma_tx_callback()
607 else if (sport->port.rs485.flags & SER_RS485_ENABLED) { in imx_uart_dma_tx_callback()
608 u32 ucr4 = imx_uart_readl(sport, UCR4); in imx_uart_dma_tx_callback()
610 imx_uart_writel(sport, ucr4, UCR4); in imx_uart_dma_tx_callback()
613 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_dma_tx_callback()
617 static void imx_uart_dma_tx(struct imx_port *sport) in imx_uart_dma_tx() argument
619 struct tty_port *tport = &sport->port.state->port; in imx_uart_dma_tx()
620 struct scatterlist *sgl = sport->tx_sgl; in imx_uart_dma_tx()
622 struct dma_chan *chan = sport->dma_chan_tx; in imx_uart_dma_tx()
623 struct device *dev = sport->port.dev; in imx_uart_dma_tx()
627 if (sport->dma_is_txing) in imx_uart_dma_tx()
630 ucr4 = imx_uart_readl(sport, UCR4); in imx_uart_dma_tx()
632 imx_uart_writel(sport, ucr4, UCR4); in imx_uart_dma_tx()
634 sg_init_table(sgl, ARRAY_SIZE(sport->tx_sgl)); in imx_uart_dma_tx()
635 sport->tx_bytes = kfifo_len(&tport->xmit_fifo); in imx_uart_dma_tx()
636 sport->dma_tx_nents = kfifo_dma_out_prepare(&tport->xmit_fifo, sgl, in imx_uart_dma_tx()
637 ARRAY_SIZE(sport->tx_sgl), sport->tx_bytes); in imx_uart_dma_tx()
639 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_dma_tx()
647 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, in imx_uart_dma_tx()
653 desc->callback_param = sport; in imx_uart_dma_tx()
655 dev_dbg(dev, "TX: prepare to send %u bytes by DMA.\n", sport->tx_bytes); in imx_uart_dma_tx()
657 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_dma_tx()
659 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_dma_tx()
662 sport->dma_is_txing = 1; in imx_uart_dma_tx()
671 struct imx_port *sport = to_imx_port(port); in imx_uart_start_tx() local
672 struct tty_port *tport = &sport->port.state->port; in imx_uart_start_tx()
675 if (!sport->port.x_char && kfifo_is_empty(&tport->xmit_fifo)) in imx_uart_start_tx()
685 if (sport->tx_state == OFF) { in imx_uart_start_tx()
686 u32 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_start_tx()
688 imx_uart_rts_active(sport, &ucr2); in imx_uart_start_tx()
690 imx_uart_rts_inactive(sport, &ucr2); in imx_uart_start_tx()
691 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_start_tx()
702 sport->tx_state = WAIT_AFTER_RTS; in imx_uart_start_tx()
705 start_hrtimer_ms(&sport->trigger_start_tx, in imx_uart_start_tx()
713 if (sport->tx_state == WAIT_AFTER_SEND in imx_uart_start_tx()
714 || sport->tx_state == WAIT_AFTER_RTS) { in imx_uart_start_tx()
716 hrtimer_try_to_cancel(&sport->trigger_stop_tx); in imx_uart_start_tx()
723 if (!sport->dma_is_enabled) { in imx_uart_start_tx()
724 u32 ucr4 = imx_uart_readl(sport, UCR4); in imx_uart_start_tx()
726 imx_uart_writel(sport, ucr4, UCR4); in imx_uart_start_tx()
729 sport->tx_state = SEND; in imx_uart_start_tx()
732 sport->tx_state = SEND; in imx_uart_start_tx()
735 if (!sport->dma_is_enabled) { in imx_uart_start_tx()
736 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_start_tx()
737 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1); in imx_uart_start_tx()
740 if (sport->dma_is_enabled) { in imx_uart_start_tx()
741 if (sport->port.x_char) { in imx_uart_start_tx()
744 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_start_tx()
747 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_start_tx()
753 imx_uart_dma_tx(sport); in imx_uart_start_tx()
760 struct imx_port *sport = dev_id; in __imx_uart_rtsint() local
763 imx_uart_writel(sport, USR1_RTSD, USR1); in __imx_uart_rtsint()
764 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS; in __imx_uart_rtsint()
777 sport->old_status |= TIOCM_CTS; in __imx_uart_rtsint()
779 sport->old_status &= ~TIOCM_CTS; in __imx_uart_rtsint()
780 uart_handle_cts_change(&sport->port, usr1); in __imx_uart_rtsint()
781 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); in __imx_uart_rtsint()
788 struct imx_port *sport = dev_id; in imx_uart_rtsint() local
791 uart_port_lock(&sport->port); in imx_uart_rtsint()
795 uart_port_unlock(&sport->port); in imx_uart_rtsint()
802 struct imx_port *sport = dev_id; in imx_uart_txint() local
804 uart_port_lock(&sport->port); in imx_uart_txint()
805 imx_uart_transmit_buffer(sport); in imx_uart_txint()
806 uart_port_unlock(&sport->port); in imx_uart_txint()
822 static void imx_uart_check_flood(struct imx_port *sport, u32 usr2) in imx_uart_check_flood() argument
848 imx_uart_writel(sport, USR2_WAKE, USR2); in imx_uart_check_flood()
849 sport->idle_counter = 0; in imx_uart_check_flood()
850 } else if (++sport->idle_counter > 3) { in imx_uart_check_flood()
851 dev_warn(sport->port.dev, "RX flood detected: soft reset."); in imx_uart_check_flood()
852 imx_uart_soft_reset(sport); /* also clears 'sport->idle_counter' */ in imx_uart_check_flood()
858 struct imx_port *sport = dev_id; in __imx_uart_rxint() local
859 struct tty_port *port = &sport->port.state->port; in __imx_uart_rxint()
863 usr2 = imx_uart_readl(sport, USR2); in __imx_uart_rxint()
865 imx_uart_check_flood(sport, usr2); in __imx_uart_rxint()
867 while ((rx = imx_uart_readl(sport, URXD0)) & URXD_CHARRDY) { in __imx_uart_rxint()
869 sport->port.icount.rx++; in __imx_uart_rxint()
873 sport->port.icount.brk++; in __imx_uart_rxint()
874 if (uart_handle_break(&sport->port)) in __imx_uart_rxint()
878 sport->port.icount.parity++; in __imx_uart_rxint()
880 sport->port.icount.frame++; in __imx_uart_rxint()
882 sport->port.icount.overrun++; in __imx_uart_rxint()
884 if (rx & sport->port.ignore_status_mask) in __imx_uart_rxint()
887 rx &= (sport->port.read_status_mask | 0xFF); in __imx_uart_rxint()
898 sport->port.sysrq = 0; in __imx_uart_rxint()
899 } else if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) { in __imx_uart_rxint()
903 if (sport->port.ignore_status_mask & URXD_DUMMY_READ) in __imx_uart_rxint()
907 sport->port.icount.buf_overrun++; in __imx_uart_rxint()
917 struct imx_port *sport = dev_id; in imx_uart_rxint() local
920 uart_port_lock(&sport->port); in imx_uart_rxint()
924 uart_port_unlock(&sport->port); in imx_uart_rxint()
929 static void imx_uart_clear_rx_errors(struct imx_port *sport);
934 static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport) in imx_uart_get_hwmctrl() argument
937 unsigned usr1 = imx_uart_readl(sport, USR1); in imx_uart_get_hwmctrl()
938 unsigned usr2 = imx_uart_readl(sport, USR2); in imx_uart_get_hwmctrl()
947 if (sport->dte_mode) in imx_uart_get_hwmctrl()
948 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN)) in imx_uart_get_hwmctrl()
957 static void imx_uart_mctrl_check(struct imx_port *sport) in imx_uart_mctrl_check() argument
961 status = imx_uart_get_hwmctrl(sport); in imx_uart_mctrl_check()
962 changed = status ^ sport->old_status; in imx_uart_mctrl_check()
967 sport->old_status = status; in imx_uart_mctrl_check()
970 sport->port.icount.rng++; in imx_uart_mctrl_check()
972 sport->port.icount.dsr++; in imx_uart_mctrl_check()
974 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); in imx_uart_mctrl_check()
976 uart_handle_cts_change(&sport->port, status & TIOCM_CTS); in imx_uart_mctrl_check()
978 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); in imx_uart_mctrl_check()
983 struct imx_port *sport = dev_id; in imx_uart_int() local
987 uart_port_lock(&sport->port); in imx_uart_int()
989 usr1 = imx_uart_readl(sport, USR1); in imx_uart_int()
990 usr2 = imx_uart_readl(sport, USR2); in imx_uart_int()
991 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_int()
992 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_int()
993 ucr3 = imx_uart_readl(sport, UCR3); in imx_uart_int()
994 ucr4 = imx_uart_readl(sport, UCR4); in imx_uart_int()
1022 imx_uart_writel(sport, USR1_AGTIM, USR1); in imx_uart_int()
1029 imx_uart_transmit_buffer(sport); in imx_uart_int()
1034 imx_uart_writel(sport, USR1_DTRD, USR1); in imx_uart_int()
1036 imx_uart_mctrl_check(sport); in imx_uart_int()
1047 imx_uart_writel(sport, USR1_AWAKE, USR1); in imx_uart_int()
1052 sport->port.icount.overrun++; in imx_uart_int()
1053 imx_uart_writel(sport, USR2_ORE, USR2); in imx_uart_int()
1057 uart_port_unlock(&sport->port); in imx_uart_int()
1067 struct imx_port *sport = to_imx_port(port); in imx_uart_tx_empty() local
1070 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; in imx_uart_tx_empty()
1073 if (sport->dma_is_txing) in imx_uart_tx_empty()
1082 struct imx_port *sport = to_imx_port(port); in imx_uart_get_mctrl() local
1083 unsigned int ret = imx_uart_get_hwmctrl(sport); in imx_uart_get_mctrl()
1085 mctrl_gpio_get(sport->gpios, &ret); in imx_uart_get_mctrl()
1093 struct imx_port *sport = to_imx_port(port); in imx_uart_set_mctrl() local
1103 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_set_mctrl()
1115 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_set_mctrl()
1118 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR; in imx_uart_set_mctrl()
1121 imx_uart_writel(sport, ucr3, UCR3); in imx_uart_set_mctrl()
1123 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP; in imx_uart_set_mctrl()
1126 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); in imx_uart_set_mctrl()
1128 mctrl_gpio_set(sport->gpios, mctrl); in imx_uart_set_mctrl()
1136 struct imx_port *sport = to_imx_port(port); in imx_uart_break_ctl() local
1140 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_break_ctl()
1142 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK; in imx_uart_break_ctl()
1147 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_break_ctl()
1149 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_break_ctl()
1158 struct imx_port *sport = from_timer(sport, t, timer); in imx_uart_timeout() local
1161 if (sport->port.state) { in imx_uart_timeout()
1162 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_timeout()
1163 imx_uart_mctrl_check(sport); in imx_uart_timeout()
1164 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_timeout()
1166 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); in imx_uart_timeout()
1180 struct imx_port *sport = data; in imx_uart_dma_rx_callback() local
1181 struct dma_chan *chan = sport->dma_chan_rx; in imx_uart_dma_rx_callback()
1182 struct scatterlist *sgl = &sport->rx_sgl; in imx_uart_dma_rx_callback()
1183 struct tty_port *port = &sport->port.state->port; in imx_uart_dma_rx_callback()
1185 struct circ_buf *rx_ring = &sport->rx_ring; in imx_uart_dma_rx_callback()
1191 status = dmaengine_tx_status(chan, sport->rx_cookie, &state); in imx_uart_dma_rx_callback()
1194 uart_port_lock(&sport->port); in imx_uart_dma_rx_callback()
1195 imx_uart_clear_rx_errors(sport); in imx_uart_dma_rx_callback()
1196 uart_port_unlock(&sport->port); in imx_uart_dma_rx_callback()
1215 bd_size = sg_dma_len(sgl) / sport->rx_periods; in imx_uart_dma_rx_callback()
1225 uart_port_lock(&sport->port); in imx_uart_dma_rx_callback()
1226 imx_uart_check_flood(sport, imx_uart_readl(sport, USR2)); in imx_uart_dma_rx_callback()
1227 uart_port_unlock(&sport->port); in imx_uart_dma_rx_callback()
1229 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { in imx_uart_dma_rx_callback()
1232 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, in imx_uart_dma_rx_callback()
1236 sport->rx_buf + rx_ring->tail, r_bytes); in imx_uart_dma_rx_callback()
1239 dma_sync_sg_for_device(sport->port.dev, sgl, 1, in imx_uart_dma_rx_callback()
1243 sport->port.icount.buf_overrun++; in imx_uart_dma_rx_callback()
1245 sport->port.icount.rx += w_bytes; in imx_uart_dma_rx_callback()
1254 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); in imx_uart_dma_rx_callback()
1258 static int imx_uart_start_rx_dma(struct imx_port *sport) in imx_uart_start_rx_dma() argument
1260 struct scatterlist *sgl = &sport->rx_sgl; in imx_uart_start_rx_dma()
1261 struct dma_chan *chan = sport->dma_chan_rx; in imx_uart_start_rx_dma()
1262 struct device *dev = sport->port.dev; in imx_uart_start_rx_dma()
1266 sport->rx_ring.head = 0; in imx_uart_start_rx_dma()
1267 sport->rx_ring.tail = 0; in imx_uart_start_rx_dma()
1269 sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size); in imx_uart_start_rx_dma()
1277 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, in imx_uart_start_rx_dma()
1286 desc->callback_param = sport; in imx_uart_start_rx_dma()
1289 sport->dma_is_rxing = 1; in imx_uart_start_rx_dma()
1290 sport->rx_cookie = dmaengine_submit(desc); in imx_uart_start_rx_dma()
1295 static void imx_uart_clear_rx_errors(struct imx_port *sport) in imx_uart_clear_rx_errors() argument
1297 struct tty_port *port = &sport->port.state->port; in imx_uart_clear_rx_errors()
1300 usr1 = imx_uart_readl(sport, USR1); in imx_uart_clear_rx_errors()
1301 usr2 = imx_uart_readl(sport, USR2); in imx_uart_clear_rx_errors()
1304 sport->port.icount.brk++; in imx_uart_clear_rx_errors()
1305 imx_uart_writel(sport, USR2_BRCD, USR2); in imx_uart_clear_rx_errors()
1306 uart_handle_break(&sport->port); in imx_uart_clear_rx_errors()
1308 sport->port.icount.buf_overrun++; in imx_uart_clear_rx_errors()
1312 sport->port.icount.frame++; in imx_uart_clear_rx_errors()
1313 imx_uart_writel(sport, USR1_FRAMERR, USR1); in imx_uart_clear_rx_errors()
1315 sport->port.icount.parity++; in imx_uart_clear_rx_errors()
1316 imx_uart_writel(sport, USR1_PARITYERR, USR1); in imx_uart_clear_rx_errors()
1321 sport->port.icount.overrun++; in imx_uart_clear_rx_errors()
1322 imx_uart_writel(sport, USR2_ORE, USR2); in imx_uart_clear_rx_errors()
1325 sport->idle_counter = 0; in imx_uart_clear_rx_errors()
1334 static void imx_uart_setup_ufcr(struct imx_port *sport, in imx_uart_setup_ufcr() argument
1340 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); in imx_uart_setup_ufcr()
1342 imx_uart_writel(sport, val, UFCR); in imx_uart_setup_ufcr()
1345 static void imx_uart_dma_exit(struct imx_port *sport) in imx_uart_dma_exit() argument
1347 if (sport->dma_chan_rx) { in imx_uart_dma_exit()
1348 dmaengine_terminate_sync(sport->dma_chan_rx); in imx_uart_dma_exit()
1349 dma_release_channel(sport->dma_chan_rx); in imx_uart_dma_exit()
1350 sport->dma_chan_rx = NULL; in imx_uart_dma_exit()
1351 sport->rx_cookie = -EINVAL; in imx_uart_dma_exit()
1352 kfree(sport->rx_buf); in imx_uart_dma_exit()
1353 sport->rx_buf = NULL; in imx_uart_dma_exit()
1356 if (sport->dma_chan_tx) { in imx_uart_dma_exit()
1357 dmaengine_terminate_sync(sport->dma_chan_tx); in imx_uart_dma_exit()
1358 dma_release_channel(sport->dma_chan_tx); in imx_uart_dma_exit()
1359 sport->dma_chan_tx = NULL; in imx_uart_dma_exit()
1363 static int imx_uart_dma_init(struct imx_port *sport) in imx_uart_dma_init() argument
1366 struct device *dev = sport->port.dev; in imx_uart_dma_init()
1374 sport->dma_chan_rx = NULL; in imx_uart_dma_init()
1378 sport->dma_chan_rx = chan; in imx_uart_dma_init()
1381 slave_config.src_addr = sport->port.mapbase + URXD0; in imx_uart_dma_init()
1385 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); in imx_uart_dma_init()
1391 sport->rx_buf_size = sport->rx_period_length * sport->rx_periods; in imx_uart_dma_init()
1392 sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL); in imx_uart_dma_init()
1393 if (!sport->rx_buf) { in imx_uart_dma_init()
1397 sport->rx_ring.buf = sport->rx_buf; in imx_uart_dma_init()
1403 sport->dma_chan_tx = NULL; in imx_uart_dma_init()
1407 sport->dma_chan_tx = chan; in imx_uart_dma_init()
1410 slave_config.dst_addr = sport->port.mapbase + URTX0; in imx_uart_dma_init()
1413 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); in imx_uart_dma_init()
1421 imx_uart_dma_exit(sport); in imx_uart_dma_init()
1425 static void imx_uart_enable_dma(struct imx_port *sport) in imx_uart_enable_dma() argument
1429 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA); in imx_uart_enable_dma()
1432 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_enable_dma()
1434 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_enable_dma()
1436 sport->dma_is_enabled = 1; in imx_uart_enable_dma()
1439 static void imx_uart_disable_dma(struct imx_port *sport) in imx_uart_disable_dma() argument
1444 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_disable_dma()
1446 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_disable_dma()
1448 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); in imx_uart_disable_dma()
1450 sport->dma_is_enabled = 0; in imx_uart_disable_dma()
1458 struct imx_port *sport = to_imx_port(port); in imx_uart_startup() local
1464 retval = clk_prepare_enable(sport->clk_per); in imx_uart_startup()
1467 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_startup()
1469 clk_disable_unprepare(sport->clk_per); in imx_uart_startup()
1473 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); in imx_uart_startup()
1478 ucr4 = imx_uart_readl(sport, UCR4); in imx_uart_startup()
1484 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4); in imx_uart_startup()
1487 if (!uart_console(port) && imx_uart_dma_init(sport) == 0) { in imx_uart_startup()
1492 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_startup()
1495 imx_uart_soft_reset(sport); in imx_uart_startup()
1500 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1); in imx_uart_startup()
1501 imx_uart_writel(sport, USR2_ORE, USR2); in imx_uart_startup()
1503 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN; in imx_uart_startup()
1505 if (sport->have_rtscts) in imx_uart_startup()
1508 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_startup()
1510 ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR); in imx_uart_startup()
1513 if (sport->inverted_rx) in imx_uart_startup()
1515 imx_uart_writel(sport, ucr4, UCR4); in imx_uart_startup()
1517 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT; in imx_uart_startup()
1521 if (sport->inverted_tx) in imx_uart_startup()
1524 if (!imx_uart_is_imx1(sport)) { in imx_uart_startup()
1527 if (sport->dte_mode) in imx_uart_startup()
1531 imx_uart_writel(sport, ucr3, UCR3); in imx_uart_startup()
1533 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN; in imx_uart_startup()
1535 if (!sport->have_rtscts) in imx_uart_startup()
1541 if (!imx_uart_is_imx1(sport)) in imx_uart_startup()
1543 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_startup()
1548 imx_uart_enable_ms(&sport->port); in imx_uart_startup()
1551 imx_uart_enable_dma(sport); in imx_uart_startup()
1552 imx_uart_start_rx_dma(sport); in imx_uart_startup()
1554 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_startup()
1556 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_startup()
1558 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_startup()
1560 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_startup()
1563 imx_uart_disable_loopback_rs485(sport); in imx_uart_startup()
1565 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_startup()
1572 struct imx_port *sport = to_imx_port(port); in imx_uart_shutdown() local
1577 if (sport->dma_is_enabled) { in imx_uart_shutdown()
1578 dmaengine_terminate_sync(sport->dma_chan_tx); in imx_uart_shutdown()
1579 if (sport->dma_is_txing) { in imx_uart_shutdown()
1580 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], in imx_uart_shutdown()
1581 sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_shutdown()
1582 sport->dma_is_txing = 0; in imx_uart_shutdown()
1584 dmaengine_terminate_sync(sport->dma_chan_rx); in imx_uart_shutdown()
1585 if (sport->dma_is_rxing) { in imx_uart_shutdown()
1586 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, in imx_uart_shutdown()
1588 sport->dma_is_rxing = 0; in imx_uart_shutdown()
1591 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_shutdown()
1594 imx_uart_disable_dma(sport); in imx_uart_shutdown()
1595 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_shutdown()
1596 imx_uart_dma_exit(sport); in imx_uart_shutdown()
1599 mctrl_gpio_disable_ms(sport->gpios); in imx_uart_shutdown()
1601 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_shutdown()
1602 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_shutdown()
1604 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_shutdown()
1605 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_shutdown()
1610 del_timer_sync(&sport->timer); in imx_uart_shutdown()
1616 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_shutdown()
1618 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_shutdown()
1624 sport->have_rtscts && !sport->have_rtsgpio) { in imx_uart_shutdown()
1625 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)); in imx_uart_shutdown()
1627 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); in imx_uart_shutdown()
1632 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_shutdown()
1634 ucr4 = imx_uart_readl(sport, UCR4); in imx_uart_shutdown()
1636 imx_uart_writel(sport, ucr4, UCR4); in imx_uart_shutdown()
1648 if (sport->tx_state == WAIT_AFTER_RTS || sport->tx_state == SEND) in imx_uart_shutdown()
1663 while (sport->tx_state != OFF && loops--) { in imx_uart_shutdown()
1664 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_shutdown()
1666 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_shutdown()
1669 if (sport->tx_state != OFF) { in imx_uart_shutdown()
1670 dev_warn(sport->port.dev, "unexpected tx_state %d\n", in imx_uart_shutdown()
1671 sport->tx_state); in imx_uart_shutdown()
1678 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_shutdown()
1680 imx_uart_rts_active(sport, &ucr2); in imx_uart_shutdown()
1682 imx_uart_rts_inactive(sport, &ucr2); in imx_uart_shutdown()
1683 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_shutdown()
1685 sport->tx_state = OFF; in imx_uart_shutdown()
1688 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_shutdown()
1690 clk_disable_unprepare(sport->clk_per); in imx_uart_shutdown()
1691 clk_disable_unprepare(sport->clk_ipg); in imx_uart_shutdown()
1697 struct imx_port *sport = to_imx_port(port); in imx_uart_flush_buffer() local
1698 struct scatterlist *sgl = &sport->tx_sgl[0]; in imx_uart_flush_buffer()
1700 if (!sport->dma_chan_tx) in imx_uart_flush_buffer()
1703 sport->tx_bytes = 0; in imx_uart_flush_buffer()
1704 dmaengine_terminate_all(sport->dma_chan_tx); in imx_uart_flush_buffer()
1705 if (sport->dma_is_txing) { in imx_uart_flush_buffer()
1708 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, in imx_uart_flush_buffer()
1710 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_flush_buffer()
1712 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_flush_buffer()
1713 sport->dma_is_txing = 0; in imx_uart_flush_buffer()
1716 imx_uart_soft_reset(sport); in imx_uart_flush_buffer()
1724 struct imx_port *sport = to_imx_port(port); in imx_uart_set_termios() local
1743 del_timer_sync(&sport->timer); in imx_uart_set_termios()
1751 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_set_termios()
1757 old_ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_set_termios()
1764 if (!sport->have_rtscts) in imx_uart_set_termios()
1774 imx_uart_rts_active(sport, &ucr2); in imx_uart_set_termios()
1776 imx_uart_rts_inactive(sport, &ucr2); in imx_uart_set_termios()
1797 sport->port.read_status_mask = 0; in imx_uart_set_termios()
1799 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); in imx_uart_set_termios()
1801 sport->port.read_status_mask |= URXD_BRK; in imx_uart_set_termios()
1806 sport->port.ignore_status_mask = 0; in imx_uart_set_termios()
1808 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; in imx_uart_set_termios()
1810 sport->port.ignore_status_mask |= URXD_BRK; in imx_uart_set_termios()
1816 sport->port.ignore_status_mask |= URXD_OVRRUN; in imx_uart_set_termios()
1820 sport->port.ignore_status_mask |= URXD_DUMMY_READ; in imx_uart_set_termios()
1828 div = sport->port.uartclk / (baud * 16); in imx_uart_set_termios()
1830 baud = sport->port.uartclk / (quot * 16); in imx_uart_set_termios()
1832 div = sport->port.uartclk / (baud * 16); in imx_uart_set_termios()
1838 rational_best_approximation(16 * div * baud, sport->port.uartclk, in imx_uart_set_termios()
1841 tdiv64 = sport->port.uartclk; in imx_uart_set_termios()
1850 ufcr = imx_uart_readl(sport, UFCR); in imx_uart_set_termios()
1852 imx_uart_writel(sport, ufcr, UFCR); in imx_uart_set_termios()
1863 old_ubir = imx_uart_readl(sport, UBIR); in imx_uart_set_termios()
1864 old_ubmr = imx_uart_readl(sport, UBMR); in imx_uart_set_termios()
1866 imx_uart_writel(sport, num, UBIR); in imx_uart_set_termios()
1867 imx_uart_writel(sport, denom, UBMR); in imx_uart_set_termios()
1870 if (!imx_uart_is_imx1(sport)) in imx_uart_set_termios()
1871 imx_uart_writel(sport, sport->port.uartclk / div / 1000, in imx_uart_set_termios()
1874 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_set_termios()
1876 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) in imx_uart_set_termios()
1877 imx_uart_enable_ms(&sport->port); in imx_uart_set_termios()
1879 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_set_termios()
1927 struct imx_port *sport = to_imx_port(port); in imx_uart_poll_init() local
1932 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_poll_init()
1935 retval = clk_prepare_enable(sport->clk_per); in imx_uart_poll_init()
1937 clk_disable_unprepare(sport->clk_ipg); in imx_uart_poll_init()
1939 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); in imx_uart_poll_init()
1941 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_poll_init()
1950 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_poll_init()
1951 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_poll_init()
1953 if (imx_uart_is_imx1(sport)) in imx_uart_poll_init()
1962 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_poll_init()
1963 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_poll_init()
1966 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1); in imx_uart_poll_init()
1967 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2); in imx_uart_poll_init()
1969 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_poll_init()
1976 struct imx_port *sport = to_imx_port(port); in imx_uart_poll_get_char() local
1977 if (!(imx_uart_readl(sport, USR2) & USR2_RDR)) in imx_uart_poll_get_char()
1980 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA; in imx_uart_poll_get_char()
1985 struct imx_port *sport = to_imx_port(port); in imx_uart_poll_put_char() local
1990 status = imx_uart_readl(sport, USR1); in imx_uart_poll_put_char()
1994 imx_uart_writel(sport, c, URTX0); in imx_uart_poll_put_char()
1998 status = imx_uart_readl(sport, USR2); in imx_uart_poll_put_char()
2007 struct imx_port *sport = to_imx_port(port); in imx_uart_rs485_config() local
2012 if (sport->have_rtscts && !sport->have_rtsgpio && in imx_uart_rs485_config()
2017 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_rs485_config()
2019 imx_uart_rts_active(sport, &ucr2); in imx_uart_rs485_config()
2021 imx_uart_rts_inactive(sport, &ucr2); in imx_uart_rs485_config()
2022 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_rs485_config()
2029 ufcr = imx_uart_readl(sport, UFCR); in imx_uart_rs485_config()
2031 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); in imx_uart_rs485_config()
2066 struct imx_port *sport = to_imx_port(port); in imx_uart_console_putchar() local
2068 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL) in imx_uart_console_putchar()
2071 imx_uart_writel(sport, ch, URTX0); in imx_uart_console_putchar()
2080 struct imx_port *sport = imx_uart_ports[co->index]; in imx_uart_console_write() local
2086 if (sport->port.sysrq) in imx_uart_console_write()
2089 locked = uart_port_trylock_irqsave(&sport->port, &flags); in imx_uart_console_write()
2091 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_console_write()
2096 imx_uart_ucrs_save(sport, &old_ucr); in imx_uart_console_write()
2099 if (imx_uart_is_imx1(sport)) in imx_uart_console_write()
2104 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_console_write()
2106 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2); in imx_uart_console_write()
2108 uart_console_write(&sport->port, s, count, imx_uart_console_putchar); in imx_uart_console_write()
2115 0, USEC_PER_SEC, false, sport, USR2); in imx_uart_console_write()
2116 imx_uart_ucrs_restore(sport, &old_ucr); in imx_uart_console_write()
2119 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_console_write()
2127 imx_uart_console_get_options(struct imx_port *sport, int *baud, in imx_uart_console_get_options() argument
2131 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) { in imx_uart_console_get_options()
2137 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_console_get_options()
2152 ubir = imx_uart_readl(sport, UBIR) & 0xffff; in imx_uart_console_get_options()
2153 ubmr = imx_uart_readl(sport, UBMR) & 0xffff; in imx_uart_console_get_options()
2155 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7; in imx_uart_console_get_options()
2161 uartclk = clk_get_rate(sport->clk_per); in imx_uart_console_get_options()
2180 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n", in imx_uart_console_get_options()
2188 struct imx_port *sport; in imx_uart_console_setup() local
2202 sport = imx_uart_ports[co->index]; in imx_uart_console_setup()
2203 if (sport == NULL) in imx_uart_console_setup()
2207 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_console_setup()
2214 imx_uart_console_get_options(sport, &baud, &parity, &bits); in imx_uart_console_setup()
2216 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); in imx_uart_console_setup()
2218 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); in imx_uart_console_setup()
2221 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_setup()
2225 retval = clk_prepare_enable(sport->clk_per); in imx_uart_console_setup()
2227 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_setup()
2236 struct imx_port *sport = imx_uart_ports[co->index]; in imx_uart_console_exit() local
2238 clk_disable_unprepare(sport->clk_per); in imx_uart_console_exit()
2239 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_exit()
2274 struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx); in imx_trigger_start_tx() local
2277 uart_port_lock_irqsave(&sport->port, &flags); in imx_trigger_start_tx()
2278 if (sport->tx_state == WAIT_AFTER_RTS) in imx_trigger_start_tx()
2279 imx_uart_start_tx(&sport->port); in imx_trigger_start_tx()
2280 uart_port_unlock_irqrestore(&sport->port, flags); in imx_trigger_start_tx()
2287 struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx); in imx_trigger_stop_tx() local
2290 uart_port_lock_irqsave(&sport->port, &flags); in imx_trigger_stop_tx()
2291 if (sport->tx_state == WAIT_AFTER_SEND) in imx_trigger_stop_tx()
2292 imx_uart_stop_tx(&sport->port); in imx_trigger_stop_tx()
2293 uart_port_unlock_irqrestore(&sport->port, flags); in imx_trigger_stop_tx()
2312 struct imx_port *sport; in imx_uart_probe() local
2320 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); in imx_uart_probe()
2321 if (!sport) in imx_uart_probe()
2324 sport->devdata = of_device_get_match_data(&pdev->dev); in imx_uart_probe()
2331 sport->port.line = ret; in imx_uart_probe()
2333 sport->have_rtscts = of_property_read_bool(np, "uart-has-rtscts") || in imx_uart_probe()
2336 sport->dte_mode = of_property_read_bool(np, "fsl,dte-mode"); in imx_uart_probe()
2338 sport->have_rtsgpio = of_property_present(np, "rts-gpios"); in imx_uart_probe()
2340 sport->inverted_tx = of_property_read_bool(np, "fsl,inverted-tx"); in imx_uart_probe()
2342 sport->inverted_rx = of_property_read_bool(np, "fsl,inverted-rx"); in imx_uart_probe()
2345 sport->rx_period_length = dma_buf_conf[0]; in imx_uart_probe()
2346 sport->rx_periods = dma_buf_conf[1]; in imx_uart_probe()
2348 sport->rx_period_length = RX_DMA_PERIOD_LEN; in imx_uart_probe()
2349 sport->rx_periods = RX_DMA_PERIODS; in imx_uart_probe()
2352 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) { in imx_uart_probe()
2354 sport->port.line); in imx_uart_probe()
2368 sport->port.dev = &pdev->dev; in imx_uart_probe()
2369 sport->port.mapbase = res->start; in imx_uart_probe()
2370 sport->port.membase = base; in imx_uart_probe()
2371 sport->port.type = PORT_IMX; in imx_uart_probe()
2372 sport->port.iotype = UPIO_MEM; in imx_uart_probe()
2373 sport->port.irq = rxirq; in imx_uart_probe()
2374 sport->port.fifosize = 32; in imx_uart_probe()
2375 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE); in imx_uart_probe()
2376 sport->port.ops = &imx_uart_pops; in imx_uart_probe()
2377 sport->port.rs485_config = imx_uart_rs485_config; in imx_uart_probe()
2379 if (sport->have_rtscts || sport->have_rtsgpio) in imx_uart_probe()
2380 sport->port.rs485_supported = imx_rs485_supported; in imx_uart_probe()
2381 sport->port.flags = UPF_BOOT_AUTOCONF; in imx_uart_probe()
2382 timer_setup(&sport->timer, imx_uart_timeout, 0); in imx_uart_probe()
2384 sport->gpios = mctrl_gpio_init(&sport->port, 0); in imx_uart_probe()
2385 if (IS_ERR(sport->gpios)) in imx_uart_probe()
2386 return PTR_ERR(sport->gpios); in imx_uart_probe()
2388 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in imx_uart_probe()
2389 if (IS_ERR(sport->clk_ipg)) { in imx_uart_probe()
2390 ret = PTR_ERR(sport->clk_ipg); in imx_uart_probe()
2395 sport->clk_per = devm_clk_get(&pdev->dev, "per"); in imx_uart_probe()
2396 if (IS_ERR(sport->clk_per)) { in imx_uart_probe()
2397 ret = PTR_ERR(sport->clk_per); in imx_uart_probe()
2402 sport->port.uartclk = clk_get_rate(sport->clk_per); in imx_uart_probe()
2405 ret = clk_prepare_enable(sport->clk_ipg); in imx_uart_probe()
2411 ret = uart_get_rs485_mode(&sport->port); in imx_uart_probe()
2420 if (sport->port.rs485.flags & SER_RS485_ENABLED && in imx_uart_probe()
2421 sport->have_rtscts && !sport->have_rtsgpio && in imx_uart_probe()
2422 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) && in imx_uart_probe()
2423 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX))) in imx_uart_probe()
2428 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_probe()
2430 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_probe()
2433 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_probe()
2435 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_probe()
2447 if (sport->port.rs485.flags & SER_RS485_ENABLED && in imx_uart_probe()
2448 sport->have_rtscts && !sport->have_rtsgpio) { in imx_uart_probe()
2449 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)); in imx_uart_probe()
2451 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); in imx_uart_probe()
2453 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_probe()
2455 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_probe()
2457 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_probe()
2459 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_probe()
2462 if (!imx_uart_is_imx1(sport) && sport->dte_mode) { in imx_uart_probe()
2469 u32 ufcr = imx_uart_readl(sport, UFCR); in imx_uart_probe()
2471 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR); in imx_uart_probe()
2478 imx_uart_writel(sport, in imx_uart_probe()
2484 u32 ufcr = imx_uart_readl(sport, UFCR); in imx_uart_probe()
2486 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR); in imx_uart_probe()
2488 if (!imx_uart_is_imx1(sport)) in imx_uart_probe()
2490 imx_uart_writel(sport, ucr3, UCR3); in imx_uart_probe()
2493 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in imx_uart_probe()
2494 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in imx_uart_probe()
2495 sport->trigger_start_tx.function = imx_trigger_start_tx; in imx_uart_probe()
2496 sport->trigger_stop_tx.function = imx_trigger_stop_tx; in imx_uart_probe()
2504 dev_name(&pdev->dev), sport); in imx_uart_probe()
2512 dev_name(&pdev->dev), sport); in imx_uart_probe()
2520 dev_name(&pdev->dev), sport); in imx_uart_probe()
2528 dev_name(&pdev->dev), sport); in imx_uart_probe()
2535 imx_uart_ports[sport->port.line] = sport; in imx_uart_probe()
2537 platform_set_drvdata(pdev, sport); in imx_uart_probe()
2539 ret = uart_add_one_port(&imx_uart_uart_driver, &sport->port); in imx_uart_probe()
2542 clk_disable_unprepare(sport->clk_ipg); in imx_uart_probe()
2549 struct imx_port *sport = platform_get_drvdata(pdev); in imx_uart_remove() local
2551 uart_remove_one_port(&imx_uart_uart_driver, &sport->port); in imx_uart_remove()
2554 static void imx_uart_restore_context(struct imx_port *sport) in imx_uart_restore_context() argument
2558 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_restore_context()
2559 if (!sport->context_saved) { in imx_uart_restore_context()
2560 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_restore_context()
2564 imx_uart_writel(sport, sport->saved_reg[4], UFCR); in imx_uart_restore_context()
2565 imx_uart_writel(sport, sport->saved_reg[5], UESC); in imx_uart_restore_context()
2566 imx_uart_writel(sport, sport->saved_reg[6], UTIM); in imx_uart_restore_context()
2567 imx_uart_writel(sport, sport->saved_reg[7], UBIR); in imx_uart_restore_context()
2568 imx_uart_writel(sport, sport->saved_reg[8], UBMR); in imx_uart_restore_context()
2569 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS); in imx_uart_restore_context()
2570 imx_uart_writel(sport, sport->saved_reg[0], UCR1); in imx_uart_restore_context()
2571 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2); in imx_uart_restore_context()
2572 imx_uart_writel(sport, sport->saved_reg[2], UCR3); in imx_uart_restore_context()
2573 imx_uart_writel(sport, sport->saved_reg[3], UCR4); in imx_uart_restore_context()
2574 sport->context_saved = false; in imx_uart_restore_context()
2575 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_restore_context()
2578 static void imx_uart_save_context(struct imx_port *sport) in imx_uart_save_context() argument
2583 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_save_context()
2584 sport->saved_reg[0] = imx_uart_readl(sport, UCR1); in imx_uart_save_context()
2585 sport->saved_reg[1] = imx_uart_readl(sport, UCR2); in imx_uart_save_context()
2586 sport->saved_reg[2] = imx_uart_readl(sport, UCR3); in imx_uart_save_context()
2587 sport->saved_reg[3] = imx_uart_readl(sport, UCR4); in imx_uart_save_context()
2588 sport->saved_reg[4] = imx_uart_readl(sport, UFCR); in imx_uart_save_context()
2589 sport->saved_reg[5] = imx_uart_readl(sport, UESC); in imx_uart_save_context()
2590 sport->saved_reg[6] = imx_uart_readl(sport, UTIM); in imx_uart_save_context()
2591 sport->saved_reg[7] = imx_uart_readl(sport, UBIR); in imx_uart_save_context()
2592 sport->saved_reg[8] = imx_uart_readl(sport, UBMR); in imx_uart_save_context()
2593 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); in imx_uart_save_context()
2594 sport->context_saved = true; in imx_uart_save_context()
2595 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_save_context()
2598 static void imx_uart_enable_wakeup(struct imx_port *sport, bool on) in imx_uart_enable_wakeup() argument
2602 ucr3 = imx_uart_readl(sport, UCR3); in imx_uart_enable_wakeup()
2604 imx_uart_writel(sport, USR1_AWAKE, USR1); in imx_uart_enable_wakeup()
2609 imx_uart_writel(sport, ucr3, UCR3); in imx_uart_enable_wakeup()
2611 if (sport->have_rtscts) { in imx_uart_enable_wakeup()
2612 u32 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_enable_wakeup()
2614 imx_uart_writel(sport, USR1_RTSD, USR1); in imx_uart_enable_wakeup()
2619 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_enable_wakeup()
2625 struct imx_port *sport = dev_get_drvdata(dev); in imx_uart_suspend_noirq() local
2627 imx_uart_save_context(sport); in imx_uart_suspend_noirq()
2629 clk_disable(sport->clk_ipg); in imx_uart_suspend_noirq()
2638 struct imx_port *sport = dev_get_drvdata(dev); in imx_uart_resume_noirq() local
2643 ret = clk_enable(sport->clk_ipg); in imx_uart_resume_noirq()
2647 imx_uart_restore_context(sport); in imx_uart_resume_noirq()
2654 struct imx_port *sport = dev_get_drvdata(dev); in imx_uart_suspend() local
2657 uart_suspend_port(&imx_uart_uart_driver, &sport->port); in imx_uart_suspend()
2658 disable_irq(sport->port.irq); in imx_uart_suspend()
2660 ret = clk_prepare_enable(sport->clk_ipg); in imx_uart_suspend()
2665 imx_uart_enable_wakeup(sport, true); in imx_uart_suspend()
2672 struct imx_port *sport = dev_get_drvdata(dev); in imx_uart_resume() local
2675 imx_uart_enable_wakeup(sport, false); in imx_uart_resume()
2677 uart_resume_port(&imx_uart_uart_driver, &sport->port); in imx_uart_resume()
2678 enable_irq(sport->port.irq); in imx_uart_resume()
2680 clk_disable_unprepare(sport->clk_ipg); in imx_uart_resume()
2687 struct imx_port *sport = dev_get_drvdata(dev); in imx_uart_freeze() local
2689 uart_suspend_port(&imx_uart_uart_driver, &sport->port); in imx_uart_freeze()
2691 return clk_prepare_enable(sport->clk_ipg); in imx_uart_freeze()
2696 struct imx_port *sport = dev_get_drvdata(dev); in imx_uart_thaw() local
2698 uart_resume_port(&imx_uart_uart_driver, &sport->port); in imx_uart_thaw()
2700 clk_disable_unprepare(sport->clk_ipg); in imx_uart_thaw()