Lines Matching refs:sport
362 static inline bool is_layerscape_lpuart(struct lpuart_port *sport) in is_layerscape_lpuart() argument
364 return (sport->devtype == LS1021A_LPUART || in is_layerscape_lpuart()
365 sport->devtype == LS1028A_LPUART); in is_layerscape_lpuart()
368 static inline bool is_imx7ulp_lpuart(struct lpuart_port *sport) in is_imx7ulp_lpuart() argument
370 return sport->devtype == IMX7ULP_LPUART; in is_imx7ulp_lpuart()
373 static inline bool is_imx8ulp_lpuart(struct lpuart_port *sport) in is_imx8ulp_lpuart() argument
375 return sport->devtype == IMX8ULP_LPUART; in is_imx8ulp_lpuart()
378 static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport) in is_imx8qxp_lpuart() argument
380 return sport->devtype == IMX8QXP_LPUART; in is_imx8qxp_lpuart()
408 static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en) in __lpuart_enable_clks() argument
413 ret = clk_prepare_enable(sport->ipg_clk); in __lpuart_enable_clks()
417 ret = clk_prepare_enable(sport->baud_clk); in __lpuart_enable_clks()
419 clk_disable_unprepare(sport->ipg_clk); in __lpuart_enable_clks()
423 clk_disable_unprepare(sport->baud_clk); in __lpuart_enable_clks()
424 clk_disable_unprepare(sport->ipg_clk); in __lpuart_enable_clks()
430 static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport) in lpuart_get_baud_clk_rate() argument
432 if (is_imx8qxp_lpuart(sport)) in lpuart_get_baud_clk_rate()
433 return clk_get_rate(sport->baud_clk); in lpuart_get_baud_clk_rate()
435 return clk_get_rate(sport->ipg_clk); in lpuart_get_baud_clk_rate()
475 static void lpuart_dma_tx(struct lpuart_port *sport) in lpuart_dma_tx() argument
477 struct tty_port *tport = &sport->port.state->port; in lpuart_dma_tx()
478 struct scatterlist *sgl = sport->tx_sgl; in lpuart_dma_tx()
479 struct device *dev = sport->port.dev; in lpuart_dma_tx()
480 struct dma_chan *chan = sport->dma_tx_chan; in lpuart_dma_tx()
483 if (sport->dma_tx_in_progress) in lpuart_dma_tx()
486 sg_init_table(sgl, ARRAY_SIZE(sport->tx_sgl)); in lpuart_dma_tx()
487 sport->dma_tx_bytes = kfifo_len(&tport->xmit_fifo); in lpuart_dma_tx()
488 sport->dma_tx_nents = kfifo_dma_out_prepare(&tport->xmit_fifo, sgl, in lpuart_dma_tx()
489 ARRAY_SIZE(sport->tx_sgl), sport->dma_tx_bytes); in lpuart_dma_tx()
491 ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents, in lpuart_dma_tx()
498 sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl, in lpuart_dma_tx()
501 if (!sport->dma_tx_desc) { in lpuart_dma_tx()
502 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, in lpuart_dma_tx()
508 sport->dma_tx_desc->callback = lpuart_dma_tx_complete; in lpuart_dma_tx()
509 sport->dma_tx_desc->callback_param = sport; in lpuart_dma_tx()
510 sport->dma_tx_in_progress = true; in lpuart_dma_tx()
511 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc); in lpuart_dma_tx()
523 struct lpuart_port *sport = arg; in lpuart_dma_tx_complete() local
524 struct scatterlist *sgl = &sport->tx_sgl[0]; in lpuart_dma_tx_complete()
525 struct tty_port *tport = &sport->port.state->port; in lpuart_dma_tx_complete()
526 struct dma_chan *chan = sport->dma_tx_chan; in lpuart_dma_tx_complete()
529 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_dma_tx_complete()
530 if (!sport->dma_tx_in_progress) { in lpuart_dma_tx_complete()
531 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_dma_tx_complete()
535 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, in lpuart_dma_tx_complete()
538 uart_xmit_advance(&sport->port, sport->dma_tx_bytes); in lpuart_dma_tx_complete()
539 sport->dma_tx_in_progress = false; in lpuart_dma_tx_complete()
540 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_dma_tx_complete()
543 uart_write_wakeup(&sport->port); in lpuart_dma_tx_complete()
545 if (waitqueue_active(&sport->dma_wait)) { in lpuart_dma_tx_complete()
546 wake_up(&sport->dma_wait); in lpuart_dma_tx_complete()
550 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_dma_tx_complete()
552 if (!lpuart_stopped_or_empty(&sport->port)) in lpuart_dma_tx_complete()
553 lpuart_dma_tx(sport); in lpuart_dma_tx_complete()
555 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_dma_tx_complete()
558 static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport) in lpuart_dma_datareg_addr() argument
560 switch (sport->port.iotype) { in lpuart_dma_datareg_addr()
562 return sport->port.mapbase + UARTDATA; in lpuart_dma_datareg_addr()
564 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1; in lpuart_dma_datareg_addr()
566 return sport->port.mapbase + UARTDR; in lpuart_dma_datareg_addr()
571 struct lpuart_port *sport = container_of(port, in lpuart_dma_tx_request() local
576 dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport); in lpuart_dma_tx_request()
580 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig); in lpuart_dma_tx_request()
583 dev_err(sport->port.dev, in lpuart_dma_tx_request()
591 static bool lpuart_is_32(struct lpuart_port *sport) in lpuart_is_32() argument
593 return sport->port.iotype == UPIO_MEM32 || in lpuart_is_32()
594 sport->port.iotype == UPIO_MEM32BE; in lpuart_is_32()
599 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); in lpuart_flush_buffer() local
600 struct dma_chan *chan = sport->dma_tx_chan; in lpuart_flush_buffer()
603 if (sport->lpuart_dma_tx_use) { in lpuart_flush_buffer()
604 if (sport->dma_tx_in_progress) { in lpuart_flush_buffer()
605 dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0], in lpuart_flush_buffer()
606 sport->dma_tx_nents, DMA_TO_DEVICE); in lpuart_flush_buffer()
607 sport->dma_tx_in_progress = false; in lpuart_flush_buffer()
612 if (lpuart_is_32(sport)) { in lpuart_flush_buffer()
613 val = lpuart32_read(&sport->port, UARTFIFO); in lpuart_flush_buffer()
615 lpuart32_write(&sport->port, val, UARTFIFO); in lpuart_flush_buffer()
617 val = readb(sport->port.membase + UARTCFIFO); in lpuart_flush_buffer()
619 writeb(val, sport->port.membase + UARTCFIFO); in lpuart_flush_buffer()
641 struct lpuart_port *sport = container_of(port, in lpuart_poll_init() local
646 sport->port.fifosize = 0; in lpuart_poll_init()
648 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_poll_init()
650 writeb(0, sport->port.membase + UARTCR2); in lpuart_poll_init()
652 temp = readb(sport->port.membase + UARTPFIFO); in lpuart_poll_init()
655 sport->port.membase + UARTPFIFO); in lpuart_poll_init()
659 sport->port.membase + UARTCFIFO); in lpuart_poll_init()
662 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { in lpuart_poll_init()
663 readb(sport->port.membase + UARTDR); in lpuart_poll_init()
664 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); in lpuart_poll_init()
667 writeb(0, sport->port.membase + UARTTWFIFO); in lpuart_poll_init()
668 writeb(1, sport->port.membase + UARTRWFIFO); in lpuart_poll_init()
671 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2); in lpuart_poll_init()
672 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_poll_init()
695 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); in lpuart32_poll_init() local
698 sport->port.fifosize = 0; in lpuart32_poll_init()
700 uart_port_lock_irqsave(&sport->port, &flags); in lpuart32_poll_init()
703 lpuart32_write(&sport->port, 0, UARTCTRL); in lpuart32_poll_init()
705 temp = lpuart32_read(&sport->port, UARTFIFO); in lpuart32_poll_init()
708 lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO); in lpuart32_poll_init()
711 lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO); in lpuart32_poll_init()
714 if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) { in lpuart32_poll_init()
715 lpuart32_read(&sport->port, UARTDATA); in lpuart32_poll_init()
716 lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO); in lpuart32_poll_init()
720 lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL); in lpuart32_poll_init()
721 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart32_poll_init()
741 static inline void lpuart_transmit_buffer(struct lpuart_port *sport) in lpuart_transmit_buffer() argument
743 struct uart_port *port = &sport->port; in lpuart_transmit_buffer()
747 readb(port->membase + UARTTCFIFO) < sport->txfifo_size, in lpuart_transmit_buffer()
751 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport) in lpuart32_transmit_buffer() argument
753 struct tty_port *tport = &sport->port.state->port; in lpuart32_transmit_buffer()
757 if (sport->port.x_char) { in lpuart32_transmit_buffer()
758 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA); in lpuart32_transmit_buffer()
759 sport->port.icount.tx++; in lpuart32_transmit_buffer()
760 sport->port.x_char = 0; in lpuart32_transmit_buffer()
764 if (lpuart_stopped_or_empty(&sport->port)) { in lpuart32_transmit_buffer()
765 lpuart32_stop_tx(&sport->port); in lpuart32_transmit_buffer()
769 txcnt = lpuart32_read(&sport->port, UARTWATER); in lpuart32_transmit_buffer()
772 while (txcnt < sport->txfifo_size && in lpuart32_transmit_buffer()
773 uart_fifo_get(&sport->port, &c)) { in lpuart32_transmit_buffer()
774 lpuart32_write(&sport->port, c, UARTDATA); in lpuart32_transmit_buffer()
775 txcnt = lpuart32_read(&sport->port, UARTWATER); in lpuart32_transmit_buffer()
781 uart_write_wakeup(&sport->port); in lpuart32_transmit_buffer()
784 lpuart32_stop_tx(&sport->port); in lpuart32_transmit_buffer()
789 struct lpuart_port *sport = container_of(port, in lpuart_start_tx() local
796 if (sport->lpuart_dma_tx_use) { in lpuart_start_tx()
798 lpuart_dma_tx(sport); in lpuart_start_tx()
801 lpuart_transmit_buffer(sport); in lpuart_start_tx()
807 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); in lpuart32_start_tx() local
810 if (sport->lpuart_dma_tx_use) { in lpuart32_start_tx()
812 lpuart_dma_tx(sport); in lpuart32_start_tx()
818 lpuart32_transmit_buffer(sport); in lpuart32_start_tx()
839 struct lpuart_port *sport = container_of(port, in lpuart_tx_empty() local
844 if (sport->dma_tx_in_progress) in lpuart_tx_empty()
855 struct lpuart_port *sport = container_of(port, in lpuart32_tx_empty() local
861 if (sport->dma_tx_in_progress) in lpuart32_tx_empty()
875 static void lpuart_txint(struct lpuart_port *sport) in lpuart_txint() argument
877 uart_port_lock(&sport->port); in lpuart_txint()
878 lpuart_transmit_buffer(sport); in lpuart_txint()
879 uart_port_unlock(&sport->port); in lpuart_txint()
882 static void lpuart_rxint(struct lpuart_port *sport) in lpuart_rxint() argument
885 struct tty_port *port = &sport->port.state->port; in lpuart_rxint()
888 uart_port_lock(&sport->port); in lpuart_rxint()
890 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { in lpuart_rxint()
892 sport->port.icount.rx++; in lpuart_rxint()
897 sr = readb(sport->port.membase + UARTSR1); in lpuart_rxint()
898 rx = readb(sport->port.membase + UARTDR); in lpuart_rxint()
900 if (uart_prepare_sysrq_char(&sport->port, rx)) in lpuart_rxint()
905 sport->port.icount.parity++; in lpuart_rxint()
907 sport->port.icount.frame++; in lpuart_rxint()
912 if (sr & sport->port.ignore_status_mask) { in lpuart_rxint()
918 sr &= sport->port.read_status_mask; in lpuart_rxint()
928 sport->port.sysrq = 0; in lpuart_rxint()
932 sport->port.icount.buf_overrun++; in lpuart_rxint()
937 sport->port.icount.overrun += overrun; in lpuart_rxint()
943 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); in lpuart_rxint()
944 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO); in lpuart_rxint()
947 uart_unlock_and_check_sysrq(&sport->port); in lpuart_rxint()
952 static void lpuart32_txint(struct lpuart_port *sport) in lpuart32_txint() argument
954 uart_port_lock(&sport->port); in lpuart32_txint()
955 lpuart32_transmit_buffer(sport); in lpuart32_txint()
956 uart_port_unlock(&sport->port); in lpuart32_txint()
959 static void lpuart32_rxint(struct lpuart_port *sport) in lpuart32_rxint() argument
962 struct tty_port *port = &sport->port.state->port; in lpuart32_rxint()
966 uart_port_lock(&sport->port); in lpuart32_rxint()
968 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) { in lpuart32_rxint()
970 sport->port.icount.rx++; in lpuart32_rxint()
975 sr = lpuart32_read(&sport->port, UARTSTAT); in lpuart32_rxint()
976 rx = lpuart32_read(&sport->port, UARTDATA); in lpuart32_rxint()
985 if (is_break && uart_handle_break(&sport->port)) in lpuart32_rxint()
988 if (uart_prepare_sysrq_char(&sport->port, rx)) in lpuart32_rxint()
993 sport->port.icount.parity++; in lpuart32_rxint()
996 sport->port.icount.brk++; in lpuart32_rxint()
998 sport->port.icount.frame++; in lpuart32_rxint()
1002 sport->port.icount.overrun++; in lpuart32_rxint()
1004 if (sr & sport->port.ignore_status_mask) { in lpuart32_rxint()
1010 sr &= sport->port.read_status_mask; in lpuart32_rxint()
1025 if (sport->is_cs7) in lpuart32_rxint()
1029 sport->port.icount.buf_overrun++; in lpuart32_rxint()
1033 uart_unlock_and_check_sysrq(&sport->port); in lpuart32_rxint()
1040 struct lpuart_port *sport = dev_id; in lpuart_int() local
1043 sts = readb(sport->port.membase + UARTSR1); in lpuart_int()
1046 if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) { in lpuart_int()
1047 readb(sport->port.membase + UARTDR); in lpuart_int()
1048 uart_handle_break(&sport->port); in lpuart_int()
1050 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); in lpuart_int()
1054 if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use) in lpuart_int()
1055 lpuart_rxint(sport); in lpuart_int()
1057 if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use) in lpuart_int()
1058 lpuart_txint(sport); in lpuart_int()
1073 static void lpuart_handle_sysrq(struct lpuart_port *sport) in lpuart_handle_sysrq() argument
1075 struct circ_buf *ring = &sport->rx_ring; in lpuart_handle_sysrq()
1079 count = sport->rx_sgl.length - ring->tail; in lpuart_handle_sysrq()
1080 lpuart_handle_sysrq_chars(&sport->port, in lpuart_handle_sysrq()
1087 lpuart_handle_sysrq_chars(&sport->port, in lpuart_handle_sysrq()
1104 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport) in lpuart_copy_rx_to_tty() argument
1106 struct tty_port *port = &sport->port.state->port; in lpuart_copy_rx_to_tty()
1109 struct dma_chan *chan = sport->dma_rx_chan; in lpuart_copy_rx_to_tty()
1110 struct circ_buf *ring = &sport->rx_ring; in lpuart_copy_rx_to_tty()
1114 if (lpuart_is_32(sport)) { in lpuart_copy_rx_to_tty()
1115 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT); in lpuart_copy_rx_to_tty()
1119 lpuart32_write(&sport->port, sr, UARTSTAT); in lpuart_copy_rx_to_tty()
1122 sport->port.icount.parity++; in lpuart_copy_rx_to_tty()
1124 sport->port.icount.frame++; in lpuart_copy_rx_to_tty()
1127 unsigned char sr = readb(sport->port.membase + UARTSR1); in lpuart_copy_rx_to_tty()
1133 cr2 = readb(sport->port.membase + UARTCR2); in lpuart_copy_rx_to_tty()
1135 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_copy_rx_to_tty()
1138 readb(sport->port.membase + UARTDR); in lpuart_copy_rx_to_tty()
1141 sport->port.icount.parity++; in lpuart_copy_rx_to_tty()
1143 sport->port.icount.frame++; in lpuart_copy_rx_to_tty()
1153 if (readb(sport->port.membase + UARTSFIFO) & in lpuart_copy_rx_to_tty()
1156 sport->port.membase + UARTSFIFO); in lpuart_copy_rx_to_tty()
1158 sport->port.membase + UARTCFIFO); in lpuart_copy_rx_to_tty()
1162 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_copy_rx_to_tty()
1166 async_tx_ack(sport->dma_rx_desc); in lpuart_copy_rx_to_tty()
1168 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_copy_rx_to_tty()
1170 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); in lpuart_copy_rx_to_tty()
1172 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); in lpuart_copy_rx_to_tty()
1173 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_copy_rx_to_tty()
1178 dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1, in lpuart_copy_rx_to_tty()
1188 ring->head = sport->rx_sgl.length - state.residue; in lpuart_copy_rx_to_tty()
1189 BUG_ON(ring->head > sport->rx_sgl.length); in lpuart_copy_rx_to_tty()
1194 if (sport->port.sysrq) { in lpuart_copy_rx_to_tty()
1195 lpuart_handle_sysrq(sport); in lpuart_copy_rx_to_tty()
1212 count = sport->rx_sgl.length - ring->tail; in lpuart_copy_rx_to_tty()
1215 count, sport->is_cs7); in lpuart_copy_rx_to_tty()
1217 sport->port.icount.buf_overrun++; in lpuart_copy_rx_to_tty()
1219 sport->port.icount.rx += copied; in lpuart_copy_rx_to_tty()
1226 count, sport->is_cs7); in lpuart_copy_rx_to_tty()
1228 sport->port.icount.buf_overrun++; in lpuart_copy_rx_to_tty()
1230 if (ring->head >= sport->rx_sgl.length) in lpuart_copy_rx_to_tty()
1233 sport->port.icount.rx += copied; in lpuart_copy_rx_to_tty()
1236 sport->last_residue = state.residue; in lpuart_copy_rx_to_tty()
1239 dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1, in lpuart_copy_rx_to_tty()
1242 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_copy_rx_to_tty()
1245 if (!sport->dma_idle_int) in lpuart_copy_rx_to_tty()
1246 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout); in lpuart_copy_rx_to_tty()
1251 struct lpuart_port *sport = arg; in lpuart_dma_rx_complete() local
1253 lpuart_copy_rx_to_tty(sport); in lpuart_dma_rx_complete()
1256 static void lpuart32_dma_idleint(struct lpuart_port *sport) in lpuart32_dma_idleint() argument
1259 struct dma_chan *chan = sport->dma_rx_chan; in lpuart32_dma_idleint()
1260 struct circ_buf *ring = &sport->rx_ring; in lpuart32_dma_idleint()
1264 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); in lpuart32_dma_idleint()
1266 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); in lpuart32_dma_idleint()
1270 ring->head = sport->rx_sgl.length - state.residue; in lpuart32_dma_idleint()
1271 count = CIRC_CNT(ring->head, ring->tail, sport->rx_sgl.length); in lpuart32_dma_idleint()
1275 lpuart_copy_rx_to_tty(sport); in lpuart32_dma_idleint()
1280 struct lpuart_port *sport = dev_id; in lpuart32_int() local
1283 sts = lpuart32_read(&sport->port, UARTSTAT); in lpuart32_int()
1284 rxcount = lpuart32_read(&sport->port, UARTWATER); in lpuart32_int()
1287 if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use) in lpuart32_int()
1288 lpuart32_rxint(sport); in lpuart32_int()
1290 if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use) in lpuart32_int()
1291 lpuart32_txint(sport); in lpuart32_int()
1293 if ((sts & UARTSTAT_IDLE) && sport->lpuart_dma_rx_use && sport->dma_idle_int) in lpuart32_int()
1294 lpuart32_dma_idleint(sport); in lpuart32_int()
1296 lpuart32_write(&sport->port, sts, UARTSTAT); in lpuart32_int()
1309 struct lpuart_port *sport = from_timer(sport, t, lpuart_timer); in lpuart_timer_func() local
1311 struct dma_chan *chan = sport->dma_rx_chan; in lpuart_timer_func()
1312 struct circ_buf *ring = &sport->rx_ring; in lpuart_timer_func()
1317 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); in lpuart_timer_func()
1319 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); in lpuart_timer_func()
1323 ring->head = sport->rx_sgl.length - state.residue; in lpuart_timer_func()
1324 count = CIRC_CNT(ring->head, ring->tail, sport->rx_sgl.length); in lpuart_timer_func()
1327 if ((count != 0) && (sport->last_residue == state.residue)) in lpuart_timer_func()
1328 lpuart_copy_rx_to_tty(sport); in lpuart_timer_func()
1330 mod_timer(&sport->lpuart_timer, in lpuart_timer_func()
1331 jiffies + sport->dma_rx_timeout); in lpuart_timer_func()
1333 if (uart_port_trylock_irqsave(&sport->port, &flags)) { in lpuart_timer_func()
1334 sport->last_residue = state.residue; in lpuart_timer_func()
1335 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_timer_func()
1339 static inline int lpuart_start_rx_dma(struct lpuart_port *sport) in lpuart_start_rx_dma() argument
1342 struct circ_buf *ring = &sport->rx_ring; in lpuart_start_rx_dma()
1344 struct tty_port *port = &sport->port.state->port; in lpuart_start_rx_dma()
1347 struct dma_chan *chan = sport->dma_rx_chan; in lpuart_start_rx_dma()
1355 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; in lpuart_start_rx_dma()
1356 sport->rx_dma_rng_buf_len = (1 << fls(sport->rx_dma_rng_buf_len)); in lpuart_start_rx_dma()
1357 sport->rx_dma_rng_buf_len = max_t(int, in lpuart_start_rx_dma()
1358 sport->rxfifo_size * 2, in lpuart_start_rx_dma()
1359 sport->rx_dma_rng_buf_len); in lpuart_start_rx_dma()
1364 if (sport->rx_dma_rng_buf_len < 16) in lpuart_start_rx_dma()
1365 sport->rx_dma_rng_buf_len = 16; in lpuart_start_rx_dma()
1367 sport->last_residue = 0; in lpuart_start_rx_dma()
1368 sport->dma_rx_timeout = max(nsecs_to_jiffies( in lpuart_start_rx_dma()
1369 sport->port.frame_time * DMA_RX_IDLE_CHARS), 1UL); in lpuart_start_rx_dma()
1371 ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC); in lpuart_start_rx_dma()
1375 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); in lpuart_start_rx_dma()
1376 nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1, in lpuart_start_rx_dma()
1380 dev_err(sport->port.dev, "DMA Rx mapping error\n"); in lpuart_start_rx_dma()
1384 dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport); in lpuart_start_rx_dma()
1391 dev_err(sport->port.dev, in lpuart_start_rx_dma()
1396 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan, in lpuart_start_rx_dma()
1397 sg_dma_address(&sport->rx_sgl), in lpuart_start_rx_dma()
1398 sport->rx_sgl.length, in lpuart_start_rx_dma()
1399 sport->rx_sgl.length / 2, in lpuart_start_rx_dma()
1402 if (!sport->dma_rx_desc) { in lpuart_start_rx_dma()
1403 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n"); in lpuart_start_rx_dma()
1407 sport->dma_rx_desc->callback = lpuart_dma_rx_complete; in lpuart_start_rx_dma()
1408 sport->dma_rx_desc->callback_param = sport; in lpuart_start_rx_dma()
1409 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc); in lpuart_start_rx_dma()
1412 if (lpuart_is_32(sport)) { in lpuart_start_rx_dma()
1413 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD); in lpuart_start_rx_dma()
1415 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD); in lpuart_start_rx_dma()
1417 if (sport->dma_idle_int) { in lpuart_start_rx_dma()
1418 unsigned long ctrl = lpuart32_read(&sport->port, UARTCTRL); in lpuart_start_rx_dma()
1420 lpuart32_write(&sport->port, ctrl | UARTCTRL_ILIE, UARTCTRL); in lpuart_start_rx_dma()
1423 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS, in lpuart_start_rx_dma()
1424 sport->port.membase + UARTCR5); in lpuart_start_rx_dma()
1432 struct lpuart_port *sport = container_of(port, in lpuart_dma_rx_free() local
1434 struct dma_chan *chan = sport->dma_rx_chan; in lpuart_dma_rx_free()
1437 if (!sport->dma_idle_int) in lpuart_dma_rx_free()
1438 del_timer_sync(&sport->lpuart_timer); in lpuart_dma_rx_free()
1440 dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); in lpuart_dma_rx_free()
1441 kfree(sport->rx_ring.buf); in lpuart_dma_rx_free()
1442 sport->rx_ring.tail = 0; in lpuart_dma_rx_free()
1443 sport->rx_ring.head = 0; in lpuart_dma_rx_free()
1444 sport->dma_rx_desc = NULL; in lpuart_dma_rx_free()
1445 sport->dma_rx_cookie = -EINVAL; in lpuart_dma_rx_free()
1451 struct lpuart_port *sport = container_of(port, in lpuart_config_rs485() local
1454 u8 modem = readb(sport->port.membase + UARTMODEM) & in lpuart_config_rs485()
1456 writeb(modem, sport->port.membase + UARTMODEM); in lpuart_config_rs485()
1474 writeb(modem, sport->port.membase + UARTMODEM); in lpuart_config_rs485()
1481 struct lpuart_port *sport = container_of(port, in lpuart32_config_rs485() local
1484 unsigned long modem = lpuart32_read(&sport->port, UARTMODIR) in lpuart32_config_rs485()
1486 lpuart32_write(&sport->port, modem, UARTMODIR); in lpuart32_config_rs485()
1504 lpuart32_write(&sport->port, modem, UARTMODIR); in lpuart32_config_rs485()
1606 static void lpuart_setup_watermark(struct lpuart_port *sport) in lpuart_setup_watermark() argument
1611 cr2 = readb(sport->port.membase + UARTCR2); in lpuart_setup_watermark()
1615 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_setup_watermark()
1617 val = readb(sport->port.membase + UARTPFIFO); in lpuart_setup_watermark()
1619 sport->port.membase + UARTPFIFO); in lpuart_setup_watermark()
1623 sport->port.membase + UARTCFIFO); in lpuart_setup_watermark()
1626 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { in lpuart_setup_watermark()
1627 readb(sport->port.membase + UARTDR); in lpuart_setup_watermark()
1628 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); in lpuart_setup_watermark()
1631 if (uart_console(&sport->port)) in lpuart_setup_watermark()
1632 sport->rx_watermark = 1; in lpuart_setup_watermark()
1633 writeb(0, sport->port.membase + UARTTWFIFO); in lpuart_setup_watermark()
1634 writeb(sport->rx_watermark, sport->port.membase + UARTRWFIFO); in lpuart_setup_watermark()
1637 writeb(cr2_saved, sport->port.membase + UARTCR2); in lpuart_setup_watermark()
1640 static void lpuart_setup_watermark_enable(struct lpuart_port *sport) in lpuart_setup_watermark_enable() argument
1644 lpuart_setup_watermark(sport); in lpuart_setup_watermark_enable()
1646 cr2 = readb(sport->port.membase + UARTCR2); in lpuart_setup_watermark_enable()
1648 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_setup_watermark_enable()
1651 static void lpuart32_setup_watermark(struct lpuart_port *sport) in lpuart32_setup_watermark() argument
1656 ctrl = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_setup_watermark()
1660 lpuart32_write(&sport->port, ctrl, UARTCTRL); in lpuart32_setup_watermark()
1663 val = lpuart32_read(&sport->port, UARTFIFO); in lpuart32_setup_watermark()
1667 lpuart32_write(&sport->port, val, UARTFIFO); in lpuart32_setup_watermark()
1670 if (uart_console(&sport->port)) in lpuart32_setup_watermark()
1671 sport->rx_watermark = 1; in lpuart32_setup_watermark()
1672 val = (sport->rx_watermark << UARTWATER_RXWATER_OFF) | in lpuart32_setup_watermark()
1674 lpuart32_write(&sport->port, val, UARTWATER); in lpuart32_setup_watermark()
1677 if (!uart_console(&sport->port)) { in lpuart32_setup_watermark()
1678 val = lpuart32_read(&sport->port, UARTMODIR); in lpuart32_setup_watermark()
1679 val |= FIELD_PREP(UARTMODIR_RTSWATER, sport->rxfifo_size >> 1); in lpuart32_setup_watermark()
1680 lpuart32_write(&sport->port, val, UARTMODIR); in lpuart32_setup_watermark()
1684 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL); in lpuart32_setup_watermark()
1687 static void lpuart32_setup_watermark_enable(struct lpuart_port *sport) in lpuart32_setup_watermark_enable() argument
1691 lpuart32_setup_watermark(sport); in lpuart32_setup_watermark_enable()
1693 temp = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_setup_watermark_enable()
1696 lpuart32_write(&sport->port, temp, UARTCTRL); in lpuart32_setup_watermark_enable()
1699 static void rx_dma_timer_init(struct lpuart_port *sport) in rx_dma_timer_init() argument
1701 if (sport->dma_idle_int) in rx_dma_timer_init()
1704 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0); in rx_dma_timer_init()
1705 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout; in rx_dma_timer_init()
1706 add_timer(&sport->lpuart_timer); in rx_dma_timer_init()
1709 static void lpuart_request_dma(struct lpuart_port *sport) in lpuart_request_dma() argument
1711 sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx"); in lpuart_request_dma()
1712 if (IS_ERR(sport->dma_tx_chan)) { in lpuart_request_dma()
1713 dev_dbg_once(sport->port.dev, in lpuart_request_dma()
1715 PTR_ERR(sport->dma_tx_chan)); in lpuart_request_dma()
1716 sport->dma_tx_chan = NULL; in lpuart_request_dma()
1719 sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx"); in lpuart_request_dma()
1720 if (IS_ERR(sport->dma_rx_chan)) { in lpuart_request_dma()
1721 dev_dbg_once(sport->port.dev, in lpuart_request_dma()
1723 PTR_ERR(sport->dma_rx_chan)); in lpuart_request_dma()
1724 sport->dma_rx_chan = NULL; in lpuart_request_dma()
1728 static void lpuart_tx_dma_startup(struct lpuart_port *sport) in lpuart_tx_dma_startup() argument
1733 if (uart_console(&sport->port)) in lpuart_tx_dma_startup()
1736 if (!sport->dma_tx_chan) in lpuart_tx_dma_startup()
1739 ret = lpuart_dma_tx_request(&sport->port); in lpuart_tx_dma_startup()
1743 init_waitqueue_head(&sport->dma_wait); in lpuart_tx_dma_startup()
1744 sport->lpuart_dma_tx_use = true; in lpuart_tx_dma_startup()
1745 if (lpuart_is_32(sport)) { in lpuart_tx_dma_startup()
1746 uartbaud = lpuart32_read(&sport->port, UARTBAUD); in lpuart_tx_dma_startup()
1747 lpuart32_write(&sport->port, in lpuart_tx_dma_startup()
1750 writeb(readb(sport->port.membase + UARTCR5) | in lpuart_tx_dma_startup()
1751 UARTCR5_TDMAS, sport->port.membase + UARTCR5); in lpuart_tx_dma_startup()
1757 sport->lpuart_dma_tx_use = false; in lpuart_tx_dma_startup()
1760 static void lpuart_rx_dma_startup(struct lpuart_port *sport) in lpuart_rx_dma_startup() argument
1765 if (uart_console(&sport->port)) in lpuart_rx_dma_startup()
1768 if (!sport->dma_rx_chan) in lpuart_rx_dma_startup()
1772 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); in lpuart_rx_dma_startup()
1774 ret = lpuart_start_rx_dma(sport); in lpuart_rx_dma_startup()
1778 if (!sport->dma_rx_timeout) in lpuart_rx_dma_startup()
1779 sport->dma_rx_timeout = 1; in lpuart_rx_dma_startup()
1781 sport->lpuart_dma_rx_use = true; in lpuart_rx_dma_startup()
1782 rx_dma_timer_init(sport); in lpuart_rx_dma_startup()
1784 if (sport->port.has_sysrq && !lpuart_is_32(sport)) { in lpuart_rx_dma_startup()
1785 cr3 = readb(sport->port.membase + UARTCR3); in lpuart_rx_dma_startup()
1787 writeb(cr3, sport->port.membase + UARTCR3); in lpuart_rx_dma_startup()
1793 sport->lpuart_dma_rx_use = false; in lpuart_rx_dma_startup()
1796 static void lpuart_hw_setup(struct lpuart_port *sport) in lpuart_hw_setup() argument
1800 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_hw_setup()
1802 lpuart_setup_watermark_enable(sport); in lpuart_hw_setup()
1804 lpuart_rx_dma_startup(sport); in lpuart_hw_setup()
1805 lpuart_tx_dma_startup(sport); in lpuart_hw_setup()
1807 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_hw_setup()
1812 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); in lpuart_startup() local
1816 temp = readb(sport->port.membase + UARTPFIFO); in lpuart_startup()
1818 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) & in lpuart_startup()
1820 sport->port.fifosize = sport->txfifo_size; in lpuart_startup()
1822 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) & in lpuart_startup()
1825 lpuart_request_dma(sport); in lpuart_startup()
1826 lpuart_hw_setup(sport); in lpuart_startup()
1831 static void lpuart32_hw_disable(struct lpuart_port *sport) in lpuart32_hw_disable() argument
1835 temp = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_hw_disable()
1838 lpuart32_write(&sport->port, temp, UARTCTRL); in lpuart32_hw_disable()
1841 static void lpuart32_configure(struct lpuart_port *sport) in lpuart32_configure() argument
1845 temp = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_configure()
1846 if (!sport->lpuart_dma_rx_use) in lpuart32_configure()
1848 if (!sport->lpuart_dma_tx_use) in lpuart32_configure()
1850 lpuart32_write(&sport->port, temp, UARTCTRL); in lpuart32_configure()
1853 static void lpuart32_hw_setup(struct lpuart_port *sport) in lpuart32_hw_setup() argument
1857 uart_port_lock_irqsave(&sport->port, &flags); in lpuart32_hw_setup()
1859 lpuart32_hw_disable(sport); in lpuart32_hw_setup()
1861 lpuart_rx_dma_startup(sport); in lpuart32_hw_setup()
1862 lpuart_tx_dma_startup(sport); in lpuart32_hw_setup()
1864 lpuart32_setup_watermark_enable(sport); in lpuart32_hw_setup()
1865 lpuart32_configure(sport); in lpuart32_hw_setup()
1867 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart32_hw_setup()
1872 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); in lpuart32_startup() local
1876 temp = lpuart32_read(&sport->port, UARTFIFO); in lpuart32_startup()
1878 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) & in lpuart32_startup()
1880 sport->port.fifosize = sport->txfifo_size; in lpuart32_startup()
1882 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) & in lpuart32_startup()
1890 if (is_layerscape_lpuart(sport)) { in lpuart32_startup()
1891 sport->rxfifo_size = 16; in lpuart32_startup()
1892 sport->txfifo_size = 16; in lpuart32_startup()
1893 sport->port.fifosize = sport->txfifo_size; in lpuart32_startup()
1896 lpuart_request_dma(sport); in lpuart32_startup()
1897 lpuart32_hw_setup(sport); in lpuart32_startup()
1902 static void lpuart_dma_shutdown(struct lpuart_port *sport) in lpuart_dma_shutdown() argument
1904 if (sport->lpuart_dma_rx_use) { in lpuart_dma_shutdown()
1905 lpuart_dma_rx_free(&sport->port); in lpuart_dma_shutdown()
1906 sport->lpuart_dma_rx_use = false; in lpuart_dma_shutdown()
1909 if (sport->lpuart_dma_tx_use) { in lpuart_dma_shutdown()
1910 if (wait_event_interruptible_timeout(sport->dma_wait, in lpuart_dma_shutdown()
1911 !sport->dma_tx_in_progress, msecs_to_jiffies(300)) <= 0) { in lpuart_dma_shutdown()
1912 sport->dma_tx_in_progress = false; in lpuart_dma_shutdown()
1913 dmaengine_terminate_sync(sport->dma_tx_chan); in lpuart_dma_shutdown()
1915 sport->lpuart_dma_tx_use = false; in lpuart_dma_shutdown()
1918 if (sport->dma_tx_chan) in lpuart_dma_shutdown()
1919 dma_release_channel(sport->dma_tx_chan); in lpuart_dma_shutdown()
1920 if (sport->dma_rx_chan) in lpuart_dma_shutdown()
1921 dma_release_channel(sport->dma_rx_chan); in lpuart_dma_shutdown()
1926 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); in lpuart_shutdown() local
1940 lpuart_dma_shutdown(sport); in lpuart_shutdown()
1945 struct lpuart_port *sport = in lpuart32_shutdown() local
1953 temp = lpuart32_read(&sport->port, UARTSTAT); in lpuart32_shutdown()
1954 lpuart32_write(&sport->port, temp, UARTSTAT); in lpuart32_shutdown()
1969 lpuart_dma_shutdown(sport); in lpuart32_shutdown()
1976 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); in lpuart_set_termios() local
1983 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); in lpuart_set_termios()
1984 old_cr2 = readb(sport->port.membase + UARTCR2); in lpuart_set_termios()
1985 cr3 = readb(sport->port.membase + UARTCR3); in lpuart_set_termios()
1986 cr4 = readb(sport->port.membase + UARTCR4); in lpuart_set_termios()
1987 bdh = readb(sport->port.membase + UARTBDH); in lpuart_set_termios()
1988 modem = readb(sport->port.membase + UARTMODEM); in lpuart_set_termios()
2020 if (sport->port.rs485.flags & SER_RS485_ENABLED) in lpuart_set_termios()
2064 if (old && sport->lpuart_dma_rx_use) in lpuart_set_termios()
2065 lpuart_dma_rx_free(&sport->port); in lpuart_set_termios()
2067 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_set_termios()
2069 sport->port.read_status_mask = 0; in lpuart_set_termios()
2071 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE; in lpuart_set_termios()
2073 sport->port.read_status_mask |= UARTSR1_FE; in lpuart_set_termios()
2076 sport->port.ignore_status_mask = 0; in lpuart_set_termios()
2078 sport->port.ignore_status_mask |= UARTSR1_PE; in lpuart_set_termios()
2080 sport->port.ignore_status_mask |= UARTSR1_FE; in lpuart_set_termios()
2086 sport->port.ignore_status_mask |= UARTSR1_OR; in lpuart_set_termios()
2093 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); in lpuart_set_termios()
2097 sport->port.membase + UARTCR2); in lpuart_set_termios()
2099 sbr = sport->port.uartclk / (16 * baud); in lpuart_set_termios()
2100 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud; in lpuart_set_termios()
2105 writeb(cr4 | brfa, sport->port.membase + UARTCR4); in lpuart_set_termios()
2106 writeb(bdh, sport->port.membase + UARTBDH); in lpuart_set_termios()
2107 writeb(sbr & 0xFF, sport->port.membase + UARTBDL); in lpuart_set_termios()
2108 writeb(cr3, sport->port.membase + UARTCR3); in lpuart_set_termios()
2109 writeb(cr1, sport->port.membase + UARTCR1); in lpuart_set_termios()
2110 writeb(modem, sport->port.membase + UARTMODEM); in lpuart_set_termios()
2113 writeb(old_cr2, sport->port.membase + UARTCR2); in lpuart_set_termios()
2115 if (old && sport->lpuart_dma_rx_use) { in lpuart_set_termios()
2116 if (!lpuart_start_rx_dma(sport)) in lpuart_set_termios()
2117 rx_dma_timer_init(sport); in lpuart_set_termios()
2119 sport->lpuart_dma_rx_use = false; in lpuart_set_termios()
2122 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_set_termios()
2201 static void lpuart32_serial_setbrg(struct lpuart_port *sport, in lpuart32_serial_setbrg() argument
2204 __lpuart32_serial_setbrg(&sport->port, baudrate, in lpuart32_serial_setbrg()
2205 sport->lpuart_dma_rx_use, in lpuart32_serial_setbrg()
2206 sport->lpuart_dma_tx_use); in lpuart32_serial_setbrg()
2214 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); in lpuart32_set_termios() local
2220 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_set_termios()
2221 bd = lpuart32_read(&sport->port, UARTBAUD); in lpuart32_set_termios()
2222 modem = lpuart32_read(&sport->port, UARTMODIR); in lpuart32_set_termios()
2223 sport->is_cs7 = false; in lpuart32_set_termios()
2255 if (sport->port.rs485.flags & SER_RS485_ENABLED) in lpuart32_set_termios()
2299 if (old && sport->lpuart_dma_rx_use) in lpuart32_set_termios()
2300 lpuart_dma_rx_free(&sport->port); in lpuart32_set_termios()
2302 uart_port_lock_irqsave(&sport->port, &flags); in lpuart32_set_termios()
2304 sport->port.read_status_mask = 0; in lpuart32_set_termios()
2306 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE; in lpuart32_set_termios()
2308 sport->port.read_status_mask |= UARTSTAT_FE; in lpuart32_set_termios()
2311 sport->port.ignore_status_mask = 0; in lpuart32_set_termios()
2313 sport->port.ignore_status_mask |= UARTSTAT_PE; in lpuart32_set_termios()
2315 sport->port.ignore_status_mask |= UARTSTAT_FE; in lpuart32_set_termios()
2321 sport->port.ignore_status_mask |= UARTSTAT_OR; in lpuart32_set_termios()
2333 lpuart32_write(&sport->port, 0, UARTMODIR); in lpuart32_set_termios()
2334 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); in lpuart32_set_termios()
2338 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE), in lpuart32_set_termios()
2341 lpuart32_write(&sport->port, bd, UARTBAUD); in lpuart32_set_termios()
2342 lpuart32_serial_setbrg(sport, baud); in lpuart32_set_termios()
2344 lpuart32_write(&sport->port, modem & ~UARTMODIR_TXCTSE, UARTMODIR); in lpuart32_set_termios()
2346 lpuart32_write(&sport->port, ctrl, UARTCTRL); in lpuart32_set_termios()
2348 lpuart32_write(&sport->port, modem, UARTMODIR); in lpuart32_set_termios()
2351 sport->is_cs7 = true; in lpuart32_set_termios()
2353 if (old && sport->lpuart_dma_rx_use) { in lpuart32_set_termios()
2354 if (!lpuart_start_rx_dma(sport)) in lpuart32_set_termios()
2355 rx_dma_timer_init(sport); in lpuart32_set_termios()
2357 sport->lpuart_dma_rx_use = false; in lpuart32_set_termios()
2360 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart32_set_termios()
2472 struct lpuart_port *sport = lpuart_ports[co->index]; in lpuart_console_write() local
2478 locked = uart_port_trylock_irqsave(&sport->port, &flags); in lpuart_console_write()
2480 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_console_write()
2483 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); in lpuart_console_write()
2486 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_console_write()
2488 uart_console_write(&sport->port, s, count, lpuart_console_putchar); in lpuart_console_write()
2491 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); in lpuart_console_write()
2493 writeb(old_cr2, sport->port.membase + UARTCR2); in lpuart_console_write()
2496 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_console_write()
2502 struct lpuart_port *sport = lpuart_ports[co->index]; in lpuart32_console_write() local
2508 locked = uart_port_trylock_irqsave(&sport->port, &flags); in lpuart32_console_write()
2510 uart_port_lock_irqsave(&sport->port, &flags); in lpuart32_console_write()
2513 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_console_write()
2516 lpuart32_write(&sport->port, cr, UARTCTRL); in lpuart32_console_write()
2518 uart_console_write(&sport->port, s, count, lpuart32_console_putchar); in lpuart32_console_write()
2521 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); in lpuart32_console_write()
2523 lpuart32_write(&sport->port, old_cr, UARTCTRL); in lpuart32_console_write()
2526 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart32_console_write()
2534 lpuart_console_get_options(struct lpuart_port *sport, int *baud, in lpuart_console_get_options() argument
2540 cr = readb(sport->port.membase + UARTCR2); in lpuart_console_get_options()
2547 cr = readb(sport->port.membase + UARTCR1); in lpuart_console_get_options()
2562 bdh = readb(sport->port.membase + UARTBDH); in lpuart_console_get_options()
2564 bdl = readb(sport->port.membase + UARTBDL); in lpuart_console_get_options()
2568 brfa = readb(sport->port.membase + UARTCR4); in lpuart_console_get_options()
2571 uartclk = lpuart_get_baud_clk_rate(sport); in lpuart_console_get_options()
2578 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" in lpuart_console_get_options()
2583 lpuart32_console_get_options(struct lpuart_port *sport, int *baud, in lpuart32_console_get_options() argument
2589 cr = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_console_get_options()
2596 cr = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_console_get_options()
2611 bd = lpuart32_read(&sport->port, UARTBAUD); in lpuart32_console_get_options()
2617 uartclk = lpuart_get_baud_clk_rate(sport); in lpuart32_console_get_options()
2624 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" in lpuart32_console_get_options()
2630 struct lpuart_port *sport; in lpuart_console_setup() local
2644 sport = lpuart_ports[co->index]; in lpuart_console_setup()
2645 if (sport == NULL) in lpuart_console_setup()
2651 if (lpuart_is_32(sport)) in lpuart_console_setup()
2652 lpuart32_console_get_options(sport, &baud, &parity, &bits); in lpuart_console_setup()
2654 lpuart_console_get_options(sport, &baud, &parity, &bits); in lpuart_console_setup()
2656 if (lpuart_is_32(sport)) in lpuart_console_setup()
2657 lpuart32_setup_watermark(sport); in lpuart_console_setup()
2659 lpuart_setup_watermark(sport); in lpuart_console_setup()
2661 return uart_set_options(&sport->port, co, baud, parity, bits, flow); in lpuart_console_setup()
2788 static int lpuart_global_reset(struct lpuart_port *sport) in lpuart_global_reset() argument
2790 struct uart_port *port = &sport->port; in lpuart_global_reset()
2796 ret = clk_prepare_enable(sport->ipg_clk); in lpuart_global_reset()
2798 dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n", ret); in lpuart_global_reset()
2802 if (is_imx7ulp_lpuart(sport) || is_imx8ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) { in lpuart_global_reset()
2809 bd = lpuart32_read(&sport->port, UARTBAUD); in lpuart_global_reset()
2812 dev_warn(sport->port.dev, in lpuart_global_reset()
2814 clk_disable_unprepare(sport->ipg_clk); in lpuart_global_reset()
2832 clk_disable_unprepare(sport->ipg_clk); in lpuart_global_reset()
2840 struct lpuart_port *sport; in lpuart_probe() local
2845 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); in lpuart_probe()
2846 if (!sport) in lpuart_probe()
2849 sport->port.membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in lpuart_probe()
2850 if (IS_ERR(sport->port.membase)) in lpuart_probe()
2851 return PTR_ERR(sport->port.membase); in lpuart_probe()
2853 sport->port.membase += sdata->reg_off; in lpuart_probe()
2854 sport->port.mapbase = res->start + sdata->reg_off; in lpuart_probe()
2855 sport->port.dev = &pdev->dev; in lpuart_probe()
2856 sport->port.type = PORT_LPUART; in lpuart_probe()
2857 sport->devtype = sdata->devtype; in lpuart_probe()
2858 sport->rx_watermark = sdata->rx_watermark; in lpuart_probe()
2859 sport->dma_idle_int = is_imx7ulp_lpuart(sport) || is_imx8ulp_lpuart(sport) || in lpuart_probe()
2860 is_imx8qxp_lpuart(sport); in lpuart_probe()
2864 sport->port.irq = ret; in lpuart_probe()
2865 sport->port.iotype = sdata->iotype; in lpuart_probe()
2866 if (lpuart_is_32(sport)) in lpuart_probe()
2867 sport->port.ops = &lpuart32_pops; in lpuart_probe()
2869 sport->port.ops = &lpuart_pops; in lpuart_probe()
2870 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE); in lpuart_probe()
2871 sport->port.flags = UPF_BOOT_AUTOCONF; in lpuart_probe()
2873 if (lpuart_is_32(sport)) in lpuart_probe()
2874 sport->port.rs485_config = lpuart32_config_rs485; in lpuart_probe()
2876 sport->port.rs485_config = lpuart_config_rs485; in lpuart_probe()
2877 sport->port.rs485_supported = lpuart_rs485_supported; in lpuart_probe()
2879 sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); in lpuart_probe()
2880 if (IS_ERR(sport->ipg_clk)) { in lpuart_probe()
2881 ret = PTR_ERR(sport->ipg_clk); in lpuart_probe()
2885 sport->baud_clk = NULL; in lpuart_probe()
2886 if (is_imx8qxp_lpuart(sport)) { in lpuart_probe()
2887 sport->baud_clk = devm_clk_get(&pdev->dev, "baud"); in lpuart_probe()
2888 if (IS_ERR(sport->baud_clk)) { in lpuart_probe()
2889 ret = PTR_ERR(sport->baud_clk); in lpuart_probe()
2903 sport->port.line = ret; in lpuart_probe()
2905 ret = lpuart_enable_clks(sport); in lpuart_probe()
2908 sport->port.uartclk = lpuart_get_baud_clk_rate(sport); in lpuart_probe()
2910 lpuart_ports[sport->port.line] = sport; in lpuart_probe()
2912 platform_set_drvdata(pdev, &sport->port); in lpuart_probe()
2914 if (lpuart_is_32(sport)) { in lpuart_probe()
2928 ret = lpuart_global_reset(sport); in lpuart_probe()
2932 ret = uart_get_rs485_mode(&sport->port); in lpuart_probe()
2936 ret = uart_add_one_port(&lpuart_reg, &sport->port); in lpuart_probe()
2940 ret = devm_request_irq(&pdev->dev, sport->port.irq, handler, 0, in lpuart_probe()
2941 DRIVER_NAME, sport); in lpuart_probe()
2948 uart_remove_one_port(&lpuart_reg, &sport->port); in lpuart_probe()
2955 lpuart_disable_clks(sport); in lpuart_probe()
2961 struct lpuart_port *sport = platform_get_drvdata(pdev); in lpuart_remove() local
2963 uart_remove_one_port(&lpuart_reg, &sport->port); in lpuart_remove()
2965 lpuart_disable_clks(sport); in lpuart_remove()
2967 if (sport->dma_tx_chan) in lpuart_remove()
2968 dma_release_channel(sport->dma_tx_chan); in lpuart_remove()
2970 if (sport->dma_rx_chan) in lpuart_remove()
2971 dma_release_channel(sport->dma_rx_chan); in lpuart_remove()
2981 struct lpuart_port *sport = platform_get_drvdata(pdev); in lpuart_runtime_suspend() local
2983 lpuart_disable_clks(sport); in lpuart_runtime_suspend()
2991 struct lpuart_port *sport = platform_get_drvdata(pdev); in lpuart_runtime_resume() local
2993 return lpuart_enable_clks(sport); in lpuart_runtime_resume()
2996 static void serial_lpuart_enable_wakeup(struct lpuart_port *sport, bool on) in serial_lpuart_enable_wakeup() argument
3000 if (lpuart_is_32(sport)) { in serial_lpuart_enable_wakeup()
3001 val = lpuart32_read(&sport->port, UARTCTRL); in serial_lpuart_enable_wakeup()
3002 baud = lpuart32_read(&sport->port, UARTBAUD); in serial_lpuart_enable_wakeup()
3005 lpuart32_write(&sport->port, 0, UARTWATER); in serial_lpuart_enable_wakeup()
3008 lpuart32_write(&sport->port, UARTSTAT_RXEDGIF, UARTSTAT); in serial_lpuart_enable_wakeup()
3014 lpuart32_write(&sport->port, val, UARTCTRL); in serial_lpuart_enable_wakeup()
3015 lpuart32_write(&sport->port, baud, UARTBAUD); in serial_lpuart_enable_wakeup()
3017 val = readb(sport->port.membase + UARTCR2); in serial_lpuart_enable_wakeup()
3022 writeb(val, sport->port.membase + UARTCR2); in serial_lpuart_enable_wakeup()
3026 static bool lpuart_uport_is_active(struct lpuart_port *sport) in lpuart_uport_is_active() argument
3028 struct tty_port *port = &sport->port.state->port; in lpuart_uport_is_active()
3041 (!console_suspend_enabled && uart_console(&sport->port))) in lpuart_uport_is_active()
3049 struct lpuart_port *sport = dev_get_drvdata(dev); in lpuart_suspend_noirq() local
3050 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); in lpuart_suspend_noirq()
3052 if (lpuart_uport_is_active(sport)) in lpuart_suspend_noirq()
3053 serial_lpuart_enable_wakeup(sport, !!irq_wake); in lpuart_suspend_noirq()
3062 struct lpuart_port *sport = dev_get_drvdata(dev); in lpuart_resume_noirq() local
3067 if (lpuart_uport_is_active(sport)) { in lpuart_resume_noirq()
3068 serial_lpuart_enable_wakeup(sport, false); in lpuart_resume_noirq()
3071 if (lpuart_is_32(sport)) { in lpuart_resume_noirq()
3072 val = lpuart32_read(&sport->port, UARTSTAT); in lpuart_resume_noirq()
3073 lpuart32_write(&sport->port, val, UARTSTAT); in lpuart_resume_noirq()
3082 struct lpuart_port *sport = dev_get_drvdata(dev); in lpuart_suspend() local
3085 uart_suspend_port(&lpuart_reg, &sport->port); in lpuart_suspend()
3087 if (lpuart_uport_is_active(sport)) { in lpuart_suspend()
3088 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_suspend()
3089 if (lpuart_is_32(sport)) { in lpuart_suspend()
3091 temp = lpuart32_read(&sport->port, UARTCTRL); in lpuart_suspend()
3093 lpuart32_write(&sport->port, temp, UARTCTRL); in lpuart_suspend()
3096 temp = readb(sport->port.membase + UARTCR2); in lpuart_suspend()
3098 writeb(temp, sport->port.membase + UARTCR2); in lpuart_suspend()
3100 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_suspend()
3102 if (sport->lpuart_dma_rx_use) { in lpuart_suspend()
3110 lpuart_dma_rx_free(&sport->port); in lpuart_suspend()
3113 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_suspend()
3114 if (lpuart_is_32(sport)) { in lpuart_suspend()
3115 temp = lpuart32_read(&sport->port, UARTBAUD); in lpuart_suspend()
3116 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE, in lpuart_suspend()
3119 writeb(readb(sport->port.membase + UARTCR5) & in lpuart_suspend()
3120 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5); in lpuart_suspend()
3122 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_suspend()
3125 if (sport->lpuart_dma_tx_use) { in lpuart_suspend()
3126 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_suspend()
3127 if (lpuart_is_32(sport)) { in lpuart_suspend()
3128 temp = lpuart32_read(&sport->port, UARTBAUD); in lpuart_suspend()
3130 lpuart32_write(&sport->port, temp, UARTBAUD); in lpuart_suspend()
3132 temp = readb(sport->port.membase + UARTCR5); in lpuart_suspend()
3134 writeb(temp, sport->port.membase + UARTCR5); in lpuart_suspend()
3136 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_suspend()
3137 sport->dma_tx_in_progress = false; in lpuart_suspend()
3138 dmaengine_terminate_sync(sport->dma_tx_chan); in lpuart_suspend()
3140 } else if (pm_runtime_active(sport->port.dev)) { in lpuart_suspend()
3141 lpuart_disable_clks(sport); in lpuart_suspend()
3142 pm_runtime_disable(sport->port.dev); in lpuart_suspend()
3143 pm_runtime_set_suspended(sport->port.dev); in lpuart_suspend()
3149 static void lpuart_console_fixup(struct lpuart_port *sport) in lpuart_console_fixup() argument
3151 struct tty_port *port = &sport->port.state->port; in lpuart_console_fixup()
3152 struct uart_port *uport = &sport->port; in lpuart_console_fixup()
3162 if (is_imx7ulp_lpuart(sport) && lpuart_uport_is_active(sport) && in lpuart_console_fixup()
3163 console_suspend_enabled && uart_console(&sport->port)) { in lpuart_console_fixup()
3177 struct lpuart_port *sport = dev_get_drvdata(dev); in lpuart_resume() local
3180 if (lpuart_uport_is_active(sport)) { in lpuart_resume()
3181 if (lpuart_is_32(sport)) in lpuart_resume()
3182 lpuart32_hw_setup(sport); in lpuart_resume()
3184 lpuart_hw_setup(sport); in lpuart_resume()
3185 } else if (pm_runtime_active(sport->port.dev)) { in lpuart_resume()
3186 ret = lpuart_enable_clks(sport); in lpuart_resume()
3189 pm_runtime_set_active(sport->port.dev); in lpuart_resume()
3190 pm_runtime_enable(sport->port.dev); in lpuart_resume()
3193 lpuart_console_fixup(sport); in lpuart_resume()
3194 uart_resume_port(&lpuart_reg, &sport->port); in lpuart_resume()