Lines Matching refs:uap
279 static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap, in pl011_reg_to_offset() argument
282 return uap->reg_offset[reg]; in pl011_reg_to_offset()
285 static unsigned int pl011_read(const struct uart_amba_port *uap, in pl011_read() argument
288 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); in pl011_read()
290 return (uap->port.iotype == UPIO_MEM32) ? in pl011_read()
294 static void pl011_write(unsigned int val, const struct uart_amba_port *uap, in pl011_write() argument
297 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); in pl011_write()
299 if (uap->port.iotype == UPIO_MEM32) in pl011_write()
310 static int pl011_fifo_to_tty(struct uart_amba_port *uap) in pl011_fifo_to_tty() argument
318 status = pl011_read(uap, REG_FR); in pl011_fifo_to_tty()
323 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX; in pl011_fifo_to_tty()
325 uap->port.icount.rx++; in pl011_fifo_to_tty()
330 uap->port.icount.brk++; in pl011_fifo_to_tty()
331 if (uart_handle_break(&uap->port)) in pl011_fifo_to_tty()
334 uap->port.icount.parity++; in pl011_fifo_to_tty()
336 uap->port.icount.frame++; in pl011_fifo_to_tty()
339 uap->port.icount.overrun++; in pl011_fifo_to_tty()
341 ch &= uap->port.read_status_mask; in pl011_fifo_to_tty()
351 sysrq = uart_prepare_sysrq_char(&uap->port, ch & 255); in pl011_fifo_to_tty()
353 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); in pl011_fifo_to_tty()
389 static void pl011_dma_probe(struct uart_amba_port *uap) in pl011_dma_probe() argument
392 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev); in pl011_dma_probe()
393 struct device *dev = uap->port.dev; in pl011_dma_probe()
395 .dst_addr = uap->port.mapbase + in pl011_dma_probe()
396 pl011_reg_to_offset(uap, REG_DR), in pl011_dma_probe()
399 .dst_maxburst = uap->fifosize >> 1, in pl011_dma_probe()
405 uap->dma_probed = true; in pl011_dma_probe()
409 uap->dma_probed = false; in pl011_dma_probe()
415 dev_dbg(uap->port.dev, "no DMA platform data\n"); in pl011_dma_probe()
426 dev_err(uap->port.dev, "no TX DMA channel!\n"); in pl011_dma_probe()
432 uap->dmatx.chan = chan; in pl011_dma_probe()
434 dev_info(uap->port.dev, "DMA channel TX %s\n", in pl011_dma_probe()
435 dma_chan_name(uap->dmatx.chan)); in pl011_dma_probe()
444 dev_err(uap->port.dev, "no RX DMA channel!\n"); in pl011_dma_probe()
451 .src_addr = uap->port.mapbase + in pl011_dma_probe()
452 pl011_reg_to_offset(uap, REG_DR), in pl011_dma_probe()
455 .src_maxburst = uap->fifosize >> 2, in pl011_dma_probe()
469 dev_info(uap->port.dev, in pl011_dma_probe()
475 uap->dmarx.chan = chan; in pl011_dma_probe()
477 uap->dmarx.auto_poll_rate = false; in pl011_dma_probe()
481 uap->dmarx.auto_poll_rate = false; in pl011_dma_probe()
482 uap->dmarx.poll_rate = plat->dma_rx_poll_rate; in pl011_dma_probe()
489 uap->dmarx.auto_poll_rate = true; in pl011_dma_probe()
490 uap->dmarx.poll_rate = 100; in pl011_dma_probe()
494 uap->dmarx.poll_timeout = in pl011_dma_probe()
497 uap->dmarx.poll_timeout = 3000; in pl011_dma_probe()
499 uap->dmarx.auto_poll_rate = in pl011_dma_probe()
501 if (uap->dmarx.auto_poll_rate) { in pl011_dma_probe()
505 uap->dmarx.poll_rate = x; in pl011_dma_probe()
507 uap->dmarx.poll_rate = 100; in pl011_dma_probe()
509 uap->dmarx.poll_timeout = x; in pl011_dma_probe()
511 uap->dmarx.poll_timeout = 3000; in pl011_dma_probe()
514 dev_info(uap->port.dev, "DMA channel RX %s\n", in pl011_dma_probe()
515 dma_chan_name(uap->dmarx.chan)); in pl011_dma_probe()
519 static void pl011_dma_remove(struct uart_amba_port *uap) in pl011_dma_remove() argument
521 if (uap->dmatx.chan) in pl011_dma_remove()
522 dma_release_channel(uap->dmatx.chan); in pl011_dma_remove()
523 if (uap->dmarx.chan) in pl011_dma_remove()
524 dma_release_channel(uap->dmarx.chan); in pl011_dma_remove()
528 static int pl011_dma_tx_refill(struct uart_amba_port *uap);
529 static void pl011_start_tx_pio(struct uart_amba_port *uap);
537 struct uart_amba_port *uap = data; in pl011_dma_tx_callback() local
538 struct tty_port *tport = &uap->port.state->port; in pl011_dma_tx_callback()
539 struct pl011_dmatx_data *dmatx = &uap->dmatx; in pl011_dma_tx_callback()
543 uart_port_lock_irqsave(&uap->port, &flags); in pl011_dma_tx_callback()
544 if (uap->dmatx.queued) in pl011_dma_tx_callback()
548 dmacr = uap->dmacr; in pl011_dma_tx_callback()
549 uap->dmacr = dmacr & ~UART011_TXDMAE; in pl011_dma_tx_callback()
550 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_callback()
561 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || in pl011_dma_tx_callback()
563 uap->dmatx.queued = false; in pl011_dma_tx_callback()
564 uart_port_unlock_irqrestore(&uap->port, flags); in pl011_dma_tx_callback()
568 if (pl011_dma_tx_refill(uap) <= 0) in pl011_dma_tx_callback()
573 pl011_start_tx_pio(uap); in pl011_dma_tx_callback()
575 uart_port_unlock_irqrestore(&uap->port, flags); in pl011_dma_tx_callback()
586 static int pl011_dma_tx_refill(struct uart_amba_port *uap) in pl011_dma_tx_refill() argument
588 struct pl011_dmatx_data *dmatx = &uap->dmatx; in pl011_dma_tx_refill()
592 struct tty_port *tport = &uap->port.state->port; in pl011_dma_tx_refill()
602 if (count < (uap->fifosize >> 1)) { in pl011_dma_tx_refill()
603 uap->dmatx.queued = false; in pl011_dma_tx_refill()
622 uap->dmatx.queued = false; in pl011_dma_tx_refill()
623 dev_dbg(uap->port.dev, "unable to map TX DMA\n"); in pl011_dma_tx_refill()
631 uap->dmatx.queued = false; in pl011_dma_tx_refill()
636 dev_dbg(uap->port.dev, "TX DMA busy\n"); in pl011_dma_tx_refill()
642 desc->callback_param = uap; in pl011_dma_tx_refill()
650 uap->dmacr |= UART011_TXDMAE; in pl011_dma_tx_refill()
651 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_refill()
652 uap->dmatx.queued = true; in pl011_dma_tx_refill()
658 uart_xmit_advance(&uap->port, count); in pl011_dma_tx_refill()
661 uart_write_wakeup(&uap->port); in pl011_dma_tx_refill()
674 static bool pl011_dma_tx_irq(struct uart_amba_port *uap) in pl011_dma_tx_irq() argument
676 if (!uap->using_tx_dma) in pl011_dma_tx_irq()
684 if (uap->dmatx.queued) { in pl011_dma_tx_irq()
685 uap->dmacr |= UART011_TXDMAE; in pl011_dma_tx_irq()
686 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_irq()
687 uap->im &= ~UART011_TXIM; in pl011_dma_tx_irq()
688 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_tx_irq()
696 if (pl011_dma_tx_refill(uap) > 0) { in pl011_dma_tx_irq()
697 uap->im &= ~UART011_TXIM; in pl011_dma_tx_irq()
698 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_tx_irq()
708 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) in pl011_dma_tx_stop() argument
710 if (uap->dmatx.queued) { in pl011_dma_tx_stop()
711 uap->dmacr &= ~UART011_TXDMAE; in pl011_dma_tx_stop()
712 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_stop()
724 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) in pl011_dma_tx_start() argument
728 if (!uap->using_tx_dma) in pl011_dma_tx_start()
731 if (!uap->port.x_char) { in pl011_dma_tx_start()
735 if (!uap->dmatx.queued) { in pl011_dma_tx_start()
736 if (pl011_dma_tx_refill(uap) > 0) { in pl011_dma_tx_start()
737 uap->im &= ~UART011_TXIM; in pl011_dma_tx_start()
738 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_tx_start()
742 } else if (!(uap->dmacr & UART011_TXDMAE)) { in pl011_dma_tx_start()
743 uap->dmacr |= UART011_TXDMAE; in pl011_dma_tx_start()
744 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_start()
753 dmacr = uap->dmacr; in pl011_dma_tx_start()
754 uap->dmacr &= ~UART011_TXDMAE; in pl011_dma_tx_start()
755 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_start()
757 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) { in pl011_dma_tx_start()
766 pl011_write(uap->port.x_char, uap, REG_DR); in pl011_dma_tx_start()
767 uap->port.icount.tx++; in pl011_dma_tx_start()
768 uap->port.x_char = 0; in pl011_dma_tx_start()
771 uap->dmacr = dmacr; in pl011_dma_tx_start()
772 pl011_write(dmacr, uap, REG_DMACR); in pl011_dma_tx_start()
782 __releases(&uap->port.lock) in pl011_dma_flush_buffer()
783 __acquires(&uap->port.lock) in pl011_dma_flush_buffer()
785 struct uart_amba_port *uap = in pl011_dma_flush_buffer() local
788 if (!uap->using_tx_dma) in pl011_dma_flush_buffer()
791 dmaengine_terminate_async(uap->dmatx.chan); in pl011_dma_flush_buffer()
793 if (uap->dmatx.queued) { in pl011_dma_flush_buffer()
794 dma_unmap_single(uap->dmatx.chan->device->dev, uap->dmatx.dma, in pl011_dma_flush_buffer()
795 uap->dmatx.len, DMA_TO_DEVICE); in pl011_dma_flush_buffer()
796 uap->dmatx.queued = false; in pl011_dma_flush_buffer()
797 uap->dmacr &= ~UART011_TXDMAE; in pl011_dma_flush_buffer()
798 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_flush_buffer()
804 static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) in pl011_dma_rx_trigger_dma() argument
806 struct dma_chan *rxchan = uap->dmarx.chan; in pl011_dma_rx_trigger_dma()
807 struct pl011_dmarx_data *dmarx = &uap->dmarx; in pl011_dma_rx_trigger_dma()
815 dbuf = uap->dmarx.use_buf_b ? in pl011_dma_rx_trigger_dma()
816 &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a; in pl011_dma_rx_trigger_dma()
826 uap->dmarx.running = false; in pl011_dma_rx_trigger_dma()
833 desc->callback_param = uap; in pl011_dma_rx_trigger_dma()
837 uap->dmacr |= UART011_RXDMAE; in pl011_dma_rx_trigger_dma()
838 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_rx_trigger_dma()
839 uap->dmarx.running = true; in pl011_dma_rx_trigger_dma()
841 uap->im &= ~UART011_RXIM; in pl011_dma_rx_trigger_dma()
842 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_rx_trigger_dma()
852 static void pl011_dma_rx_chars(struct uart_amba_port *uap, in pl011_dma_rx_chars() argument
856 struct tty_port *port = &uap->port.state->port; in pl011_dma_rx_chars()
858 &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a; in pl011_dma_rx_chars()
862 struct pl011_dmarx_data *dmarx = &uap->dmarx; in pl011_dma_rx_chars()
865 if (uap->dmarx.poll_rate) { in pl011_dma_rx_chars()
882 uap->port.icount.rx += dma_count; in pl011_dma_rx_chars()
884 dev_warn(uap->port.dev, in pl011_dma_rx_chars()
889 if (uap->dmarx.poll_rate) in pl011_dma_rx_chars()
899 UART011_FEIS, uap, REG_ICR); in pl011_dma_rx_chars()
912 fifotaken = pl011_fifo_to_tty(uap); in pl011_dma_rx_chars()
915 dev_vdbg(uap->port.dev, in pl011_dma_rx_chars()
921 static void pl011_dma_rx_irq(struct uart_amba_port *uap) in pl011_dma_rx_irq() argument
923 struct pl011_dmarx_data *dmarx = &uap->dmarx; in pl011_dma_rx_irq()
937 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); in pl011_dma_rx_irq()
941 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); in pl011_dma_rx_irq()
944 uap->dmacr &= ~UART011_RXDMAE; in pl011_dma_rx_irq()
945 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_rx_irq()
946 uap->dmarx.running = false; in pl011_dma_rx_irq()
957 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true); in pl011_dma_rx_irq()
961 if (pl011_dma_rx_trigger_dma(uap)) { in pl011_dma_rx_irq()
962 dev_dbg(uap->port.dev, in pl011_dma_rx_irq()
964 uap->im |= UART011_RXIM; in pl011_dma_rx_irq()
965 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_rx_irq()
971 struct uart_amba_port *uap = data; in pl011_dma_rx_callback() local
972 struct pl011_dmarx_data *dmarx = &uap->dmarx; in pl011_dma_rx_callback()
988 uart_port_lock_irq(&uap->port); in pl011_dma_rx_callback()
999 uap->dmarx.running = false; in pl011_dma_rx_callback()
1001 ret = pl011_dma_rx_trigger_dma(uap); in pl011_dma_rx_callback()
1003 pl011_dma_rx_chars(uap, pending, lastbuf, false); in pl011_dma_rx_callback()
1004 uart_unlock_and_check_sysrq(&uap->port); in pl011_dma_rx_callback()
1010 dev_dbg(uap->port.dev, in pl011_dma_rx_callback()
1012 uap->im |= UART011_RXIM; in pl011_dma_rx_callback()
1013 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_rx_callback()
1022 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) in pl011_dma_rx_stop() argument
1024 if (!uap->using_rx_dma) in pl011_dma_rx_stop()
1028 uap->dmacr &= ~UART011_RXDMAE; in pl011_dma_rx_stop()
1029 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_rx_stop()
1039 struct uart_amba_port *uap = from_timer(uap, t, dmarx.timer); in pl011_dma_rx_poll() local
1040 struct tty_port *port = &uap->port.state->port; in pl011_dma_rx_poll()
1041 struct pl011_dmarx_data *dmarx = &uap->dmarx; in pl011_dma_rx_poll()
1042 struct dma_chan *rxchan = uap->dmarx.chan; in pl011_dma_rx_poll()
1050 dbuf = dmarx->use_buf_b ? &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a; in pl011_dma_rx_poll()
1068 > uap->dmarx.poll_timeout) { in pl011_dma_rx_poll()
1069 uart_port_lock_irqsave(&uap->port, &flags); in pl011_dma_rx_poll()
1070 pl011_dma_rx_stop(uap); in pl011_dma_rx_poll()
1071 uap->im |= UART011_RXIM; in pl011_dma_rx_poll()
1072 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_rx_poll()
1073 uart_port_unlock_irqrestore(&uap->port, flags); in pl011_dma_rx_poll()
1075 uap->dmarx.running = false; in pl011_dma_rx_poll()
1077 del_timer(&uap->dmarx.timer); in pl011_dma_rx_poll()
1079 mod_timer(&uap->dmarx.timer, in pl011_dma_rx_poll()
1080 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); in pl011_dma_rx_poll()
1084 static void pl011_dma_startup(struct uart_amba_port *uap) in pl011_dma_startup() argument
1088 if (!uap->dma_probed) in pl011_dma_startup()
1089 pl011_dma_probe(uap); in pl011_dma_startup()
1091 if (!uap->dmatx.chan) in pl011_dma_startup()
1094 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA); in pl011_dma_startup()
1095 if (!uap->dmatx.buf) { in pl011_dma_startup()
1096 uap->port.fifosize = uap->fifosize; in pl011_dma_startup()
1100 uap->dmatx.len = PL011_DMA_BUFFER_SIZE; in pl011_dma_startup()
1103 uap->port.fifosize = PL011_DMA_BUFFER_SIZE; in pl011_dma_startup()
1104 uap->using_tx_dma = true; in pl011_dma_startup()
1106 if (!uap->dmarx.chan) in pl011_dma_startup()
1110 ret = pl011_dmabuf_init(uap->dmarx.chan, &uap->dmarx.dbuf_a, in pl011_dma_startup()
1113 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", in pl011_dma_startup()
1118 ret = pl011_dmabuf_init(uap->dmarx.chan, &uap->dmarx.dbuf_b, in pl011_dma_startup()
1121 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", in pl011_dma_startup()
1123 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_a, in pl011_dma_startup()
1128 uap->using_rx_dma = true; in pl011_dma_startup()
1132 uap->dmacr |= UART011_DMAONERR; in pl011_dma_startup()
1133 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_startup()
1140 if (uap->vendor->dma_threshold) in pl011_dma_startup()
1142 uap, REG_ST_DMAWM); in pl011_dma_startup()
1144 if (uap->using_rx_dma) { in pl011_dma_startup()
1145 if (pl011_dma_rx_trigger_dma(uap)) in pl011_dma_startup()
1146 dev_dbg(uap->port.dev, in pl011_dma_startup()
1148 if (uap->dmarx.poll_rate) { in pl011_dma_startup()
1149 timer_setup(&uap->dmarx.timer, pl011_dma_rx_poll, 0); in pl011_dma_startup()
1150 mod_timer(&uap->dmarx.timer, in pl011_dma_startup()
1151 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); in pl011_dma_startup()
1152 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; in pl011_dma_startup()
1153 uap->dmarx.last_jiffies = jiffies; in pl011_dma_startup()
1158 static void pl011_dma_shutdown(struct uart_amba_port *uap) in pl011_dma_shutdown() argument
1160 if (!(uap->using_tx_dma || uap->using_rx_dma)) in pl011_dma_shutdown()
1164 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy) in pl011_dma_shutdown()
1167 uart_port_lock_irq(&uap->port); in pl011_dma_shutdown()
1168 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE); in pl011_dma_shutdown()
1169 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_shutdown()
1170 uart_port_unlock_irq(&uap->port); in pl011_dma_shutdown()
1172 if (uap->using_tx_dma) { in pl011_dma_shutdown()
1174 dmaengine_terminate_all(uap->dmatx.chan); in pl011_dma_shutdown()
1175 if (uap->dmatx.queued) { in pl011_dma_shutdown()
1176 dma_unmap_single(uap->dmatx.chan->device->dev, in pl011_dma_shutdown()
1177 uap->dmatx.dma, uap->dmatx.len, in pl011_dma_shutdown()
1179 uap->dmatx.queued = false; in pl011_dma_shutdown()
1182 kfree(uap->dmatx.buf); in pl011_dma_shutdown()
1183 uap->using_tx_dma = false; in pl011_dma_shutdown()
1186 if (uap->using_rx_dma) { in pl011_dma_shutdown()
1187 dmaengine_terminate_all(uap->dmarx.chan); in pl011_dma_shutdown()
1189 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_a, DMA_FROM_DEVICE); in pl011_dma_shutdown()
1190 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_b, DMA_FROM_DEVICE); in pl011_dma_shutdown()
1191 if (uap->dmarx.poll_rate) in pl011_dma_shutdown()
1192 del_timer_sync(&uap->dmarx.timer); in pl011_dma_shutdown()
1193 uap->using_rx_dma = false; in pl011_dma_shutdown()
1197 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) in pl011_dma_rx_available() argument
1199 return uap->using_rx_dma; in pl011_dma_rx_available()
1202 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) in pl011_dma_rx_running() argument
1204 return uap->using_rx_dma && uap->dmarx.running; in pl011_dma_rx_running()
1209 static inline void pl011_dma_remove(struct uart_amba_port *uap) in pl011_dma_remove() argument
1213 static inline void pl011_dma_startup(struct uart_amba_port *uap) in pl011_dma_startup() argument
1217 static inline void pl011_dma_shutdown(struct uart_amba_port *uap) in pl011_dma_shutdown() argument
1221 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap) in pl011_dma_tx_irq() argument
1226 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) in pl011_dma_tx_stop() argument
1230 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) in pl011_dma_tx_start() argument
1235 static inline void pl011_dma_rx_irq(struct uart_amba_port *uap) in pl011_dma_rx_irq() argument
1239 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) in pl011_dma_rx_stop() argument
1243 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) in pl011_dma_rx_trigger_dma() argument
1248 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) in pl011_dma_rx_available() argument
1253 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) in pl011_dma_rx_running() argument
1261 static void pl011_rs485_tx_stop(struct uart_amba_port *uap) in pl011_rs485_tx_stop() argument
1267 const int MAX_TX_DRAIN_ITERS = uap->port.fifosize * 2; in pl011_rs485_tx_stop()
1268 struct uart_port *port = &uap->port; in pl011_rs485_tx_stop()
1280 udelay(uap->rs485_tx_drain_interval); in pl011_rs485_tx_stop()
1287 cr = pl011_read(uap, REG_CR); in pl011_rs485_tx_stop()
1297 pl011_write(cr, uap, REG_CR); in pl011_rs485_tx_stop()
1299 uap->rs485_tx_started = false; in pl011_rs485_tx_stop()
1304 struct uart_amba_port *uap = in pl011_stop_tx() local
1307 uap->im &= ~UART011_TXIM; in pl011_stop_tx()
1308 pl011_write(uap->im, uap, REG_IMSC); in pl011_stop_tx()
1309 pl011_dma_tx_stop(uap); in pl011_stop_tx()
1311 if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started) in pl011_stop_tx()
1312 pl011_rs485_tx_stop(uap); in pl011_stop_tx()
1315 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq);
1318 static void pl011_start_tx_pio(struct uart_amba_port *uap) in pl011_start_tx_pio() argument
1320 if (pl011_tx_chars(uap, false)) { in pl011_start_tx_pio()
1321 uap->im |= UART011_TXIM; in pl011_start_tx_pio()
1322 pl011_write(uap->im, uap, REG_IMSC); in pl011_start_tx_pio()
1326 static void pl011_rs485_tx_start(struct uart_amba_port *uap) in pl011_rs485_tx_start() argument
1328 struct uart_port *port = &uap->port; in pl011_rs485_tx_start()
1332 cr = pl011_read(uap, REG_CR); in pl011_rs485_tx_start()
1344 pl011_write(cr, uap, REG_CR); in pl011_rs485_tx_start()
1349 uap->rs485_tx_started = true; in pl011_rs485_tx_start()
1354 struct uart_amba_port *uap = in pl011_start_tx() local
1357 if ((uap->port.rs485.flags & SER_RS485_ENABLED) && in pl011_start_tx()
1358 !uap->rs485_tx_started) in pl011_start_tx()
1359 pl011_rs485_tx_start(uap); in pl011_start_tx()
1361 if (!pl011_dma_tx_start(uap)) in pl011_start_tx()
1362 pl011_start_tx_pio(uap); in pl011_start_tx()
1367 struct uart_amba_port *uap = in pl011_stop_rx() local
1370 uap->im &= ~(UART011_RXIM | UART011_RTIM | UART011_FEIM | in pl011_stop_rx()
1372 pl011_write(uap->im, uap, REG_IMSC); in pl011_stop_rx()
1374 pl011_dma_rx_stop(uap); in pl011_stop_rx()
1388 struct uart_amba_port *uap = in pl011_enable_ms() local
1391 uap->im |= UART011_RIMIM | UART011_CTSMIM | UART011_DCDMIM | UART011_DSRMIM; in pl011_enable_ms()
1392 pl011_write(uap->im, uap, REG_IMSC); in pl011_enable_ms()
1395 static void pl011_rx_chars(struct uart_amba_port *uap) in pl011_rx_chars() argument
1396 __releases(&uap->port.lock) in pl011_rx_chars()
1397 __acquires(&uap->port.lock) in pl011_rx_chars()
1399 pl011_fifo_to_tty(uap); in pl011_rx_chars()
1401 uart_port_unlock(&uap->port); in pl011_rx_chars()
1402 tty_flip_buffer_push(&uap->port.state->port); in pl011_rx_chars()
1407 if (pl011_dma_rx_available(uap)) { in pl011_rx_chars()
1408 if (pl011_dma_rx_trigger_dma(uap)) { in pl011_rx_chars()
1409 dev_dbg(uap->port.dev, in pl011_rx_chars()
1411 uap->im |= UART011_RXIM; in pl011_rx_chars()
1412 pl011_write(uap->im, uap, REG_IMSC); in pl011_rx_chars()
1416 if (uap->dmarx.poll_rate) { in pl011_rx_chars()
1417 uap->dmarx.last_jiffies = jiffies; in pl011_rx_chars()
1418 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; in pl011_rx_chars()
1419 mod_timer(&uap->dmarx.timer, in pl011_rx_chars()
1420 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); in pl011_rx_chars()
1425 uart_port_lock(&uap->port); in pl011_rx_chars()
1428 static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c, in pl011_tx_char() argument
1432 pl011_read(uap, REG_FR) & UART01x_FR_TXFF) in pl011_tx_char()
1435 pl011_write(c, uap, REG_DR); in pl011_tx_char()
1436 uap->port.icount.tx++; in pl011_tx_char()
1442 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq) in pl011_tx_chars() argument
1444 struct tty_port *tport = &uap->port.state->port; in pl011_tx_chars()
1445 int count = uap->fifosize >> 1; in pl011_tx_chars()
1447 if (uap->port.x_char) { in pl011_tx_chars()
1448 if (!pl011_tx_char(uap, uap->port.x_char, from_irq)) in pl011_tx_chars()
1450 uap->port.x_char = 0; in pl011_tx_chars()
1453 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(&uap->port)) { in pl011_tx_chars()
1454 pl011_stop_tx(&uap->port); in pl011_tx_chars()
1459 if (pl011_dma_tx_irq(uap)) in pl011_tx_chars()
1471 if (!pl011_tx_char(uap, c, from_irq)) in pl011_tx_chars()
1478 uart_write_wakeup(&uap->port); in pl011_tx_chars()
1481 pl011_stop_tx(&uap->port); in pl011_tx_chars()
1487 static void pl011_modem_status(struct uart_amba_port *uap) in pl011_modem_status() argument
1491 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; in pl011_modem_status()
1493 delta = status ^ uap->old_status; in pl011_modem_status()
1494 uap->old_status = status; in pl011_modem_status()
1500 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); in pl011_modem_status()
1502 if (delta & uap->vendor->fr_dsr) in pl011_modem_status()
1503 uap->port.icount.dsr++; in pl011_modem_status()
1505 if (delta & uap->vendor->fr_cts) in pl011_modem_status()
1506 uart_handle_cts_change(&uap->port, in pl011_modem_status()
1507 status & uap->vendor->fr_cts); in pl011_modem_status()
1509 wake_up_interruptible(&uap->port.state->port.delta_msr_wait); in pl011_modem_status()
1512 static void check_apply_cts_event_workaround(struct uart_amba_port *uap) in check_apply_cts_event_workaround() argument
1514 if (!uap->vendor->cts_event_workaround) in check_apply_cts_event_workaround()
1518 pl011_write(0x00, uap, REG_ICR); in check_apply_cts_event_workaround()
1525 pl011_read(uap, REG_ICR); in check_apply_cts_event_workaround()
1526 pl011_read(uap, REG_ICR); in check_apply_cts_event_workaround()
1531 struct uart_amba_port *uap = dev_id; in pl011_int() local
1535 uart_port_lock(&uap->port); in pl011_int()
1536 status = pl011_read(uap, REG_RIS) & uap->im; in pl011_int()
1539 check_apply_cts_event_workaround(uap); in pl011_int()
1542 uap, REG_ICR); in pl011_int()
1545 if (pl011_dma_rx_running(uap)) in pl011_int()
1546 pl011_dma_rx_irq(uap); in pl011_int()
1548 pl011_rx_chars(uap); in pl011_int()
1552 pl011_modem_status(uap); in pl011_int()
1554 pl011_tx_chars(uap, true); in pl011_int()
1559 status = pl011_read(uap, REG_RIS) & uap->im; in pl011_int()
1564 uart_unlock_and_check_sysrq(&uap->port); in pl011_int()
1571 struct uart_amba_port *uap = in pl011_tx_empty() local
1575 unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr; in pl011_tx_empty()
1577 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ? in pl011_tx_empty()
1589 struct uart_amba_port *uap = in pl011_get_mctrl() local
1592 unsigned int status = pl011_read(uap, REG_FR); in pl011_get_mctrl()
1595 pl011_maybe_set_bit(status & uap->vendor->fr_dsr, &result, TIOCM_DSR); in pl011_get_mctrl()
1596 pl011_maybe_set_bit(status & uap->vendor->fr_cts, &result, TIOCM_CTS); in pl011_get_mctrl()
1597 pl011_maybe_set_bit(status & uap->vendor->fr_ri, &result, TIOCM_RNG); in pl011_get_mctrl()
1612 struct uart_amba_port *uap = in pl011_set_mctrl() local
1616 cr = pl011_read(uap, REG_CR); in pl011_set_mctrl()
1629 pl011_write(cr, uap, REG_CR); in pl011_set_mctrl()
1634 struct uart_amba_port *uap = in pl011_break_ctl() local
1639 uart_port_lock_irqsave(&uap->port, &flags); in pl011_break_ctl()
1640 lcr_h = pl011_read(uap, REG_LCRH_TX); in pl011_break_ctl()
1645 pl011_write(lcr_h, uap, REG_LCRH_TX); in pl011_break_ctl()
1646 uart_port_unlock_irqrestore(&uap->port, flags); in pl011_break_ctl()
1653 struct uart_amba_port *uap = in pl011_quiesce_irqs() local
1656 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR); in pl011_quiesce_irqs()
1670 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap, in pl011_quiesce_irqs()
1676 struct uart_amba_port *uap = in pl011_get_poll_char() local
1686 status = pl011_read(uap, REG_FR); in pl011_get_poll_char()
1690 return pl011_read(uap, REG_DR); in pl011_get_poll_char()
1695 struct uart_amba_port *uap = in pl011_put_poll_char() local
1698 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) in pl011_put_poll_char()
1701 pl011_write(ch, uap, REG_DR); in pl011_put_poll_char()
1708 struct uart_amba_port *uap = in pl011_hwinit() local
1718 retval = clk_prepare_enable(uap->clk); in pl011_hwinit()
1722 uap->port.uartclk = clk_get_rate(uap->clk); in pl011_hwinit()
1727 uap, REG_ICR); in pl011_hwinit()
1733 uap->im = pl011_read(uap, REG_IMSC); in pl011_hwinit()
1734 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC); in pl011_hwinit()
1736 if (dev_get_platdata(uap->port.dev)) { in pl011_hwinit()
1739 plat = dev_get_platdata(uap->port.dev); in pl011_hwinit()
1746 static bool pl011_split_lcrh(const struct uart_amba_port *uap) in pl011_split_lcrh() argument
1748 return pl011_reg_to_offset(uap, REG_LCRH_RX) != in pl011_split_lcrh()
1749 pl011_reg_to_offset(uap, REG_LCRH_TX); in pl011_split_lcrh()
1752 static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h) in pl011_write_lcr_h() argument
1754 pl011_write(lcr_h, uap, REG_LCRH_RX); in pl011_write_lcr_h()
1755 if (pl011_split_lcrh(uap)) { in pl011_write_lcr_h()
1762 pl011_write(0xff, uap, REG_MIS); in pl011_write_lcr_h()
1763 pl011_write(lcr_h, uap, REG_LCRH_TX); in pl011_write_lcr_h()
1767 static int pl011_allocate_irq(struct uart_amba_port *uap) in pl011_allocate_irq() argument
1769 pl011_write(uap->im, uap, REG_IMSC); in pl011_allocate_irq()
1771 return request_irq(uap->port.irq, pl011_int, IRQF_SHARED, "uart-pl011", uap); in pl011_allocate_irq()
1779 static void pl011_enable_interrupts(struct uart_amba_port *uap) in pl011_enable_interrupts() argument
1784 uart_port_lock_irqsave(&uap->port, &flags); in pl011_enable_interrupts()
1787 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR); in pl011_enable_interrupts()
1795 for (i = 0; i < uap->fifosize * 2; ++i) { in pl011_enable_interrupts()
1796 if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE) in pl011_enable_interrupts()
1799 pl011_read(uap, REG_DR); in pl011_enable_interrupts()
1802 uap->im = UART011_RTIM; in pl011_enable_interrupts()
1803 if (!pl011_dma_rx_running(uap)) in pl011_enable_interrupts()
1804 uap->im |= UART011_RXIM; in pl011_enable_interrupts()
1805 pl011_write(uap->im, uap, REG_IMSC); in pl011_enable_interrupts()
1806 uart_port_unlock_irqrestore(&uap->port, flags); in pl011_enable_interrupts()
1811 struct uart_amba_port *uap = container_of(port, struct uart_amba_port, port); in pl011_unthrottle_rx() local
1814 uart_port_lock_irqsave(&uap->port, &flags); in pl011_unthrottle_rx()
1816 uap->im = UART011_RTIM; in pl011_unthrottle_rx()
1817 if (!pl011_dma_rx_running(uap)) in pl011_unthrottle_rx()
1818 uap->im |= UART011_RXIM; in pl011_unthrottle_rx()
1820 pl011_write(uap->im, uap, REG_IMSC); in pl011_unthrottle_rx()
1822 uart_port_unlock_irqrestore(&uap->port, flags); in pl011_unthrottle_rx()
1827 struct uart_amba_port *uap = in pl011_startup() local
1836 retval = pl011_allocate_irq(uap); in pl011_startup()
1840 pl011_write(uap->vendor->ifls, uap, REG_IFLS); in pl011_startup()
1842 uart_port_lock_irq(&uap->port); in pl011_startup()
1844 cr = pl011_read(uap, REG_CR); in pl011_startup()
1851 pl011_write(cr, uap, REG_CR); in pl011_startup()
1853 uart_port_unlock_irq(&uap->port); in pl011_startup()
1858 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; in pl011_startup()
1861 pl011_dma_startup(uap); in pl011_startup()
1863 pl011_enable_interrupts(uap); in pl011_startup()
1868 clk_disable_unprepare(uap->clk); in pl011_startup()
1874 struct uart_amba_port *uap = in sbsa_uart_startup() local
1882 retval = pl011_allocate_irq(uap); in sbsa_uart_startup()
1887 uap->old_status = 0; in sbsa_uart_startup()
1889 pl011_enable_interrupts(uap); in sbsa_uart_startup()
1894 static void pl011_shutdown_channel(struct uart_amba_port *uap, unsigned int lcrh) in pl011_shutdown_channel() argument
1898 val = pl011_read(uap, lcrh); in pl011_shutdown_channel()
1900 pl011_write(val, uap, lcrh); in pl011_shutdown_channel()
1908 static void pl011_disable_uart(struct uart_amba_port *uap) in pl011_disable_uart() argument
1912 uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); in pl011_disable_uart()
1913 uart_port_lock_irq(&uap->port); in pl011_disable_uart()
1914 cr = pl011_read(uap, REG_CR); in pl011_disable_uart()
1917 pl011_write(cr, uap, REG_CR); in pl011_disable_uart()
1918 uart_port_unlock_irq(&uap->port); in pl011_disable_uart()
1923 pl011_shutdown_channel(uap, REG_LCRH_RX); in pl011_disable_uart()
1924 if (pl011_split_lcrh(uap)) in pl011_disable_uart()
1925 pl011_shutdown_channel(uap, REG_LCRH_TX); in pl011_disable_uart()
1928 static void pl011_disable_interrupts(struct uart_amba_port *uap) in pl011_disable_interrupts() argument
1930 uart_port_lock_irq(&uap->port); in pl011_disable_interrupts()
1933 uap->im = 0; in pl011_disable_interrupts()
1934 pl011_write(uap->im, uap, REG_IMSC); in pl011_disable_interrupts()
1935 pl011_write(0xffff, uap, REG_ICR); in pl011_disable_interrupts()
1937 uart_port_unlock_irq(&uap->port); in pl011_disable_interrupts()
1942 struct uart_amba_port *uap = in pl011_shutdown() local
1945 pl011_disable_interrupts(uap); in pl011_shutdown()
1947 pl011_dma_shutdown(uap); in pl011_shutdown()
1949 if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started) in pl011_shutdown()
1950 pl011_rs485_tx_stop(uap); in pl011_shutdown()
1952 free_irq(uap->port.irq, uap); in pl011_shutdown()
1954 pl011_disable_uart(uap); in pl011_shutdown()
1959 clk_disable_unprepare(uap->clk); in pl011_shutdown()
1963 if (dev_get_platdata(uap->port.dev)) { in pl011_shutdown()
1966 plat = dev_get_platdata(uap->port.dev); in pl011_shutdown()
1971 if (uap->port.ops->flush_buffer) in pl011_shutdown()
1972 uap->port.ops->flush_buffer(port); in pl011_shutdown()
1977 struct uart_amba_port *uap = in sbsa_uart_shutdown() local
1980 pl011_disable_interrupts(uap); in sbsa_uart_shutdown()
1982 free_irq(uap->port.irq, uap); in sbsa_uart_shutdown()
1984 if (uap->port.ops->flush_buffer) in sbsa_uart_shutdown()
1985 uap->port.ops->flush_buffer(port); in sbsa_uart_shutdown()
2024 struct uart_amba_port *uap = in pl011_set_termios() local
2031 if (uap->vendor->oversampling) in pl011_set_termios()
2045 if (uap->dmarx.auto_poll_rate) in pl011_set_termios()
2046 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud); in pl011_set_termios()
2077 if (uap->fifosize > 1) in pl011_set_termios()
2094 uap->rs485_tx_drain_interval = DIV_ROUND_UP(bits * 1000 * 1000, baud); in pl011_set_termios()
2104 old_cr = pl011_read(uap, REG_CR); in pl011_set_termios()
2117 if (uap->vendor->oversampling) { in pl011_set_termios()
2130 if (uap->vendor->oversampling) { in pl011_set_termios()
2137 pl011_write(quot & 0x3f, uap, REG_FBRD); in pl011_set_termios()
2138 pl011_write(quot >> 6, uap, REG_IBRD); in pl011_set_termios()
2146 pl011_write_lcr_h(uap, lcr_h); in pl011_set_termios()
2154 pl011_write(old_cr, uap, REG_CR); in pl011_set_termios()
2163 struct uart_amba_port *uap = in sbsa_uart_set_termios() local
2167 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud); in sbsa_uart_set_termios()
2175 uart_update_timeout(port, CS8, uap->fixed_baud); in sbsa_uart_set_termios()
2182 struct uart_amba_port *uap = in pl011_type() local
2184 return uap->port.type == PORT_AMBA ? uap->type : NULL; in pl011_type()
2217 struct uart_amba_port *uap = in pl011_rs485_config() local
2221 pl011_rs485_tx_stop(uap); in pl011_rs485_config()
2225 u32 cr = pl011_read(uap, REG_CR); in pl011_rs485_config()
2228 pl011_write(cr, uap, REG_CR); in pl011_rs485_config()
2295 struct uart_amba_port *uap = in pl011_console_putchar() local
2298 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) in pl011_console_putchar()
2300 pl011_write(ch, uap, REG_DR); in pl011_console_putchar()
2306 struct uart_amba_port *uap = amba_ports[co->index]; in pl011_console_write() local
2311 clk_enable(uap->clk); in pl011_console_write()
2314 locked = uart_port_trylock_irqsave(&uap->port, &flags); in pl011_console_write()
2316 uart_port_lock_irqsave(&uap->port, &flags); in pl011_console_write()
2321 if (!uap->vendor->always_enabled) { in pl011_console_write()
2322 old_cr = pl011_read(uap, REG_CR); in pl011_console_write()
2325 pl011_write(new_cr, uap, REG_CR); in pl011_console_write()
2328 uart_console_write(&uap->port, s, count, pl011_console_putchar); in pl011_console_write()
2335 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr) in pl011_console_write()
2336 & uap->vendor->fr_busy) in pl011_console_write()
2338 if (!uap->vendor->always_enabled) in pl011_console_write()
2339 pl011_write(old_cr, uap, REG_CR); in pl011_console_write()
2342 uart_port_unlock_irqrestore(&uap->port, flags); in pl011_console_write()
2344 clk_disable(uap->clk); in pl011_console_write()
2347 static void pl011_console_get_options(struct uart_amba_port *uap, int *baud, in pl011_console_get_options() argument
2352 if (!(pl011_read(uap, REG_CR) & UART01x_CR_UARTEN)) in pl011_console_get_options()
2355 lcr_h = pl011_read(uap, REG_LCRH_TX); in pl011_console_get_options()
2370 ibrd = pl011_read(uap, REG_IBRD); in pl011_console_get_options()
2371 fbrd = pl011_read(uap, REG_FBRD); in pl011_console_get_options()
2373 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); in pl011_console_get_options()
2375 if (uap->vendor->oversampling && in pl011_console_get_options()
2376 (pl011_read(uap, REG_CR) & ST_UART011_CR_OVSFACT)) in pl011_console_get_options()
2382 struct uart_amba_port *uap; in pl011_console_setup() local
2396 uap = amba_ports[co->index]; in pl011_console_setup()
2397 if (!uap) in pl011_console_setup()
2401 pinctrl_pm_select_default_state(uap->port.dev); in pl011_console_setup()
2403 ret = clk_prepare(uap->clk); in pl011_console_setup()
2407 if (dev_get_platdata(uap->port.dev)) { in pl011_console_setup()
2410 plat = dev_get_platdata(uap->port.dev); in pl011_console_setup()
2415 uap->port.uartclk = clk_get_rate(uap->clk); in pl011_console_setup()
2417 if (uap->vendor->fixed_options) { in pl011_console_setup()
2418 baud = uap->fixed_baud; in pl011_console_setup()
2424 pl011_console_get_options(uap, &baud, &parity, &bits); in pl011_console_setup()
2427 return uart_set_options(&uap->port, co, baud, parity, bits, flow); in pl011_console_setup()
2668 static void pl011_unregister_port(struct uart_amba_port *uap) in pl011_unregister_port() argument
2674 if (amba_ports[i] == uap) in pl011_unregister_port()
2679 pl011_dma_remove(uap); in pl011_unregister_port()
2695 static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap, in pl011_setup_port() argument
2707 uap->port.dev = dev; in pl011_setup_port()
2708 uap->port.mapbase = mmiobase->start; in pl011_setup_port()
2709 uap->port.membase = base; in pl011_setup_port()
2710 uap->port.fifosize = uap->fifosize; in pl011_setup_port()
2711 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_AMBA_PL011_CONSOLE); in pl011_setup_port()
2712 uap->port.flags = UPF_BOOT_AUTOCONF; in pl011_setup_port()
2713 uap->port.line = index; in pl011_setup_port()
2715 ret = uart_get_rs485_mode(&uap->port); in pl011_setup_port()
2719 amba_ports[index] = uap; in pl011_setup_port()
2724 static int pl011_register_port(struct uart_amba_port *uap) in pl011_register_port() argument
2729 pl011_write(0, uap, REG_IMSC); in pl011_register_port()
2730 pl011_write(0xffff, uap, REG_ICR); in pl011_register_port()
2735 dev_err(uap->port.dev, in pl011_register_port()
2738 if (amba_ports[i] == uap) in pl011_register_port()
2744 ret = uart_add_one_port(&amba_reg, &uap->port); in pl011_register_port()
2746 pl011_unregister_port(uap); in pl011_register_port()
2760 struct uart_amba_port *uap; in pl011_probe() local
2769 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port), in pl011_probe()
2771 if (!uap) in pl011_probe()
2774 uap->clk = devm_clk_get(&dev->dev, NULL); in pl011_probe()
2775 if (IS_ERR(uap->clk)) in pl011_probe()
2776 return PTR_ERR(uap->clk); in pl011_probe()
2778 uap->reg_offset = vendor->reg_offset; in pl011_probe()
2779 uap->vendor = vendor; in pl011_probe()
2780 uap->fifosize = vendor->get_fifosize(dev); in pl011_probe()
2781 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; in pl011_probe()
2782 uap->port.irq = dev->irq[0]; in pl011_probe()
2783 uap->port.ops = &amba_pl011_pops; in pl011_probe()
2784 uap->port.rs485_config = pl011_rs485_config; in pl011_probe()
2785 uap->port.rs485_supported = pl011_rs485_supported; in pl011_probe()
2786 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev)); in pl011_probe()
2791 uap->port.iotype = UPIO_MEM; in pl011_probe()
2794 uap->port.iotype = UPIO_MEM32; in pl011_probe()
2803 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr); in pl011_probe()
2807 amba_set_drvdata(dev, uap); in pl011_probe()
2809 return pl011_register_port(uap); in pl011_probe()
2814 struct uart_amba_port *uap = amba_get_drvdata(dev); in pl011_remove() local
2816 uart_remove_one_port(&amba_reg, &uap->port); in pl011_remove()
2817 pl011_unregister_port(uap); in pl011_remove()
2823 struct uart_amba_port *uap = dev_get_drvdata(dev); in pl011_suspend() local
2825 if (!uap) in pl011_suspend()
2828 return uart_suspend_port(&amba_reg, &uap->port); in pl011_suspend()
2833 struct uart_amba_port *uap = dev_get_drvdata(dev); in pl011_resume() local
2835 if (!uap) in pl011_resume()
2838 return uart_resume_port(&amba_reg, &uap->port); in pl011_resume()
2846 struct uart_amba_port *uap) in qpdf2400_erratum44_workaround() argument
2852 uap->vendor = &vendor_qdt_qdf2400_e44; in qpdf2400_erratum44_workaround()
2856 struct uart_amba_port *uap) in qpdf2400_erratum44_workaround() argument
2862 struct uart_amba_port *uap; in sbsa_uart_probe() local
2885 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port), in sbsa_uart_probe()
2887 if (!uap) in sbsa_uart_probe()
2893 uap->port.irq = ret; in sbsa_uart_probe()
2895 uap->vendor = &vendor_sbsa; in sbsa_uart_probe()
2896 qpdf2400_erratum44_workaround(&pdev->dev, uap); in sbsa_uart_probe()
2898 uap->reg_offset = uap->vendor->reg_offset; in sbsa_uart_probe()
2899 uap->fifosize = 32; in sbsa_uart_probe()
2900 uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; in sbsa_uart_probe()
2901 uap->port.ops = &sbsa_uart_pops; in sbsa_uart_probe()
2902 uap->fixed_baud = baudrate; in sbsa_uart_probe()
2904 snprintf(uap->type, sizeof(uap->type), "SBSA"); in sbsa_uart_probe()
2908 ret = pl011_setup_port(&pdev->dev, uap, r, portnr); in sbsa_uart_probe()
2912 platform_set_drvdata(pdev, uap); in sbsa_uart_probe()
2914 return pl011_register_port(uap); in sbsa_uart_probe()
2919 struct uart_amba_port *uap = platform_get_drvdata(pdev); in sbsa_uart_remove() local
2921 uart_remove_one_port(&amba_reg, &uap->port); in sbsa_uart_remove()
2922 pl011_unregister_port(uap); in sbsa_uart_remove()