65 	cr = readb(uap->port.membase + UART010_CR);  in pl010_stop_tx()
67 	writel(cr, uap->port.membase + UART010_CR);  in pl010_stop_tx()
76 	cr = readb(uap->port.membase + UART010_CR);  in pl010_start_tx()
78 	writel(cr, uap->port.membase + UART010_CR);  in pl010_start_tx()
87 	cr = readb(uap->port.membase + UART010_CR);  in pl010_stop_rx()
89 	writel(cr, uap->port.membase + UART010_CR);  in pl010_stop_rx()
97 	cr = readb(uap->port.membase + UART010_CR);  in pl010_disable_ms()
99 	writel(cr, uap->port.membase + UART010_CR);  in pl010_disable_ms()
108 	cr = readb(uap->port.membase + UART010_CR);  in pl010_enable_ms()
110 	writel(cr, uap->port.membase + UART010_CR);  in pl010_enable_ms()
118 	status = readb(port->membase + UART01x_FR);  in pl010_rx_chars()
120 		ch = readb(port->membase + UART01x_DR);  in pl010_rx_chars()
129 		rsr = readb(port->membase + UART01x_RSR) | UART_DUMMY_RSR_RX;  in pl010_rx_chars()
131 			writel(0, port->membase + UART01x_ECR);  in pl010_rx_chars()
161 		status = readb(port->membase + UART01x_FR);  in pl010_rx_chars()
172 		writel(ch, port->membase + UART01x_DR),  in pl010_tx_chars()
181 	writel(0, port->membase + UART010_ICR);  in pl010_modem_status()
183 	status = readb(port->membase + UART01x_FR) & UART01x_FR_MODEM_ANY;  in pl010_modem_status()
212 	status = readb(port->membase + UART010_IIR);  in pl010_int()
225 			status = readb(port->membase + UART010_IIR);  in pl010_int()
238 	unsigned int status = readb(port->membase + UART01x_FR);  in pl010_tx_empty()
248 	status = readb(port->membase + UART01x_FR);  in pl010_get_mctrl()
265 		uap->data->set_mctrl(uap->dev, port->membase, mctrl);  in pl010_set_mctrl()
274 	lcr_h = readb(port->membase + UART010_LCRH);  in pl010_break_ctl()
279 	writel(lcr_h, port->membase + UART010_LCRH);  in pl010_break_ctl()
308 	uap->old_status = readb(port->membase + UART01x_FR) & UART01x_FR_MODEM_ANY;  in pl010_startup()
314 	       port->membase + UART010_CR);  in pl010_startup()
337 	writel(0, port->membase + UART010_CR);  in pl010_shutdown()
340 	writel(readb(port->membase + UART010_LCRH) &  in pl010_shutdown()
342 	       port->membase + UART010_LCRH);  in pl010_shutdown()
423 	old_cr = readb(port->membase + UART010_CR) & ~UART010_CR_MSIE;  in pl010_set_termios()
430 	writel((quot & 0xf00) >> 8, port->membase + UART010_LCRM);  in pl010_set_termios()
431 	writel(quot & 0xff, port->membase + UART010_LCRL);  in pl010_set_termios()
438 	writel(lcr_h, port->membase + UART010_LCRH);  in pl010_set_termios()
439 	writel(old_cr, port->membase + UART010_CR);  in pl010_set_termios()
538 		status = readb(port->membase + UART01x_FR);  in pl010_console_putchar()
541 	writel(ch, port->membase + UART01x_DR);  in pl010_console_putchar()
556 	old_cr = readb(port->membase + UART010_CR);  in pl010_console_write()
557 	writel(UART01x_CR_UARTEN, port->membase + UART010_CR);  in pl010_console_write()
566 		status = readb(port->membase + UART01x_FR);  in pl010_console_write()
569 	writel(old_cr, port->membase + UART010_CR);  in pl010_console_write()
578 	if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {  in pl010_console_get_options()
580 		lcr_h = readb(uap->port.membase + UART010_LCRH);  in pl010_console_get_options()
595 		quot = readb(uap->port.membase + UART010_LCRL) |  in pl010_console_get_options()
596 		       readb(uap->port.membase + UART010_LCRM) << 8;  in pl010_console_get_options()
691 	uap->port.membase = base;  in pl010_probe()