Lines Matching +full:port +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0
3 * Probe module for 8250/16550-type MCHP PCI serial ports.
90 #define ADCL_CFG_PIN_SEL BIT(1)
101 #define UART_WAKE_NCTS BIT(1)
123 #define UART_BYTE_SIZE 1
148 .delay_rts_after_send = 1,
152 static int pci1xxxx_set_sys_lock(struct pci1xxxx_8250 *port) in pci1xxxx_set_sys_lock() argument
154 writel(UART_SYSLOCK, port->membase + UART_SYSLOCK_REG); in pci1xxxx_set_sys_lock()
155 return readl(port->membase + UART_SYSLOCK_REG); in pci1xxxx_set_sys_lock()
158 static int pci1xxxx_acquire_sys_lock(struct pci1xxxx_8250 *port) in pci1xxxx_acquire_sys_lock() argument
162 return readx_poll_timeout(pci1xxxx_set_sys_lock, port, regval, in pci1xxxx_acquire_sys_lock()
168 static void pci1xxxx_release_sys_lock(struct pci1xxxx_8250 *port) in pci1xxxx_release_sys_lock() argument
170 writel(0x0, port->membase + UART_SYSLOCK_REG); in pci1xxxx_release_sys_lock()
174 {0, 1, 2, 3}, /* PCI12000, PCI11010, PCI11101, PCI11400, PCI11414 */
175 {0, 1, 2, 3}, /* PCI4p */
176 {0, 1, 2, -1}, /* PCI3p012 */
177 {0, 1, 3, -1}, /* PCI3p013 */
178 {0, 2, 3, -1}, /* PCI3p023 */
179 {1, 2, 3, -1}, /* PCI3p123 */
180 {0, 1, -1, -1}, /* PCI2p01 */
181 {0, 2, -1, -1}, /* PCI2p02 */
182 {0, 3, -1, -1}, /* PCI2p03 */
183 {1, 2, -1, -1}, /* PCI2p12 */
184 {1, 3, -1, -1}, /* PCI2p13 */
185 {2, 3, -1, -1}, /* PCI2p23 */
186 {0, -1, -1, -1}, /* PCI1p0 */
187 {1, -1, -1, -1}, /* PCI1p1 */
188 {2, -1, -1, -1}, /* PCI1p2 */
189 {3, -1, -1, -1}, /* PCI1p3 */
194 switch (dev->subsystem_device) { in pci1xxxx_get_num_ports()
204 return 1; in pci1xxxx_get_num_ports()
223 static unsigned int pci1xxxx_get_divisor(struct uart_port *port, in pci1xxxx_get_divisor() argument
239 *frac = (NSEC_PER_SEC - quot * baud * uart_sample_cnt) * in pci1xxxx_get_divisor()
245 static void pci1xxxx_set_divisor(struct uart_port *port, unsigned int baud, in pci1xxxx_set_divisor() argument
249 writel(UART_BIT_DIVISOR_8, port->membase + FRAC_DIV_CFG_REG); in pci1xxxx_set_divisor()
251 writel(UART_BIT_DIVISOR_16, port->membase + FRAC_DIV_CFG_REG); in pci1xxxx_set_divisor()
254 port->membase + UART_BAUD_CLK_DIVISOR_REG); in pci1xxxx_set_divisor()
257 static int pci1xxxx_rs485_config(struct uart_port *port, in pci1xxxx_rs485_config() argument
268 frac_div = readl(port->membase + FRAC_DIV_CFG_REG); in pci1xxxx_rs485_config()
279 if (rs485->flags & SER_RS485_ENABLED) { in pci1xxxx_rs485_config()
282 if (!(rs485->flags & SER_RS485_RTS_ON_SEND)) in pci1xxxx_rs485_config()
285 if (rs485->delay_rts_after_send) { in pci1xxxx_rs485_config()
286 clock_div = readl(port->membase + UART_BAUD_CLK_DIVISOR_REG); in pci1xxxx_rs485_config()
291 rs485->delay_rts_after_send * NSEC_PER_MSEC / in pci1xxxx_rs485_config()
298 rs485->delay_rts_after_send = in pci1xxxx_rs485_config()
303 writel(mode_cfg, port->membase + ADCL_CFG_REG); in pci1xxxx_rs485_config()
307 static u32 pci1xxxx_read_burst_status(struct uart_port *port) in pci1xxxx_read_burst_status() argument
311 status = readl(port->membase + UART_BURST_STATUS_REG); in pci1xxxx_read_burst_status()
315 port->membase + UART_FIFO_CTL); in pci1xxxx_read_burst_status()
316 port->icount.overrun++; in pci1xxxx_read_burst_status()
320 port->icount.frame++; in pci1xxxx_read_burst_status()
323 port->icount.parity++; in pci1xxxx_read_burst_status()
328 static void pci1xxxx_process_read_data(struct uart_port *port, in pci1xxxx_process_read_data() argument
341 while (valid_burst_count--) { in pci1xxxx_process_read_data()
342 if (*buff_index > (RX_BUF_SIZE - UART_BURST_SIZE)) in pci1xxxx_process_read_data()
345 *burst_buf = readl(port->membase + UART_RX_BURST_FIFO); in pci1xxxx_process_read_data()
347 *valid_byte_count -= UART_BURST_SIZE; in pci1xxxx_process_read_data()
353 rx_buff[*buff_index] = readb(port->membase + in pci1xxxx_process_read_data()
356 *valid_byte_count -= UART_BYTE_SIZE; in pci1xxxx_process_read_data()
360 static void pci1xxxx_rx_burst(struct uart_port *port, u32 uart_status) in pci1xxxx_rx_burst() argument
363 struct tty_port *tty_port = &port->state->port; in pci1xxxx_rx_burst()
370 pci1xxxx_process_read_data(port, rx_buff, &buff_index, in pci1xxxx_rx_burst()
377 port->icount.overrun += buff_index - copied_len; in pci1xxxx_rx_burst()
379 port->icount.rx += buff_index; in pci1xxxx_rx_burst()
384 static void pci1xxxx_process_write_data(struct uart_port *port, in pci1xxxx_process_write_data() argument
388 struct tty_port *tport = &port->state->port; in pci1xxxx_process_write_data()
400 if (*data_empty_count - UART_BURST_SIZE < 0) in pci1xxxx_process_write_data()
402 if (kfifo_len(&tport->xmit_fifo) < UART_BURST_SIZE) in pci1xxxx_process_write_data()
404 if (WARN_ON(kfifo_out(&tport->xmit_fifo, (u8 *)&c, sizeof(c)) != in pci1xxxx_process_write_data()
407 writel(c, port->membase + UART_TX_BURST_FIFO); in pci1xxxx_process_write_data()
408 *valid_byte_count -= UART_BURST_SIZE; in pci1xxxx_process_write_data()
409 *data_empty_count -= UART_BURST_SIZE; in pci1xxxx_process_write_data()
410 valid_burst_count -= UART_BYTE_SIZE; in pci1xxxx_process_write_data()
416 if (!kfifo_get(&tport->xmit_fifo, &c)) in pci1xxxx_process_write_data()
418 writeb(c, port->membase + UART_TX_BYTE_FIFO); in pci1xxxx_process_write_data()
419 *data_empty_count -= UART_BYTE_SIZE; in pci1xxxx_process_write_data()
420 *valid_byte_count -= UART_BYTE_SIZE; in pci1xxxx_process_write_data()
427 kfifo_len(&tport->xmit_fifo) >= UART_BURST_SIZE) in pci1xxxx_process_write_data()
432 static void pci1xxxx_tx_burst(struct uart_port *port, u32 uart_status) in pci1xxxx_tx_burst() argument
434 struct uart_8250_port *up = up_to_u8250p(port); in pci1xxxx_tx_burst()
435 struct tty_port *tport = &port->state->port; in pci1xxxx_tx_burst()
439 if (port->x_char) { in pci1xxxx_tx_burst()
440 writeb(port->x_char, port->membase + UART_TX); in pci1xxxx_tx_burst()
441 port->icount.tx++; in pci1xxxx_tx_burst()
442 port->x_char = 0; in pci1xxxx_tx_burst()
446 if ((uart_tx_stopped(port)) || kfifo_is_empty(&tport->xmit_fifo)) { in pci1xxxx_tx_burst()
447 port->ops->stop_tx(port); in pci1xxxx_tx_burst()
449 data_empty_count = (pci1xxxx_read_burst_status(port) & in pci1xxxx_tx_burst()
452 valid_byte_count = kfifo_len(&tport->xmit_fifo); in pci1xxxx_tx_burst()
454 pci1xxxx_process_write_data(port, in pci1xxxx_tx_burst()
458 port->icount.tx++; in pci1xxxx_tx_burst()
459 if (kfifo_is_empty(&tport->xmit_fifo)) in pci1xxxx_tx_burst()
464 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in pci1xxxx_tx_burst()
465 uart_write_wakeup(port); in pci1xxxx_tx_burst()
472 if (kfifo_is_empty(&tport->xmit_fifo) && in pci1xxxx_tx_burst()
473 !(up->capabilities & UART_CAP_RPM)) in pci1xxxx_tx_burst()
474 port->ops->stop_tx(port); in pci1xxxx_tx_burst()
477 static int pci1xxxx_handle_irq(struct uart_port *port) in pci1xxxx_handle_irq() argument
482 status = pci1xxxx_read_burst_status(port); in pci1xxxx_handle_irq()
487 spin_lock_irqsave(&port->lock, flags); in pci1xxxx_handle_irq()
490 pci1xxxx_rx_burst(port, status); in pci1xxxx_handle_irq()
493 pci1xxxx_tx_burst(port, status); in pci1xxxx_handle_irq()
495 spin_unlock_irqrestore(&port->lock, flags); in pci1xxxx_handle_irq()
497 return 1; in pci1xxxx_handle_irq()
503 struct uart_port *port = &up->port; in pci1xxxx_port_suspend() local
504 struct tty_port *tport = &port->state->port; in pci1xxxx_port_suspend()
509 mutex_lock(&tport->mutex); in pci1xxxx_port_suspend()
510 if (port->suspended == 0 && port->dev) { in pci1xxxx_port_suspend()
511 wakeup_mask = readb(up->port.membase + UART_WAKE_MASK_REG); in pci1xxxx_port_suspend()
513 uart_port_lock_irqsave(port, &flags); in pci1xxxx_port_suspend()
514 port->mctrl &= ~TIOCM_OUT2; in pci1xxxx_port_suspend()
515 port->ops->set_mctrl(port, port->mctrl); in pci1xxxx_port_suspend()
516 uart_port_unlock_irqrestore(port, flags); in pci1xxxx_port_suspend()
521 writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG); in pci1xxxx_port_suspend()
522 mutex_unlock(&tport->mutex); in pci1xxxx_port_suspend()
530 struct uart_port *port = &up->port; in pci1xxxx_port_resume() local
531 struct tty_port *tport = &port->state->port; in pci1xxxx_port_resume()
534 mutex_lock(&tport->mutex); in pci1xxxx_port_resume()
535 writeb(UART_BLOCK_SET_ACTIVE, port->membase + UART_ACTV_REG); in pci1xxxx_port_resume()
536 writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG); in pci1xxxx_port_resume()
538 if (port->suspended == 0) { in pci1xxxx_port_resume()
539 uart_port_lock_irqsave(port, &flags); in pci1xxxx_port_resume()
540 port->mctrl |= TIOCM_OUT2; in pci1xxxx_port_resume()
541 port->ops->set_mctrl(port, port->mctrl); in pci1xxxx_port_resume()
542 uart_port_unlock_irqrestore(port, flags); in pci1xxxx_port_resume()
544 mutex_unlock(&tport->mutex); in pci1xxxx_port_resume()
556 for (i = 0; i < priv->nr; i++) { in pci1xxxx_suspend()
557 if (priv->line[i] >= 0) { in pci1xxxx_suspend()
558 serial8250_suspend_port(priv->line[i]); in pci1xxxx_suspend()
559 wakeup |= pci1xxxx_port_suspend(priv->line[i]); in pci1xxxx_suspend()
566 return -ENOMEM; in pci1xxxx_suspend()
593 return -ENOMEM; in pci1xxxx_resume()
600 for (i = 0; i < priv->nr; i++) { in pci1xxxx_resume()
601 if (priv->line[i] >= 0) { in pci1xxxx_resume()
602 pci1xxxx_port_resume(priv->line[i]); in pci1xxxx_resume()
603 serial8250_resume_port(priv->line[i]); in pci1xxxx_resume()
611 struct uart_8250_port *port, int port_idx, int rev) in pci1xxxx_setup() argument
615 port->port.flags |= UPF_FIXED_TYPE | UPF_SKIP_TEST; in pci1xxxx_setup()
616 port->port.type = PORT_MCHP16550A; in pci1xxxx_setup()
627 port->port.uartclk = 64 * HZ_PER_MHZ; in pci1xxxx_setup()
628 port->port.set_termios = serial8250_do_set_termios; in pci1xxxx_setup()
629 port->port.get_divisor = pci1xxxx_get_divisor; in pci1xxxx_setup()
630 port->port.set_divisor = pci1xxxx_set_divisor; in pci1xxxx_setup()
631 port->port.rs485_config = pci1xxxx_rs485_config; in pci1xxxx_setup()
632 port->port.rs485_supported = pci1xxxx_rs485_supported; in pci1xxxx_setup()
636 port->port.handle_irq = pci1xxxx_handle_irq; in pci1xxxx_setup()
638 ret = serial8250_pci_setup_port(pdev, port, 0, PORT_OFFSET * port_idx, 0); in pci1xxxx_setup()
642 writeb(UART_BLOCK_SET_ACTIVE, port->port.membase + UART_ACTV_REG); in pci1xxxx_setup()
643 writeb(UART_WAKE_SRCS, port->port.membase + UART_WAKE_REG); in pci1xxxx_setup()
644 writeb(UART_WAKE_N_PIN, port->port.membase + UART_WAKE_MASK_REG); in pci1xxxx_setup()
654 while (i--) { in pci1xxxx_get_max_port()
655 if (logical_to_physical_port_idx[subsys_dev][i] != -1) in pci1xxxx_get_max_port()
656 return logical_to_physical_port_idx[subsys_dev][i] + 1; in pci1xxxx_get_max_port()
662 return 1; in pci1xxxx_get_max_port()
665 static int pci1xxxx_logical_to_physical_port_translate(int subsys_dev, int port) in pci1xxxx_logical_to_physical_port_translate() argument
668 return logical_to_physical_port_idx[subsys_dev][port]; in pci1xxxx_logical_to_physical_port_translate()
670 return logical_to_physical_port_idx[0][port]; in pci1xxxx_logical_to_physical_port_translate()
686 regval = readl(priv->membase + UART_DEV_REV_REG); in pci1xxxx_get_device_revision()
687 priv->dev_rev = regval & UART_DEV_REV_MASK; in pci1xxxx_get_device_revision()
697 struct device *dev = &pdev->dev; in pci1xxxx_serial_probe()
716 return -ENOMEM; in pci1xxxx_serial_probe()
718 priv->membase = pci_ioremap_bar(pdev, 0); in pci1xxxx_serial_probe()
719 if (!priv->membase) in pci1xxxx_serial_probe()
720 return -ENOMEM; in pci1xxxx_serial_probe()
728 priv->nr = nr_ports; in pci1xxxx_serial_probe()
730 subsys_dev = pdev->subsystem_device; in pci1xxxx_serial_probe()
733 num_vectors = pci_alloc_irq_vectors(pdev, 1, max_vec_reqd, PCI_IRQ_ALL_TYPES); in pci1xxxx_serial_probe()
735 pci_iounmap(pdev, priv->membase); in pci1xxxx_serial_probe()
740 uart.port.flags = UPF_SHARE_IRQ | UPF_FIXED_PORT; in pci1xxxx_serial_probe()
741 uart.port.dev = dev; in pci1xxxx_serial_probe()
744 writeb(UART_PCI_CTRL_SET_MULTIPLE_MSI, priv->membase + UART_PCI_CTRL_REG); in pci1xxxx_serial_probe()
747 priv->line[i] = -ENODEV; in pci1xxxx_serial_probe()
752 uart.port.irq = pci_irq_vector(pdev, port_idx); in pci1xxxx_serial_probe()
754 uart.port.irq = pci_irq_vector(pdev, 0); in pci1xxxx_serial_probe()
756 rc = pci1xxxx_setup(pdev, &uart, port_idx, priv->dev_rev); in pci1xxxx_serial_probe()
758 dev_warn(dev, "Failed to setup port %u\n", i); in pci1xxxx_serial_probe()
762 priv->line[i] = serial8250_register_8250_port(&uart); in pci1xxxx_serial_probe()
763 if (priv->line[i] < 0) { in pci1xxxx_serial_probe()
765 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", in pci1xxxx_serial_probe()
766 uart.port.iobase, uart.port.irq, uart.port.iotype, in pci1xxxx_serial_probe()
767 priv->line[i]); in pci1xxxx_serial_probe()
781 for (i = 0; i < priv->nr; i++) { in pci1xxxx_serial_remove()
782 if (priv->line[i] >= 0) in pci1xxxx_serial_remove()
783 serial8250_unregister_port(priv->line[i]); in pci1xxxx_serial_remove()
787 pci_iounmap(dev, priv->membase); in pci1xxxx_serial_remove()
813 static_assert((ARRAY_SIZE(logical_to_physical_port_idx) == PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3 + 1));