1 // SPDX-License-Identifier: GPL-2.0+
79 	struct dw8250_port_data *d = p->private_data;  in dw8250_get_divisor()
81 	quot = p->uartclk / base_baud;  in dw8250_get_divisor()
82 	rem = p->uartclk % base_baud;  in dw8250_get_divisor()
83 	*frac = DIV_ROUND_CLOSEST(rem << d->dlf_size, base_baud);  in dw8250_get_divisor()
98 	p->status &= ~UPSTAT_AUTOCTS;  in dw8250_do_set_termios()
99 	if (termios->c_cflag & CRTSCTS)  in dw8250_do_set_termios()
100 		p->status |= UPSTAT_AUTOCTS;  in dw8250_do_set_termios()
105 	p->ignore_status_mask |= DW_UART_LSR_ADDR_RCVD;  in dw8250_do_set_termios()
106 	p->read_status_mask |= DW_UART_LSR_ADDR_RCVD;  in dw8250_do_set_termios()
111  * Wait until re is de-asserted for sure. An ongoing receive will keep
112  * re asserted until end of frame. Without BUSY indication available,
119 	ndelay(p->frame_time);  in dw8250_wait_re_deassert()
127 	 * RAR shouldn't be changed while receiving. Thus, de-assert RE_EN  in dw8250_update_rar()
128 	 * if asserted and wait.  in dw8250_update_rar()
143 	if (rs485->flags & SER_RS485_ADDRB) {  in dw8250_rs485_set_addr()
146 			termios->c_cflag |= ADDRB;  in dw8250_rs485_set_addr()
148 		if (rs485->flags & SER_RS485_ADDR_RECV) {  in dw8250_rs485_set_addr()
149 			u32 delta = p->rs485.flags ^ rs485->flags;  in dw8250_rs485_set_addr()
155 			if (unlikely(&p->rs485 == rs485))  in dw8250_rs485_set_addr()
156 				delta = rs485->flags;  in dw8250_rs485_set_addr()
159 			    (p->rs485.addr_recv != rs485->addr_recv))  in dw8250_rs485_set_addr()
160 				dw8250_update_rar(p, rs485->addr_recv);  in dw8250_rs485_set_addr()
165 		if (rs485->flags & SER_RS485_ADDR_DEST) {  in dw8250_rs485_set_addr()
171 			dw8250_writel_ext(p, DW_UART_TAR, rs485->addr_dest);  in dw8250_rs485_set_addr()
188 	if (rs485->flags & SER_RS485_ENABLED) {  in dw8250_rs485_config()
191 		if (rs485->flags & SER_RS485_RX_DURING_TX)  in dw8250_rs485_config()
199 			termios->c_cflag &= ~ADDRB;  in dw8250_rs485_config()
208 	if (!(rs485->flags & SER_RS485_RTS_ON_SEND))  in dw8250_rs485_config()
210 	if (device_property_read_bool(p->dev, "rs485-rx-active-high"))  in dw8250_rs485_config()
216 	if (rs485->flags & SER_RS485_ENABLED)  in dw8250_rs485_config()
223  * Tests if RE_EN register can have non-zero value to see if RS-485 HW support
244 	struct dw8250_port_data *pd = p->private_data;  in dw8250_setup_port()
248 	pd->hw_rs485_support = dw8250_detect_rs485_hw(p);  in dw8250_setup_port()
249 	if (pd->hw_rs485_support) {  in dw8250_setup_port()
250 		p->rs485_config = dw8250_rs485_config;  in dw8250_setup_port()
251 		up->lsr_save_mask = LSR_SAVE_FLAGS | DW_UART_LSR_ADDR_RCVD;  in dw8250_setup_port()
252 		p->rs485_supported = dw8250_rs485_supported;  in dw8250_setup_port()
254 		p->rs485_config = serial8250_em485_config;  in dw8250_setup_port()
255 		p->rs485_supported = serial8250_em485_supported;  in dw8250_setup_port()
256 		up->rs485_start_tx = serial8250_em485_start_tx;  in dw8250_setup_port()
257 		up->rs485_stop_tx = serial8250_em485_stop_tx;  in dw8250_setup_port()
259 	up->capabilities |= UART_CAP_NOTEMT;  in dw8250_setup_port()
268 		pd->dlf_size = fls(reg);  in dw8250_setup_port()
269 		p->get_divisor = dw8250_get_divisor;  in dw8250_setup_port()
270 		p->set_divisor = dw8250_set_divisor;  in dw8250_setup_port()
275 		dev_dbg(p->dev, "Designware UART version %c.%c%c\n",  in dw8250_setup_port()
280 		reg = pd->cpr_value;  in dw8250_setup_port()
281 		dev_dbg(p->dev, "CPR is not available, using 0x%08x instead\n", reg);  in dw8250_setup_port()
288 		p->type = PORT_16550A;  in dw8250_setup_port()
289 		p->flags |= UPF_FIXED_TYPE;  in dw8250_setup_port()
290 		p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);  in dw8250_setup_port()
291 		up->capabilities = UART_CAP_FIFO | UART_CAP_NOTEMT;  in dw8250_setup_port()
295 		up->capabilities |= UART_CAP_AFE;  in dw8250_setup_port()
298 		up->capabilities |= UART_CAP_IRDA;  in dw8250_setup_port()