Lines Matching +full:0 +full:x1e8

27  * DRA752_BANDGAP_BASE		0x4a0021e0
34 #define DRA752_BANDGAP_CTRL_1_OFFSET		0x1a0
35 #define DRA752_BANDGAP_STATUS_1_OFFSET		0x1c8
36 #define DRA752_BANDGAP_CTRL_2_OFFSET		0x39c
37 #define DRA752_BANDGAP_STATUS_2_OFFSET		0x3b8
40 #define DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET		0x8
41 #define DRA752_TEMP_SENSOR_CORE_OFFSET			0x154
42 #define DRA752_BANDGAP_THRESHOLD_CORE_OFFSET		0x1ac
43 #define DRA752_DTEMP_CORE_1_OFFSET			0x20c
44 #define DRA752_DTEMP_CORE_2_OFFSET			0x210
47 #define DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET		0x388
48 #define DRA752_TEMP_SENSOR_IVA_OFFSET			0x398
49 #define DRA752_BANDGAP_THRESHOLD_IVA_OFFSET		0x3a4
50 #define DRA752_DTEMP_IVA_1_OFFSET			0x3d4
51 #define DRA752_DTEMP_IVA_2_OFFSET			0x3d8
54 #define DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET		0x4
55 #define DRA752_TEMP_SENSOR_MPU_OFFSET			0x14c
56 #define DRA752_BANDGAP_THRESHOLD_MPU_OFFSET		0x1a4
57 #define DRA752_DTEMP_MPU_1_OFFSET			0x1e4
58 #define DRA752_DTEMP_MPU_2_OFFSET			0x1e8
61 #define DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET			0x384
62 #define DRA752_TEMP_SENSOR_DSPEVE_OFFSET			0x394
63 #define DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET			0x3a0
64 #define DRA752_DTEMP_DSPEVE_1_OFFSET				0x3c0
65 #define DRA752_DTEMP_DSPEVE_2_OFFSET				0x3c4
68 #define DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET		0x0
69 #define DRA752_TEMP_SENSOR_GPU_OFFSET			0x150
70 #define DRA752_BANDGAP_THRESHOLD_GPU_OFFSET		0x1a8
71 #define DRA752_DTEMP_GPU_1_OFFSET			0x1f8
72 #define DRA752_DTEMP_GPU_2_OFFSET			0x1fc
88 #define DRA752_BANDGAP_STATUS_1_COLD_MPU_MASK		BIT(0)
96 #define DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK		BIT(0)
102 #define DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK		BIT(0)
105 #define DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK		(0x7 << 27)
114 #define DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK		BIT(0)
119 #define DRA752_TEMP_SENSOR_DTEMP_MASK		(0x3ff << 0)
122 #define DRA752_BANDGAP_THRESHOLD_HOT_MASK		(0x3ff << 16)
123 #define DRA752_BANDGAP_THRESHOLD_COLD_MASK		(0x3ff << 0)