Lines Matching refs:REG_SET_MASK
199 #define REG_SET_MASK(r, m, v) (((r) & ~(m)) | \ macro
488 r = REG_SET_MASK(r, sg->thermtrip_threshold_mask, temp); in thermtrip_program()
489 r = REG_SET_MASK(r, sg->thermtrip_enable_mask, 1); in thermtrip_program()
490 r = REG_SET_MASK(r, sg->thermtrip_any_en_mask, 0); in thermtrip_program()
545 r = REG_SET_MASK(r, sg->thermctl_lvl0_up_thresh_mask, temp); in throttrip_program()
546 r = REG_SET_MASK(r, sg->thermctl_lvl0_dn_thresh_mask, temp); in throttrip_program()
547 r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_CPU_THROT_MASK, cpu_throt); in throttrip_program()
548 r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_GPU_THROT_MASK, gpu_throt); in throttrip_program()
549 r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_EN_MASK, 1); in throttrip_program()
637 r = REG_SET_MASK(r, zn->sg->thermctl_isr_mask, TH_INTR_UP_DN_EN); in thermal_irq_enable()
649 r = REG_SET_MASK(r, zn->sg->thermctl_isr_mask, 0); in thermal_irq_disable()
662 r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_EN_MASK, 0); in tegra_thermctl_set_trips()
669 r = REG_SET_MASK(r, zone->sg->thermctl_lvl0_up_thresh_mask, hi); in tegra_thermctl_set_trips()
670 r = REG_SET_MASK(r, zone->sg->thermctl_lvl0_dn_thresh_mask, lo); in tegra_thermctl_set_trips()
671 r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_EN_MASK, 1); in tegra_thermctl_set_trips()
916 r = REG_SET_MASK(r, OC_INTR_OC1_MASK, 1); in soctherm_oc_intr_enable()
919 r = REG_SET_MASK(r, OC_INTR_OC2_MASK, 1); in soctherm_oc_intr_enable()
922 r = REG_SET_MASK(r, OC_INTR_OC3_MASK, 1); in soctherm_oc_intr_enable()
925 r = REG_SET_MASK(r, OC_INTR_OC4_MASK, 1); in soctherm_oc_intr_enable()
1754 r = REG_SET_MASK(r, CCROC_THROT_PSKIP_RAMP_DURATION_MASK, 0xff); in throttlectl_cpu_level_cfg()
1755 r = REG_SET_MASK(r, CCROC_THROT_PSKIP_RAMP_STEP_MASK, 0xf); in throttlectl_cpu_level_cfg()
1759 r = REG_SET_MASK(r, CCROC_THROT_PSKIP_CTRL_ENB_MASK, 1); in throttlectl_cpu_level_cfg()
1760 r = REG_SET_MASK(r, CCROC_THROT_PSKIP_CTRL_DIVIDEND_MASK, dividend); in throttlectl_cpu_level_cfg()
1761 r = REG_SET_MASK(r, CCROC_THROT_PSKIP_CTRL_DIVISOR_MASK, 0xff); in throttlectl_cpu_level_cfg()
1799 r = REG_SET_MASK(r, THROT_PSKIP_CTRL_ENABLE_MASK, 1); in throttlectl_cpu_level_select()
1800 r = REG_SET_MASK(r, THROT_PSKIP_CTRL_VECT_CPU_MASK, throt_vect); in throttlectl_cpu_level_select()
1801 r = REG_SET_MASK(r, THROT_PSKIP_CTRL_VECT2_CPU_MASK, throt_vect); in throttlectl_cpu_level_select()
1805 r = REG_SET_MASK(0, THROT_PSKIP_RAMP_SEQ_BYPASS_MODE_MASK, 1); in throttlectl_cpu_level_select()
1832 r = REG_SET_MASK(r, THROT_PSKIP_CTRL_ENABLE_MASK, 1); in throttlectl_cpu_mn()
1833 r = REG_SET_MASK(r, THROT_PSKIP_CTRL_DIVIDEND_MASK, dividend); in throttlectl_cpu_mn()
1834 r = REG_SET_MASK(r, THROT_PSKIP_CTRL_DIVISOR_MASK, 0xff); in throttlectl_cpu_mn()
1838 r = REG_SET_MASK(r, THROT_PSKIP_RAMP_DURATION_MASK, 0xff); in throttlectl_cpu_mn()
1839 r = REG_SET_MASK(r, THROT_PSKIP_RAMP_STEP_MASK, 0xf); in throttlectl_cpu_mn()
1861 r = REG_SET_MASK(r, THROT_PSKIP_CTRL_ENABLE_MASK, 1); in throttlectl_gpu_level_select()
1862 r = REG_SET_MASK(r, THROT_PSKIP_CTRL_VECT_GPU_MASK, throt_vect); in throttlectl_gpu_level_select()
1875 r = REG_SET_MASK(0, OC1_CFG_HW_RESTORE_MASK, 1); in soctherm_oc_cfg_program()
1876 r = REG_SET_MASK(r, OC1_CFG_THROTTLE_MODE_MASK, oc->mode); in soctherm_oc_cfg_program()
1877 r = REG_SET_MASK(r, OC1_CFG_ALARM_POLARITY_MASK, oc->active_low); in soctherm_oc_cfg_program()
1878 r = REG_SET_MASK(r, OC1_CFG_EN_THROTTLE_MASK, 1); in soctherm_oc_cfg_program()
1916 r = REG_SET_MASK(0, THROT_PRIORITY_LITE_PRIO_MASK, stc.priority); in soctherm_throttle_program()
1919 r = REG_SET_MASK(0, THROT_DELAY_LITE_DELAY_MASK, 0); in soctherm_throttle_program()
1926 r = REG_SET_MASK(0, THROT_PRIORITY_LOCK_PRIORITY_MASK, in soctherm_throttle_program()
1948 v = REG_SET_MASK(0, THROT_GLOBAL_ENB_MASK, 1); in tegra_soctherm_throttle()
1953 v = REG_SET_MASK(v, CDIVG_USE_THERM_CONTROLS_MASK, 1); in tegra_soctherm_throttle()
1959 v = REG_SET_MASK(v, CDIVG_USE_THERM_CONTROLS_MASK, 1); in tegra_soctherm_throttle()
2035 pdiv = REG_SET_MASK(pdiv, ttgs[i]->pdiv_mask, in soctherm_init()
2040 hotspot = REG_SET_MASK(hotspot, in soctherm_init()