Lines Matching +full:chip +full:- +full:temperature +full:- +full:threshold +full:- +full:celsius
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014 - 2018, NVIDIA CORPORATION. All rights reserved.
34 #include <dt-bindings/thermal/tegra124-soctherm.h>
197 #define REG_GET_MASK(r, m) (((r) & (m)) >> (ffs(m) - 1))
200 (((v) & (m >> (ffs(m) - 1))) << (ffs(m) - 1)))
203 #define THROT_DEPTH_DIVIDEND(depth) ((256 * (100 - (depth)) / 100) - 1)
205 /* gk20a nv_therm interface N:3 Mapping. Levels defined in tegra124-soctherm.h
212 #define THROT_LEVEL_TO_DEPTH(level) ((0x1 << (level)) - 1)
229 (ALARM_OFFSET * (throt - THROTTLE_OC1)))
232 (ALARM_OFFSET * (throt - THROTTLE_OC1)))
235 (ALARM_OFFSET * (throt - THROTTLE_OC1)))
238 (ALARM_OFFSET * (throt - THROTTLE_OC1)))
241 (ALARM_OFFSET * (throt - THROTTLE_OC1)))
244 (4 * (throt - THROTTLE_OC1)))
260 static const int min_low_temp = -127000;
361 * ccroc_writel() - writes a value to a CCROC register
370 writel(value, (ts->ccroc_regs + reg)); in ccroc_writel()
374 * ccroc_readl() - reads specified register from CCROC IP block
382 return readl(ts->ccroc_regs + reg); in ccroc_readl()
387 const struct tegra_tsensor *sensor = &tegra->soc->tsensors[i]; in enable_tsensor()
388 void __iomem *base = tegra->regs + sensor->base; in enable_tsensor()
391 val = sensor->config->tall << SENSOR_CONFIG0_TALL_SHIFT; in enable_tsensor()
394 val = (sensor->config->tsample - 1) << SENSOR_CONFIG1_TSAMPLE_SHIFT; in enable_tsensor()
395 val |= sensor->config->tiddq_en << SENSOR_CONFIG1_TIDDQ_EN_SHIFT; in enable_tsensor()
396 val |= sensor->config->ten_count << SENSOR_CONFIG1_TEN_COUNT_SHIFT; in enable_tsensor()
400 writel(tegra->calib[i], base + SENSOR_CONFIG2); in enable_tsensor()
407 * where T's contain the temperature in Celsius,
408 * H denotes an addition of 0.5 Celsius and N denotes negation
419 t *= -1; in translate_temp()
429 val = readl(zone->reg); in tegra_thermctl_get_temp()
430 val = REG_GET_MASK(val, zone->sg->sensor_temp_mask); in tegra_thermctl_get_temp()
437 * enforce_temp_range() - check and enforce temperature range [min, max]
439 * @trip_temp: the trip temperature to check
441 * Checks and enforces the permitted temperature range that SOC_THERM
445 * Return: The precision adjusted capped temperature in millicelsius.
453 dev_dbg(dev, "soctherm: trip temperature %d forced to %d\n", in enforce_temp_range()
459 * thermtrip_program() - Configures the hardware to shut down the
460 * system if a given sensor group reaches a given temperature
462 * @sg: pointer to the sensor group to set the thermtrip temperature for
463 * @trip_temp: the temperature in millicelsius to trigger the thermal trip at
465 * Sets the thermal trip threshold of the given sensor group to be the
466 * @trip_temp. If this threshold is crossed, the hardware will shut
470 * hardware is programmed in degrees Celsius.
472 * Return: 0 upon success, or %-EINVAL upon failure.
482 if (!sg || !sg->thermtrip_threshold_mask) in thermtrip_program()
483 return -EINVAL; in thermtrip_program()
485 temp = enforce_temp_range(dev, trip_temp) / ts->soc->thresh_grain; in thermtrip_program()
487 r = readl(ts->regs + THERMCTL_THERMTRIP_CTL); in thermtrip_program()
488 r = REG_SET_MASK(r, sg->thermtrip_threshold_mask, temp); in thermtrip_program()
489 r = REG_SET_MASK(r, sg->thermtrip_enable_mask, 1); in thermtrip_program()
490 r = REG_SET_MASK(r, sg->thermtrip_any_en_mask, 0); in thermtrip_program()
491 writel(r, ts->regs + THERMCTL_THERMTRIP_CTL); in thermtrip_program()
497 * throttrip_program() - Configures the hardware to throttle the
498 * pulse if a given sensor group reaches a given temperature
500 * @sg: pointer to the sensor group to set the thermtrip temperature for
502 * @trip_temp: the temperature in millicelsius to trigger the thermal trip at
504 * Sets the thermal trip threshold and throttle event of the given sensor
505 * group. If this threshold is crossed, the hardware will trigger the
509 * hardware is programmed in degrees Celsius.
511 * Return: 0 upon success, or %-EINVAL upon failure.
523 if (!sg || !stc || !stc->init) in throttrip_program()
524 return -EINVAL; in throttrip_program()
526 temp = enforce_temp_range(dev, trip_temp) / ts->soc->thresh_grain; in throttrip_program()
529 throt = stc->id; in throttrip_program()
530 reg_off = THERMCTL_LVL_REG(sg->thermctl_lvl0_offset, throt + 1); in throttrip_program()
540 "invalid throt id %d - assuming HEAVY", in throttrip_program()
544 r = readl(ts->regs + reg_off); in throttrip_program()
545 r = REG_SET_MASK(r, sg->thermctl_lvl0_up_thresh_mask, temp); in throttrip_program()
546 r = REG_SET_MASK(r, sg->thermctl_lvl0_dn_thresh_mask, temp); in throttrip_program()
550 writel(r, ts->regs + reg_off); in throttrip_program()
560 for (i = 0; ts->throt_cfgs[i].name; i++) in find_throttle_cfg_by_name()
561 if (!strcmp(ts->throt_cfgs[i].name, name)) in find_throttle_cfg_by_name()
562 return &ts->throt_cfgs[i]; in find_throttle_cfg_by_name()
570 struct tsensor_group_thermtrips *tt = ts->soc->thermtrips; in tsensor_group_thermtrip_get()
576 for (i = 0; i < ts->soc->num_ttgs; i++) { in tsensor_group_thermtrip_get()
589 struct tegra_soctherm *ts = zone->ts; in tegra_thermctl_set_trip_temp()
590 const struct tegra_tsensor_group *sg = zone->sg; in tegra_thermctl_set_trip_temp()
591 struct device *dev = zone->dev; in tegra_thermctl_set_trip_temp()
594 return -EINVAL; in tegra_thermctl_set_trip_temp()
596 if (trip->type == THERMAL_TRIP_CRITICAL) { in tegra_thermctl_set_trip_temp()
602 if (min_low_temp == tsensor_group_thermtrip_get(ts, sg->id)) in tegra_thermctl_set_trip_temp()
607 } else if (trip->type == THERMAL_TRIP_HOT) { in tegra_thermctl_set_trip_temp()
614 if (!ts->throt_cfgs[i].init) in tegra_thermctl_set_trip_temp()
617 cdev = ts->throt_cfgs[i].cdev; in tegra_thermctl_set_trip_temp()
619 stc = find_throttle_cfg_by_name(ts, cdev->type); in tegra_thermctl_set_trip_temp()
635 mutex_lock(&zn->ts->thermctl_lock); in thermal_irq_enable()
636 r = readl(zn->ts->regs + THERMCTL_INTR_ENABLE); in thermal_irq_enable()
637 r = REG_SET_MASK(r, zn->sg->thermctl_isr_mask, TH_INTR_UP_DN_EN); in thermal_irq_enable()
638 writel(r, zn->ts->regs + THERMCTL_INTR_ENABLE); in thermal_irq_enable()
639 mutex_unlock(&zn->ts->thermctl_lock); in thermal_irq_enable()
647 mutex_lock(&zn->ts->thermctl_lock); in thermal_irq_disable()
648 r = readl(zn->ts->regs + THERMCTL_INTR_DISABLE); in thermal_irq_disable()
649 r = REG_SET_MASK(r, zn->sg->thermctl_isr_mask, 0); in thermal_irq_disable()
650 writel(r, zn->ts->regs + THERMCTL_INTR_DISABLE); in thermal_irq_disable()
651 mutex_unlock(&zn->ts->thermctl_lock); in thermal_irq_disable()
661 r = readl(zone->ts->regs + zone->sg->thermctl_lvl0_offset); in tegra_thermctl_set_trips()
663 writel(r, zone->ts->regs + zone->sg->thermctl_lvl0_offset); in tegra_thermctl_set_trips()
665 lo = enforce_temp_range(zone->dev, lo) / zone->ts->soc->thresh_grain; in tegra_thermctl_set_trips()
666 hi = enforce_temp_range(zone->dev, hi) / zone->ts->soc->thresh_grain; in tegra_thermctl_set_trips()
667 dev_dbg(zone->dev, "%s hi:%d, lo:%d\n", __func__, hi, lo); in tegra_thermctl_set_trips()
669 r = REG_SET_MASK(r, zone->sg->thermctl_lvl0_up_thresh_mask, hi); in tegra_thermctl_set_trips()
670 r = REG_SET_MASK(r, zone->sg->thermctl_lvl0_dn_thresh_mask, lo); in tegra_thermctl_set_trips()
672 writel(r, zone->ts->regs + zone->sg->thermctl_lvl0_offset); in tegra_thermctl_set_trips()
689 if (trip->type != THERMAL_TRIP_HOT) in get_hot_trip_cb()
707 * tegra_soctherm_set_hwtrips() - set HW trip point from DT data
709 * @sg: pointer to the sensor group to set the thermtrip temperature for
718 * certain temperature.
737 int i, temperature, ret; in tegra_soctherm_set_hwtrips() local
740 temperature = tsensor_group_thermtrip_get(ts, sg->id); in tegra_soctherm_set_hwtrips()
741 if (min_low_temp == temperature) in tegra_soctherm_set_hwtrips()
742 if (thermal_zone_get_crit_temp(tz, &temperature)) in tegra_soctherm_set_hwtrips()
743 temperature = max_high_temp; in tegra_soctherm_set_hwtrips()
745 ret = thermtrip_program(dev, sg, temperature); in tegra_soctherm_set_hwtrips()
747 dev_err(dev, "thermtrip: %s: error during enable\n", sg->name); in tegra_soctherm_set_hwtrips()
752 sg->name, temperature); in tegra_soctherm_set_hwtrips()
756 dev_info(dev, "throttrip: %s: missing hot temperature\n", in tegra_soctherm_set_hwtrips()
757 sg->name); in tegra_soctherm_set_hwtrips()
764 if (!ts->throt_cfgs[i].init) in tegra_soctherm_set_hwtrips()
767 cdev = ts->throt_cfgs[i].cdev; in tegra_soctherm_set_hwtrips()
769 stc = find_throttle_cfg_by_name(ts, cdev->type); in tegra_soctherm_set_hwtrips()
773 ret = throttrip_program(dev, sg, stc, temperature); in tegra_soctherm_set_hwtrips()
776 sg->name); in tegra_soctherm_set_hwtrips()
782 sg->name, temperature); in tegra_soctherm_set_hwtrips()
788 sg->name); in tegra_soctherm_set_hwtrips()
804 * cause a new interrupt but this is taken care of by the re-reading of in soctherm_thermal_isr()
807 r = readl(ts->regs + THERMCTL_INTR_STATUS); in soctherm_thermal_isr()
808 writel(r, ts->regs + THERMCTL_INTR_DISABLE); in soctherm_thermal_isr()
814 * soctherm_thermal_isr_thread() - Handles a thermal interrupt request
825 * Disabled interrupts are re-enabled.
836 st = readl(ts->regs + THERMCTL_INTR_STATUS); in soctherm_thermal_isr_thread()
853 writel(ex, ts->regs + THERMCTL_INTR_STATUS); in soctherm_thermal_isr_thread()
857 tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_CPU]; in soctherm_thermal_isr_thread()
863 tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_GPU]; in soctherm_thermal_isr_thread()
869 tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_PLLX]; in soctherm_thermal_isr_thread()
875 tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_MEM]; in soctherm_thermal_isr_thread()
888 writel(st, ts->regs + THERMCTL_INTR_STATUS); in soctherm_thermal_isr_thread()
895 * soctherm_oc_intr_enable() - Enables the soctherm over-current interrupt
898 * @enable: Flag indicating enable the soctherm over-current
901 * Enables a specific over-current pins @alarm to raise an interrupt if the flag
913 r = readl(ts->regs + OC_INTR_ENABLE); in soctherm_oc_intr_enable()
931 writel(r, ts->regs + OC_INTR_ENABLE); in soctherm_oc_intr_enable()
935 * soctherm_handle_alarm() - Handles soctherm alarms
938 * "Handles" over-current alarms (OC1, OC2, OC3, and OC4) by printing
941 * Return: -EINVAL for @alarm = THROTTLE_OC3, otherwise 0 (success).
945 int rv = -EINVAL; in soctherm_handle_alarm()
980 * soctherm_edp_isr_thread() - log an over-current interrupt request
984 * Over-current events are handled in hardware. This function is called to log
986 * over-current interrupt registers for registers are set but
997 st = readl(ts->regs + OC_INTR_STATUS); in soctherm_edp_isr_thread()
1008 writel(st, ts->regs + OC_INTR_STATUS); in soctherm_edp_isr_thread()
1042 writel(st, ts->regs + OC_INTR_STATUS); in soctherm_edp_isr_thread()
1049 * soctherm_edp_isr() - Disables any active interrupts
1056 * handle asserted interrupts and subsequently unmask/re-enable them.
1071 r = readl(ts->regs + OC_INTR_STATUS); in soctherm_edp_isr()
1072 writel(r, ts->regs + OC_INTR_DISABLE); in soctherm_edp_isr()
1078 * soctherm_oc_irq_lock() - locks the over-current interrupt request
1081 * Looks up the chip data from @data and locks the mutex associated with
1082 * a particular over-current interrupt request.
1088 mutex_lock(&d->irq_lock); in soctherm_oc_irq_lock()
1092 * soctherm_oc_irq_sync_unlock() - Unlocks the OC interrupt request
1096 * with a particular over-current interrupt request.
1102 mutex_unlock(&d->irq_lock); in soctherm_oc_irq_sync_unlock()
1106 * soctherm_oc_irq_enable() - Enables the SOC_THERM over-current interrupt queue
1107 * @data: irq_data structure of the chip
1110 * to respond to over-current interrupts.
1117 d->irq_enable |= BIT(data->hwirq); in soctherm_oc_irq_enable()
1121 * soctherm_oc_irq_disable() - Disables overcurrent interrupt requests
1125 * interrupt request chip data.
1133 d->irq_enable &= ~BIT(data->hwirq); in soctherm_oc_irq_disable()
1142 * soctherm_oc_irq_map() - SOC_THERM interrupt request domain mapper
1161 struct soctherm_oc_irq_chip_data *data = h->host_data; in soctherm_oc_irq_map()
1164 irq_set_chip(virq, &data->irq_chip); in soctherm_oc_irq_map()
1170 * soctherm_irq_domain_xlate_twocell() - xlate for soctherm interrupts
1190 return -EINVAL; in soctherm_irq_domain_xlate_twocell()
1196 *out_hwirq = intspec[0] - 1; in soctherm_irq_domain_xlate_twocell()
1207 * soctherm_oc_int_init() - Initial enabling of the over
1212 * Sets the over current interrupt request chip data
1215 * -ENOMEM (out of memory), or irq_base if the function failed to
1243 return -ENOMEM; in soctherm_oc_int_init()
1253 struct platform_device *pdev = s->private; in regs_show()
1255 const struct tegra_tsensor *tsensors = ts->soc->tsensors; in regs_show()
1256 const struct tegra_tsensor_group **ttgs = ts->soc->ttgs; in regs_show()
1260 seq_puts(s, "-----TSENSE (convert HW)-----\n"); in regs_show()
1262 for (i = 0; i < ts->soc->num_tsensors; i++) { in regs_show()
1263 r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG1); in regs_show()
1281 r = readl(ts->regs + tsensors[i].base + SENSOR_STATUS1); in regs_show()
1287 r = readl(ts->regs + tsensors[i].base + SENSOR_STATUS0); in regs_show()
1293 r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG0); in regs_show()
1305 r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG2); in regs_show()
1312 r = readl(ts->regs + SENSOR_PDIV); in regs_show()
1315 r = readl(ts->regs + SENSOR_HOTSPOT_OFF); in regs_show()
1319 seq_puts(s, "-----SOC_THERM-----\n"); in regs_show()
1321 r = readl(ts->regs + SENSOR_TEMP1); in regs_show()
1326 r = readl(ts->regs + SENSOR_TEMP2); in regs_show()
1332 for (i = 0; i < ts->soc->num_ttgs; i++) { in regs_show()
1333 seq_printf(s, "%s:\n", ttgs[i]->name); in regs_show()
1337 u16 off = ttgs[i]->thermctl_lvl0_offset; in regs_show()
1339 r = readl(ts->regs + THERMCTL_LVL_REG(off, level)); in regs_show()
1341 mask = ttgs[i]->thermctl_lvl0_up_thresh_mask; in regs_show()
1343 v = sign_extend32(state, ts->soc->bptt - 1); in regs_show()
1344 v *= ts->soc->thresh_grain; in regs_show()
1347 mask = ttgs[i]->thermctl_lvl0_dn_thresh_mask; in regs_show()
1349 v = sign_extend32(state, ts->soc->bptt - 1); in regs_show()
1350 v *= ts->soc->thresh_grain; in regs_show()
1390 r = readl(ts->regs + THERMCTL_STATS_CTL); in regs_show()
1392 r & STATS_CTL_EN_UP ? "En" : "--", in regs_show()
1393 r & STATS_CTL_EN_DN ? "En" : "--"); in regs_show()
1399 r = readl(ts->regs + THERMCTL_LVL_REG(off, level)); in regs_show()
1403 r = readl(ts->regs + THERMCTL_LVL_REG(off, level)); in regs_show()
1407 r = readl(ts->regs + THERMCTL_THERMTRIP_CTL); in regs_show()
1408 state = REG_GET_MASK(r, ttgs[0]->thermtrip_any_en_mask); in regs_show()
1410 for (i = 0; i < ts->soc->num_ttgs; i++) { in regs_show()
1411 state = REG_GET_MASK(r, ttgs[i]->thermtrip_enable_mask); in regs_show()
1412 seq_printf(s, " %s En(%d) ", ttgs[i]->name, state); in regs_show()
1413 state = REG_GET_MASK(r, ttgs[i]->thermtrip_threshold_mask); in regs_show()
1414 state *= ts->soc->thresh_grain; in regs_show()
1418 r = readl(ts->regs + THROT_GLOBAL_CFG); in regs_show()
1422 seq_puts(s, "---------------------------------------------------\n"); in regs_show()
1423 r = readl(ts->regs + THROT_STATUS); in regs_show()
1431 r = readl(ts->regs + CPU_PSKIP_STATUS); in regs_show()
1432 if (ts->soc->use_ccroc) { in regs_show()
1456 tegra->debugfs_dir = root; in soctherm_debug_init()
1469 if (!tegra->clock_soctherm || !tegra->clock_tsensor) in soctherm_clk_enable()
1470 return -EINVAL; in soctherm_clk_enable()
1472 reset_control_assert(tegra->reset); in soctherm_clk_enable()
1475 err = clk_prepare_enable(tegra->clock_soctherm); in soctherm_clk_enable()
1477 reset_control_deassert(tegra->reset); in soctherm_clk_enable()
1481 err = clk_prepare_enable(tegra->clock_tsensor); in soctherm_clk_enable()
1483 clk_disable_unprepare(tegra->clock_soctherm); in soctherm_clk_enable()
1484 reset_control_deassert(tegra->reset); in soctherm_clk_enable()
1488 clk_disable_unprepare(tegra->clock_tsensor); in soctherm_clk_enable()
1489 clk_disable_unprepare(tegra->clock_soctherm); in soctherm_clk_enable()
1492 reset_control_deassert(tegra->reset); in soctherm_clk_enable()
1507 struct tegra_soctherm *ts = cdev->devdata; in throt_get_cdev_cur_state()
1510 r = readl(ts->regs + THROT_STATUS); in throt_get_cdev_cur_state()
1533 struct device *dev = &pdev->dev; in soctherm_thermtrips_parse()
1535 struct tsensor_group_thermtrips *tt = ts->soc->thermtrips; in soctherm_thermtrips_parse()
1536 const int max_num_prop = ts->soc->num_ttgs * 2; in soctherm_thermtrips_parse()
1541 return -ENOMEM; in soctherm_thermtrips_parse()
1543 n = of_property_count_u32_elems(dev->of_node, "nvidia,thermtrips"); in soctherm_thermtrips_parse()
1552 tlb = devm_kcalloc(&pdev->dev, max_num_prop, sizeof(u32), GFP_KERNEL); in soctherm_thermtrips_parse()
1554 return -ENOMEM; in soctherm_thermtrips_parse()
1555 ret = of_property_read_u32_array(dev->of_node, "nvidia,thermtrips", in soctherm_thermtrips_parse()
1581 if (of_property_read_bool(np_oc, "nvidia,polarity-active-low")) in soctherm_oc_cfg_parse()
1582 stc->oc_cfg.active_low = 1; in soctherm_oc_cfg_parse()
1584 stc->oc_cfg.active_low = 0; in soctherm_oc_cfg_parse()
1586 if (!of_property_read_u32(np_oc, "nvidia,count-threshold", &val)) { in soctherm_oc_cfg_parse()
1587 stc->oc_cfg.intr_en = 1; in soctherm_oc_cfg_parse()
1588 stc->oc_cfg.alarm_cnt_thresh = val; in soctherm_oc_cfg_parse()
1591 if (!of_property_read_u32(np_oc, "nvidia,throttle-period-us", &val)) in soctherm_oc_cfg_parse()
1592 stc->oc_cfg.throt_period = val; in soctherm_oc_cfg_parse()
1594 if (!of_property_read_u32(np_oc, "nvidia,alarm-filter", &val)) in soctherm_oc_cfg_parse()
1595 stc->oc_cfg.alarm_filter = val; in soctherm_oc_cfg_parse()
1598 stc->oc_cfg.mode = OC_THROTTLE_MODE_BRIEF; in soctherm_oc_cfg_parse()
1611 dev_err(dev, "throttle-cfg: %s: invalid priority\n", stc->name); in soctherm_throt_cfg_parse()
1612 return -EINVAL; in soctherm_throt_cfg_parse()
1614 stc->priority = val; in soctherm_throt_cfg_parse()
1616 ret = of_property_read_u32(np, ts->soc->use_ccroc ? in soctherm_throt_cfg_parse()
1617 "nvidia,cpu-throt-level" : in soctherm_throt_cfg_parse()
1618 "nvidia,cpu-throt-percent", &val); in soctherm_throt_cfg_parse()
1620 if (ts->soc->use_ccroc && in soctherm_throt_cfg_parse()
1622 stc->cpu_throt_level = val; in soctherm_throt_cfg_parse()
1623 else if (!ts->soc->use_ccroc && val <= 100) in soctherm_throt_cfg_parse()
1624 stc->cpu_throt_depth = val; in soctherm_throt_cfg_parse()
1631 ret = of_property_read_u32(np, "nvidia,gpu-throt-level", &val); in soctherm_throt_cfg_parse()
1633 stc->gpu_throt_level = val; in soctherm_throt_cfg_parse()
1640 dev_err(dev, "throttle-cfg: %s: no throt prop or invalid prop\n", in soctherm_throt_cfg_parse()
1641 stc->name); in soctherm_throt_cfg_parse()
1642 return -EINVAL; in soctherm_throt_cfg_parse()
1646 * soctherm_init_hw_throt_cdev() - Parse the HW throttle configurations
1652 struct device *dev = &pdev->dev; in soctherm_init_hw_throt_cdev()
1659 ts->throt_cfgs[i].name = throt_names[i]; in soctherm_init_hw_throt_cdev()
1660 ts->throt_cfgs[i].id = i; in soctherm_init_hw_throt_cdev()
1661 ts->throt_cfgs[i].init = false; in soctherm_init_hw_throt_cdev()
1664 np_stc = of_get_child_by_name(dev->of_node, "throttle-cfgs"); in soctherm_init_hw_throt_cdev()
1667 "throttle-cfg: no throttle-cfgs - not enabling\n"); in soctherm_init_hw_throt_cdev()
1676 name = np_stcc->name; in soctherm_init_hw_throt_cdev()
1680 "throttle-cfg: could not find %s\n", name); in soctherm_init_hw_throt_cdev()
1684 if (stc->init) { in soctherm_init_hw_throt_cdev()
1685 dev_err(dev, "throttle-cfg: %s: redefined!\n", name); in soctherm_init_hw_throt_cdev()
1694 if (stc->id >= THROTTLE_OC1) { in soctherm_init_hw_throt_cdev()
1696 stc->init = true; in soctherm_init_hw_throt_cdev()
1704 "throttle-cfg: %s: failed to register cooling device\n", in soctherm_init_hw_throt_cdev()
1708 stc->cdev = tcd; in soctherm_init_hw_throt_cdev()
1709 stc->init = true; in soctherm_init_hw_throt_cdev()
1718 * throttlectl_cpu_level_cfg() - programs CCROC NV_THERM level config
1722 * It's necessary to set up the CPU-local CCROC NV_THERM instance with
1725 * This function pre-programs the CCROC NV_THERM levels in terms of
1726 * pre-configured "Low", "Medium" or "Heavy" throttle levels which are
1766 * throttlectl_cpu_level_select() - program CPU pulse skipper config
1772 * data. This function is used on SoCs which have CPU-local pulse
1783 switch (ts->throt_cfgs[throt].cpu_throt_level) { in throttlectl_cpu_level_select()
1798 r = readl(ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU)); in throttlectl_cpu_level_select()
1802 writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU)); in throttlectl_cpu_level_select()
1806 writel(r, ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU)); in throttlectl_cpu_level_select()
1810 * throttlectl_cpu_mn() - program CPU pulse skipper configuration
1828 depth = ts->throt_cfgs[throt].cpu_throt_depth; in throttlectl_cpu_mn()
1831 r = readl(ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU)); in throttlectl_cpu_mn()
1835 writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU)); in throttlectl_cpu_mn()
1837 r = readl(ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU)); in throttlectl_cpu_mn()
1840 writel(r, ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU)); in throttlectl_cpu_mn()
1844 * throttlectl_gpu_level_select() - selects throttling level for GPU
1849 * pre-configured "Low", "Medium" or "Heavy" throttle levels.
1858 level = ts->throt_cfgs[throt].gpu_throt_level; in throttlectl_gpu_level_select()
1860 r = readl(ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_GPU)); in throttlectl_gpu_level_select()
1863 writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_GPU)); in throttlectl_gpu_level_select()
1870 struct soctherm_oc_cfg *oc = &ts->throt_cfgs[throt].oc_cfg; in soctherm_oc_cfg_program()
1872 if (oc->mode == OC_THROTTLE_MODE_DISABLED) in soctherm_oc_cfg_program()
1873 return -EINVAL; in soctherm_oc_cfg_program()
1876 r = REG_SET_MASK(r, OC1_CFG_THROTTLE_MODE_MASK, oc->mode); in soctherm_oc_cfg_program()
1877 r = REG_SET_MASK(r, OC1_CFG_ALARM_POLARITY_MASK, oc->active_low); in soctherm_oc_cfg_program()
1879 writel(r, ts->regs + ALARM_CFG(throt)); in soctherm_oc_cfg_program()
1880 writel(oc->throt_period, ts->regs + ALARM_THROTTLE_PERIOD(throt)); in soctherm_oc_cfg_program()
1881 writel(oc->alarm_cnt_thresh, ts->regs + ALARM_CNT_THRESHOLD(throt)); in soctherm_oc_cfg_program()
1882 writel(oc->alarm_filter, ts->regs + ALARM_FILTER(throt)); in soctherm_oc_cfg_program()
1883 soctherm_oc_intr_enable(ts, throt, oc->intr_en); in soctherm_oc_cfg_program()
1889 * soctherm_throttle_program() - programs pulse skippers' configuration
1900 struct soctherm_throt_cfg stc = ts->throt_cfgs[throt]; in soctherm_throttle_program()
1909 if (ts->soc->use_ccroc) in soctherm_throttle_program()
1917 writel(r, ts->regs + THROT_PRIORITY_CTRL(throt)); in soctherm_throttle_program()
1920 writel(r, ts->regs + THROT_DELAY_CTRL(throt)); in soctherm_throttle_program()
1922 r = readl(ts->regs + THROT_PRIORITY_LOCK); in soctherm_throttle_program()
1928 writel(r, ts->regs + THROT_PRIORITY_LOCK); in soctherm_throttle_program()
1938 if (ts->soc->use_ccroc) { in tegra_soctherm_throttle()
1949 if (ts->soc->use_ccroc) { in tegra_soctherm_throttle()
1956 writel(v, ts->regs + THROT_GLOBAL_CFG); in tegra_soctherm_throttle()
1958 v = readl(ts->clk_regs + CAR_SUPER_CCLKG_DIVIDER); in tegra_soctherm_throttle()
1960 writel(v, ts->clk_regs + CAR_SUPER_CCLKG_DIVIDER); in tegra_soctherm_throttle()
1966 writel(v, ts->regs + THERMCTL_STATS_CTL); in tegra_soctherm_throttle()
1972 struct device_node *np = pdev->dev.of_node; in soctherm_interrupts_init()
1977 dev_err(&pdev->dev, "soctherm_oc_int_init failed\n"); in soctherm_interrupts_init()
1981 tegra->thermal_irq = platform_get_irq(pdev, 0); in soctherm_interrupts_init()
1982 if (tegra->thermal_irq < 0) { in soctherm_interrupts_init()
1983 dev_dbg(&pdev->dev, "get 'thermal_irq' failed.\n"); in soctherm_interrupts_init()
1987 tegra->edp_irq = platform_get_irq(pdev, 1); in soctherm_interrupts_init()
1988 if (tegra->edp_irq < 0) { in soctherm_interrupts_init()
1989 dev_dbg(&pdev->dev, "get 'edp_irq' failed.\n"); in soctherm_interrupts_init()
1993 ret = devm_request_threaded_irq(&pdev->dev, in soctherm_interrupts_init()
1994 tegra->thermal_irq, in soctherm_interrupts_init()
1998 dev_name(&pdev->dev), in soctherm_interrupts_init()
2001 dev_err(&pdev->dev, "request_irq 'thermal_irq' failed.\n"); in soctherm_interrupts_init()
2005 ret = devm_request_threaded_irq(&pdev->dev, in soctherm_interrupts_init()
2006 tegra->edp_irq, in soctherm_interrupts_init()
2013 dev_err(&pdev->dev, "request_irq 'edp_irq' failed.\n"); in soctherm_interrupts_init()
2023 const struct tegra_tsensor_group **ttgs = tegra->soc->ttgs; in soctherm_init()
2028 for (i = 0; i < tegra->soc->num_tsensors; ++i) in soctherm_init()
2032 pdiv = readl(tegra->regs + SENSOR_PDIV); in soctherm_init()
2033 hotspot = readl(tegra->regs + SENSOR_HOTSPOT_OFF); in soctherm_init()
2034 for (i = 0; i < tegra->soc->num_ttgs; ++i) { in soctherm_init()
2035 pdiv = REG_SET_MASK(pdiv, ttgs[i]->pdiv_mask, in soctherm_init()
2036 ttgs[i]->pdiv); in soctherm_init()
2038 if (ttgs[i]->id == TEGRA124_SOCTHERM_SENSOR_PLLX) in soctherm_init()
2041 ttgs[i]->pllx_hotspot_mask, in soctherm_init()
2042 ttgs[i]->pllx_hotspot_diff); in soctherm_init()
2044 writel(pdiv, tegra->regs + SENSOR_PDIV); in soctherm_init()
2045 writel(hotspot, tegra->regs + SENSOR_HOTSPOT_OFF); in soctherm_init()
2048 tegra_soctherm_throttle(&pdev->dev); in soctherm_init()
2054 .compatible = "nvidia,tegra124-soctherm",
2060 .compatible = "nvidia,tegra132-soctherm",
2066 .compatible = "nvidia,tegra210-soctherm",
2084 match = of_match_node(tegra_soctherm_of_match, pdev->dev.of_node); in tegra_soctherm_probe()
2086 return -ENODEV; in tegra_soctherm_probe()
2088 soc = (struct tegra_soctherm_soc *)match->data; in tegra_soctherm_probe()
2089 if (soc->num_ttgs > TEGRA124_SOCTHERM_SENSOR_NUM) in tegra_soctherm_probe()
2090 return -EINVAL; in tegra_soctherm_probe()
2092 tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL); in tegra_soctherm_probe()
2094 return -ENOMEM; in tegra_soctherm_probe()
2096 mutex_init(&tegra->thermctl_lock); in tegra_soctherm_probe()
2097 dev_set_drvdata(&pdev->dev, tegra); in tegra_soctherm_probe()
2099 tegra->soc = soc; in tegra_soctherm_probe()
2101 tegra->regs = devm_platform_ioremap_resource_byname(pdev, "soctherm-reg"); in tegra_soctherm_probe()
2102 if (IS_ERR(tegra->regs)) { in tegra_soctherm_probe()
2103 dev_err(&pdev->dev, "can't get soctherm registers"); in tegra_soctherm_probe()
2104 return PTR_ERR(tegra->regs); in tegra_soctherm_probe()
2107 if (!tegra->soc->use_ccroc) { in tegra_soctherm_probe()
2108 tegra->clk_regs = devm_platform_ioremap_resource_byname(pdev, "car-reg"); in tegra_soctherm_probe()
2109 if (IS_ERR(tegra->clk_regs)) { in tegra_soctherm_probe()
2110 dev_err(&pdev->dev, "can't get car clk registers"); in tegra_soctherm_probe()
2111 return PTR_ERR(tegra->clk_regs); in tegra_soctherm_probe()
2114 tegra->ccroc_regs = devm_platform_ioremap_resource_byname(pdev, "ccroc-reg"); in tegra_soctherm_probe()
2115 if (IS_ERR(tegra->ccroc_regs)) { in tegra_soctherm_probe()
2116 dev_err(&pdev->dev, "can't get ccroc registers"); in tegra_soctherm_probe()
2117 return PTR_ERR(tegra->ccroc_regs); in tegra_soctherm_probe()
2121 tegra->reset = devm_reset_control_get(&pdev->dev, "soctherm"); in tegra_soctherm_probe()
2122 if (IS_ERR(tegra->reset)) { in tegra_soctherm_probe()
2123 dev_err(&pdev->dev, "can't get soctherm reset\n"); in tegra_soctherm_probe()
2124 return PTR_ERR(tegra->reset); in tegra_soctherm_probe()
2127 tegra->clock_tsensor = devm_clk_get(&pdev->dev, "tsensor"); in tegra_soctherm_probe()
2128 if (IS_ERR(tegra->clock_tsensor)) { in tegra_soctherm_probe()
2129 dev_err(&pdev->dev, "can't get tsensor clock\n"); in tegra_soctherm_probe()
2130 return PTR_ERR(tegra->clock_tsensor); in tegra_soctherm_probe()
2133 tegra->clock_soctherm = devm_clk_get(&pdev->dev, "soctherm"); in tegra_soctherm_probe()
2134 if (IS_ERR(tegra->clock_soctherm)) { in tegra_soctherm_probe()
2135 dev_err(&pdev->dev, "can't get soctherm clock\n"); in tegra_soctherm_probe()
2136 return PTR_ERR(tegra->clock_soctherm); in tegra_soctherm_probe()
2139 tegra->calib = devm_kcalloc(&pdev->dev, in tegra_soctherm_probe()
2140 soc->num_tsensors, sizeof(u32), in tegra_soctherm_probe()
2142 if (!tegra->calib) in tegra_soctherm_probe()
2143 return -ENOMEM; in tegra_soctherm_probe()
2146 err = tegra_calc_shared_calib(soc->tfuse, &shared_calib); in tegra_soctherm_probe()
2151 for (i = 0; i < soc->num_tsensors; ++i) { in tegra_soctherm_probe()
2152 err = tegra_calc_tsensor_calib(&soc->tsensors[i], in tegra_soctherm_probe()
2154 &tegra->calib[i]); in tegra_soctherm_probe()
2159 tegra->thermctl_tzs = devm_kcalloc(&pdev->dev, in tegra_soctherm_probe()
2160 soc->num_ttgs, sizeof(z), in tegra_soctherm_probe()
2162 if (!tegra->thermctl_tzs) in tegra_soctherm_probe()
2163 return -ENOMEM; in tegra_soctherm_probe()
2175 for (i = 0; i < soc->num_ttgs; ++i) { in tegra_soctherm_probe()
2177 devm_kzalloc(&pdev->dev, sizeof(*zone), GFP_KERNEL); in tegra_soctherm_probe()
2179 err = -ENOMEM; in tegra_soctherm_probe()
2183 zone->reg = tegra->regs + soc->ttgs[i]->sensor_temp_offset; in tegra_soctherm_probe()
2184 zone->dev = &pdev->dev; in tegra_soctherm_probe()
2185 zone->sg = soc->ttgs[i]; in tegra_soctherm_probe()
2186 zone->ts = tegra; in tegra_soctherm_probe()
2188 z = devm_thermal_of_zone_register(&pdev->dev, in tegra_soctherm_probe()
2189 soc->ttgs[i]->id, zone, in tegra_soctherm_probe()
2193 dev_err(&pdev->dev, "failed to register sensor: %d\n", in tegra_soctherm_probe()
2198 zone->tz = z; in tegra_soctherm_probe()
2199 tegra->thermctl_tzs[soc->ttgs[i]->id] = z; in tegra_soctherm_probe()
2202 err = tegra_soctherm_set_hwtrips(&pdev->dev, soc->ttgs[i], z); in tegra_soctherm_probe()
2223 debugfs_remove_recursive(tegra->debugfs_dir); in tegra_soctherm_remove()
2241 struct tegra_soctherm_soc *soc = tegra->soc; in soctherm_resume()
2246 dev_err(&pdev->dev, in soctherm_resume()
2253 for (i = 0; i < soc->num_ttgs; ++i) { in soctherm_resume()
2256 tz = tegra->thermctl_tzs[soc->ttgs[i]->id]; in soctherm_resume()
2257 err = tegra_soctherm_set_hwtrips(dev, soc->ttgs[i], tz); in soctherm_resume()
2259 dev_err(&pdev->dev, in soctherm_resume()