28 #define EXYNOS_TMU_REG_TRIMINFO		0x0
29 #define EXYNOS_TMU_REG_CONTROL		0x20
30 #define EXYNOS_TMU_REG_STATUS		0x28
31 #define EXYNOS_TMU_REG_CURRENT_TEMP	0x40
32 #define EXYNOS_TMU_REG_INTEN		0x70
33 #define EXYNOS_TMU_REG_INTSTAT		0x74
34 #define EXYNOS_TMU_REG_INTCLEAR		0x78
36 #define EXYNOS_TMU_TEMP_MASK		0xff
38 #define EXYNOS_TMU_REF_VOLTAGE_MASK	0x1f
39 #define EXYNOS_TMU_BUF_SLOPE_SEL_MASK	0xf
41 #define EXYNOS_TMU_CORE_EN_SHIFT	0
44 #define EXYNOS_TMU_TRIMINFO_CON1	0x10
47 #define EXYNOS4210_TMU_REG_THRESHOLD_TEMP	0x44
48 #define EXYNOS4210_TMU_REG_TRIG_LEVEL0	0x50
51 #define EXYNOS_TMU_TRIMINFO_CON2	0x14
52 #define EXYNOS_THD_TEMP_RISE		0x50
53 #define EXYNOS_THD_TEMP_FALL		0x54
54 #define EXYNOS_EMUL_CON		0x80
57 #define EXYNOS_TRIMINFO_25_SHIFT	0
60 #define EXYNOS_TMU_TRIP_MODE_MASK	0x7
63 #define EXYNOS_TMU_INTEN_RISE0_SHIFT	0
66 #define EXYNOS_EMUL_TIME	0x57F0
67 #define EXYNOS_EMUL_TIME_MASK	0xffff
70 #define EXYNOS_EMUL_DATA_MASK	0xFF
71 #define EXYNOS_EMUL_ENABLE	0x1
74 #define EXYNOS5260_TMU_REG_INTEN		0xC0
75 #define EXYNOS5260_TMU_REG_INTSTAT		0xC4
76 #define EXYNOS5260_TMU_REG_INTCLEAR		0xC8
77 #define EXYNOS5260_EMUL_CON			0x100
84 #define EXYNOS5433_THD_TEMP_RISE3_0		0x050
85 #define EXYNOS5433_THD_TEMP_RISE7_4		0x054
86 #define EXYNOS5433_THD_TEMP_FALL3_0		0x060
87 #define EXYNOS5433_THD_TEMP_FALL7_4		0x064
88 #define EXYNOS5433_TMU_REG_INTEN		0x0c0
89 #define EXYNOS5433_TMU_REG_INTPEND		0x0c8
90 #define EXYNOS5433_TMU_EMUL_CON			0x110
91 #define EXYNOS5433_TMU_PD_DET_EN		0x130
96 			(0xf << EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT)
99 #define EXYNOS5433_TRIMINFO_ONE_POINT_TRIMMING	0
104 #define EXYNOS5433_G3D_BASE			0x10070000
107 #define EXYNOS7_THD_TEMP_RISE7_6		0x50
108 #define EXYNOS7_THD_TEMP_FALL7_6		0x60
109 #define EXYNOS7_TMU_REG_INTEN			0x110
110 #define EXYNOS7_TMU_REG_INTPEND			0x118
111 #define EXYNOS7_TMU_REG_EMUL_CON		0x160
113 #define EXYNOS7_TMU_TEMP_MASK			0x1ff
115 #define EXYNOS7_TMU_INTEN_RISE0_SHIFT		0
117 #define EXYNOS7_EMUL_DATA_MASK			0x1ff
156  *	0 < gain <= 15
159  *	0 < reference_voltage <= 31
257 	int ret = 0;  in exynos_tmu_initialize()
290 			return 0;  in exynos_thermal_zone_configure()
305 	return 0;  in exynos_thermal_zone_configure()
414 	writeb(0, data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP);  in exynos4210_tmu_initialize()
419 	exynos_tmu_update_temp(data, EXYNOS_THD_TEMP_FALL, 0, temp);  in exynos4412_tmu_set_low_temp()
473 	exynos_tmu_update_temp(data, EXYNOS5433_THD_TEMP_FALL3_0, 0, temp);  in exynos5433_tmu_set_low_temp()
518 	dev_info(&pdev->dev, "Temperature sensor ID: 0x%x\n", sensor_id);  in exynos5433_tmu_initialize()
541 	exynos_tmu_update_temp(data, EXYNOS7_THD_TEMP_FALL7_6 + 12, 0, temp);  in exynos7_tmu_set_low_temp()
543 			      EXYNOS_TMU_INTEN_FALL0_SHIFT + 0, true);  in exynos7_tmu_set_low_temp()
556 			      EXYNOS_TMU_INTEN_FALL0_SHIFT + 0, false);  in exynos7_tmu_disable_low()
571 	exynos_tmu_update_temp(data, EXYNOS7_THD_TEMP_RISE7_6 + 0, 16, temp);  in exynos7_tmu_set_crit_temp()
612 	pd_det_en = on ? EXYNOS5433_PD_DET_EN : 0;  in exynos5433_tmu_control()
639 	int value, ret = 0;  in exynos_get_temp()
654 	if (value < 0)  in exynos_get_temp()
730 	return 0;  in exynos_tmu_set_emulation()
849 	data->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);  in exynos_map_dt_data()
850 	if (data->irq <= 0) {  in exynos_map_dt_data()
855 	if (of_address_to_resource(pdev->dev.of_node, 0, &res)) {  in exynos_map_dt_data()
856 		dev_err(&pdev->dev, "failed to get Resource 0\n");  in exynos_map_dt_data()
908 			data->min_efuse_value = 0;  in exynos_map_dt_data()
960 		return 0;  in exynos_map_dt_data()
974 	return 0;  in exynos_map_dt_data()
996 	return 0;  in exynos_set_trips()
1025 	case 0:  in exynos_tmu_probe()
1087 	data->tzd = devm_thermal_of_zone_register(dev, 0, data,  in exynos_tmu_probe()
1111 	return 0;  in exynos_tmu_probe()
1140 	return 0;  in exynos_tmu_suspend()
1150 	return 0;  in exynos_tmu_resume()