thermal/intel/intel_tcc.c

22  * The bitmask of TjMax is not included in this structure. It is always 0xff.
38 TCC_MODEL_TEMP_MASKS(nehalem, 0, 0x7f, 0x7f);
39 TCC_MODEL_TEMP_MASKS(haswell_x, 0xf, 0x7f, 0x7f);
40 TCC_MODEL_TEMP_MASKS(broadwell, 0x3f, 0x7f, 0x7f);
41 TCC_MODEL_TEMP_MASKS(goldmont, 0x7f, 0x7f, 0x7f);
42 TCC_MODEL_TEMP_MASKS(tigerlake, 0x3f, 0xff, 0xff);
43 TCC_MODEL_TEMP_MASKS(sapphirerapids, 0x3f, 0x7f, 0xff);
47 	.tcc_offset = 0x7f,
48 	.digital_readout = 0xff,
49 	.pkg_digital_readout = 0xff,
132 	return 0;  in intel_tcc_init()
144  * TEMPERATURE_TARGET register. If the mask is 0, it means the processor does
187 	if (cpu < 0)  in intel_tcc_get_tjmax()
194 	val = (low >> 16) & 0xff;  in intel_tcc_get_tjmax()
214 	if (cpu < 0)  in intel_tcc_get_offset()
233  * Return: On success returns 0, negative error code otherwise.
244 	if (offset < 0 || offset > intel_tcc_temp_masks.tcc_offset)  in intel_tcc_set_offset()
247 	if (cpu < 0)  in intel_tcc_set_offset()
261 	if (cpu < 0)  in intel_tcc_set_offset()
277  * Return: 0 on success, negative error code otherwise.
286 	if (tjmax < 0)  in intel_tcc_get_temp()
289 	if (cpu < 0)  in intel_tcc_get_temp()
304 	return 0;  in intel_tcc_get_temp()