22 #define PCH_THERMAL_DID_HSW_1	0x9C24 /* Haswell PCH */
23 #define PCH_THERMAL_DID_HSW_2	0x8C24 /* Haswell PCH */
24 #define PCH_THERMAL_DID_WPT	0x9CA4 /* Wildcat Point */
25 #define PCH_THERMAL_DID_SKL	0x9D31 /* Skylake PCH */
26 #define PCH_THERMAL_DID_SKL_H	0xA131 /* Skylake PCH 100 series */
27 #define PCH_THERMAL_DID_CNL	0x9Df9 /* CNL PCH */
28 #define PCH_THERMAL_DID_CNL_H	0xA379 /* CNL-H PCH */
29 #define PCH_THERMAL_DID_CNL_LP	0x02F9 /* CNL-LP PCH */
30 #define PCH_THERMAL_DID_CML_H	0X06F9 /* CML-H PCH */
31 #define PCH_THERMAL_DID_LWB	0xA1B1 /* Lewisburg PCH */
32 #define PCH_THERMAL_DID_WBG	0x8D24 /* Wellsburg PCH */
35 #define WPT_TEMP	0x0000	/* Temperature */
36 #define WPT_TSC	0x04	/* Thermal Sensor Control */
37 #define WPT_TSS	0x06	/* Thermal Sensor Status */
38 #define WPT_TSEL	0x08	/* Thermal Sensor Enable and Lock */
39 #define WPT_TSREL	0x0A	/* Thermal Sensor Report Enable and Lock */
40 #define WPT_TSMIC	0x0C	/* Thermal Sensor SMI Control */
41 #define WPT_CTT	0x0010	/* Catastrophic Trip Point */
42 #define WPT_TSPM	0x001C	/* Thermal Sensor Power Management */
43 #define WPT_TAHV	0x0014	/* Thermal Alert High Value */
44 #define WPT_TALV	0x0018	/* Thermal Alert Low Value */
45 #define WPT_TL		0x00000040	/* Throttle Value */
46 #define WPT_PHL	0x0060	/* PCH Hot Level */
47 #define WPT_PHLC	0x62	/* PHL Control */
48 #define WPT_TAS	0x80	/* Thermal Alert Status */
49 #define WPT_TSPIEN	0x82	/* PCI Interrupt Event Enables */
50 #define WPT_TSGPEN	0x84	/* General Purpose Event Enables */
53 #define WPT_TEMP_TSR	0x01ff	/* Temp TS Reading */
54 #define WPT_TSC_CPDE	0x01	/* Catastrophic Power-Down Enable */
55 #define WPT_TSS_TSDSS	0x10	/* Thermal Sensor Dynamic Shutdown Status */
56 #define WPT_TSS_GPES	0x08	/* GPE status */
57 #define WPT_TSEL_ETS	0x01    /* Enable TS */
58 #define WPT_TSEL_PLDB	0x80	/* TSEL Policy Lock-Down Bit */
59 #define WPT_TL_TOL	0x000001FF	/* T0 Level */
60 #define WPT_TL_T1L	0x1ff00000	/* T1 Level */
61 #define WPT_TL_TTEN	0x20000000	/* TT Enable */
104 		return 0;  in pch_wpt_add_acpi_psv_trip()
106 	if (thermal_acpi_passive_trip_temp(adev, &temp) || temp <= 0)  in pch_wpt_add_acpi_psv_trip()
107 		return 0;  in pch_wpt_add_acpi_psv_trip()
117 	return 0;  in pch_wpt_add_acpi_psv_trip()
126 	return 0;  in pch_thermal_get_temp()
141 	PCH_BOARD_HSW = 0,
163 	struct thermal_trip ptd_trips[PCH_MAX_TRIPS] = { 0 };  in intel_pch_thermal_probe()
166 	int nr_trips = 0;  in intel_pch_thermal_probe()
190 	ptd->hw_base = pci_ioremap_bar(pdev, 0);  in intel_pch_thermal_probe()
223 	trip_temp &= 0x1FF;  in intel_pch_thermal_probe()
230 	trip_temp &= 0x1FF;  in intel_pch_thermal_probe()
241 							   NULL, 0, 0);  in intel_pch_thermal_probe()
252 	return 0;  in intel_pch_thermal_probe()
281 	int pch_delay_cnt = 0;  in intel_pch_thermal_suspend_noirq()
287 		writeb(tsel & 0xFE, ptd->hw_base + WPT_TSEL);  in intel_pch_thermal_suspend_noirq()
288 		return 0;  in intel_pch_thermal_suspend_noirq()
293 		return 0;  in intel_pch_thermal_suspend_noirq()
320 			return 0;  in intel_pch_thermal_suspend_noirq()
347 	return 0;  in intel_pch_thermal_suspend_noirq()
356 		return 0;  in intel_pch_thermal_resume()
362 	return 0;  in intel_pch_thermal_resume()
388 	{ 0, },