Lines Matching full:qspi
3 * TI QSPI driver
126 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi, in ti_qspi_read() argument
129 return readl(qspi->base + reg); in ti_qspi_read()
132 static inline void ti_qspi_write(struct ti_qspi *qspi, in ti_qspi_write() argument
135 writel(val, qspi->base + reg); in ti_qspi_write()
140 struct ti_qspi *qspi = spi_controller_get_devdata(spi->controller); in ti_qspi_setup() local
144 dev_dbg(qspi->dev, "host busy doing other transfers\n"); in ti_qspi_setup()
148 if (!qspi->host->max_speed_hz) { in ti_qspi_setup()
149 dev_err(qspi->dev, "spi max frequency not defined\n"); in ti_qspi_setup()
153 spi->max_speed_hz = min(spi->max_speed_hz, qspi->host->max_speed_hz); in ti_qspi_setup()
155 ret = pm_runtime_resume_and_get(qspi->dev); in ti_qspi_setup()
157 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n"); in ti_qspi_setup()
161 pm_runtime_mark_last_busy(qspi->dev); in ti_qspi_setup()
162 ret = pm_runtime_put_autosuspend(qspi->dev); in ti_qspi_setup()
164 dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n"); in ti_qspi_setup()
171 static void ti_qspi_setup_clk(struct ti_qspi *qspi, u32 speed_hz) in ti_qspi_setup_clk() argument
173 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg; in ti_qspi_setup_clk()
177 clk_rate = clk_get_rate(qspi->fclk); in ti_qspi_setup_clk()
180 dev_dbg(qspi->dev, "hz: %d, clock divider %d\n", speed_hz, clk_div); in ti_qspi_setup_clk()
182 pm_runtime_resume_and_get(qspi->dev); in ti_qspi_setup_clk()
186 clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG); in ti_qspi_setup_clk()
191 ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG); in ti_qspi_setup_clk()
194 ti_qspi_write(qspi, clk_ctrl_new, QSPI_SPI_CLOCK_CNTRL_REG); in ti_qspi_setup_clk()
198 pm_runtime_mark_last_busy(qspi->dev); in ti_qspi_setup_clk()
199 pm_runtime_put_autosuspend(qspi->dev); in ti_qspi_setup_clk()
202 static void ti_qspi_restore_ctx(struct ti_qspi *qspi) in ti_qspi_restore_ctx() argument
204 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg; in ti_qspi_restore_ctx()
206 ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG); in ti_qspi_restore_ctx()
209 static inline u32 qspi_is_busy(struct ti_qspi *qspi) in qspi_is_busy() argument
214 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG); in qspi_is_busy()
217 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG); in qspi_is_busy()
220 WARN(stat & BUSY, "qspi busy\n"); in qspi_is_busy()
224 static inline int ti_qspi_poll_wc(struct ti_qspi *qspi) in ti_qspi_poll_wc() argument
230 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG); in ti_qspi_poll_wc()
236 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG); in ti_qspi_poll_wc()
242 static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t, in qspi_write_msg() argument
251 cmd = qspi->cmd | QSPI_WR_SNGL; in qspi_write_msg()
256 if (qspi_is_busy(qspi)) in qspi_write_msg()
261 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n", in qspi_write_msg()
262 cmd, qspi->dc, *txbuf); in qspi_write_msg()
267 writel(data, qspi->base + in qspi_write_msg()
270 writel(data, qspi->base + in qspi_write_msg()
273 writel(data, qspi->base + in qspi_write_msg()
276 writel(data, qspi->base + in qspi_write_msg()
281 writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG); in qspi_write_msg()
282 cmd = qspi->cmd | QSPI_WR_SNGL; in qspi_write_msg()
288 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n", in qspi_write_msg()
289 cmd, qspi->dc, *txbuf); in qspi_write_msg()
290 writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG); in qspi_write_msg()
293 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n", in qspi_write_msg()
294 cmd, qspi->dc, *txbuf); in qspi_write_msg()
295 writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG); in qspi_write_msg()
299 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG); in qspi_write_msg()
300 if (ti_qspi_poll_wc(qspi)) { in qspi_write_msg()
301 dev_err(qspi->dev, "write timed out\n"); in qspi_write_msg()
311 static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t, in qspi_read_msg() argument
321 cmd = qspi->cmd; in qspi_read_msg()
337 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc); in qspi_read_msg()
338 if (qspi_is_busy(qspi)) in qspi_read_msg()
361 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG); in qspi_read_msg()
362 if (ti_qspi_poll_wc(qspi)) { in qspi_read_msg()
363 dev_err(qspi->dev, "read timed out\n"); in qspi_read_msg()
375 rx = readl(qspi->base + QSPI_SPI_DATA_REG_3); in qspi_read_msg()
377 rx = readl(qspi->base + QSPI_SPI_DATA_REG_2); in qspi_read_msg()
379 rx = readl(qspi->base + QSPI_SPI_DATA_REG_1); in qspi_read_msg()
381 rx = readl(qspi->base + QSPI_SPI_DATA_REG); in qspi_read_msg()
385 rx = readl(qspi->base + QSPI_SPI_DATA_REG); in qspi_read_msg()
397 *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG); in qspi_read_msg()
400 *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG); in qspi_read_msg()
410 static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t, in qspi_transfer_msg() argument
416 ret = qspi_write_msg(qspi, t, count); in qspi_transfer_msg()
418 dev_dbg(qspi->dev, "Error while writing\n"); in qspi_transfer_msg()
424 ret = qspi_read_msg(qspi, t, count); in qspi_transfer_msg()
426 dev_dbg(qspi->dev, "Error while reading\n"); in qspi_transfer_msg()
436 struct ti_qspi *qspi = param; in ti_qspi_dma_callback() local
438 complete(&qspi->transfer_complete); in ti_qspi_dma_callback()
441 static int ti_qspi_dma_xfer(struct ti_qspi *qspi, dma_addr_t dma_dst, in ti_qspi_dma_xfer() argument
444 struct dma_chan *chan = qspi->rx_chan; in ti_qspi_dma_xfer()
453 dev_err(qspi->dev, "device_prep_dma_memcpy error\n"); in ti_qspi_dma_xfer()
458 tx->callback_param = qspi; in ti_qspi_dma_xfer()
460 reinit_completion(&qspi->transfer_complete); in ti_qspi_dma_xfer()
464 dev_err(qspi->dev, "dma_submit_error %d\n", cookie); in ti_qspi_dma_xfer()
469 time_left = wait_for_completion_timeout(&qspi->transfer_complete, in ti_qspi_dma_xfer()
473 dev_err(qspi->dev, "DMA wait_for_completion_timeout\n"); in ti_qspi_dma_xfer()
480 static int ti_qspi_dma_bounce_buffer(struct ti_qspi *qspi, loff_t offs, in ti_qspi_dma_bounce_buffer() argument
483 dma_addr_t dma_src = qspi->mmap_phys_base + offs; in ti_qspi_dma_bounce_buffer()
494 ret = ti_qspi_dma_xfer(qspi, qspi->rx_bb_dma_addr, in ti_qspi_dma_bounce_buffer()
498 memcpy(to, qspi->rx_bb_addr, xfer_len); in ti_qspi_dma_bounce_buffer()
507 static int ti_qspi_dma_xfer_sg(struct ti_qspi *qspi, struct sg_table rx_sg, in ti_qspi_dma_xfer_sg() argument
511 dma_addr_t dma_src = qspi->mmap_phys_base + from; in ti_qspi_dma_xfer_sg()
518 ret = ti_qspi_dma_xfer(qspi, dma_dst, dma_src, len); in ti_qspi_dma_xfer_sg()
529 struct ti_qspi *qspi = spi_controller_get_devdata(spi->controller); in ti_qspi_enable_memory_map() local
531 ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG); in ti_qspi_enable_memory_map()
532 if (qspi->ctrl_base) { in ti_qspi_enable_memory_map()
533 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg, in ti_qspi_enable_memory_map()
537 qspi->mmap_enabled = true; in ti_qspi_enable_memory_map()
538 qspi->current_cs = spi_get_chipselect(spi, 0); in ti_qspi_enable_memory_map()
543 struct ti_qspi *qspi = spi_controller_get_devdata(spi->controller); in ti_qspi_disable_memory_map() local
545 ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG); in ti_qspi_disable_memory_map()
546 if (qspi->ctrl_base) in ti_qspi_disable_memory_map()
547 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg, in ti_qspi_disable_memory_map()
549 qspi->mmap_enabled = false; in ti_qspi_disable_memory_map()
550 qspi->current_cs = -1; in ti_qspi_disable_memory_map()
557 struct ti_qspi *qspi = spi_controller_get_devdata(spi->controller); in ti_qspi_setup_mmap_read() local
573 ti_qspi_write(qspi, memval, in ti_qspi_setup_mmap_read()
579 struct ti_qspi *qspi = spi_controller_get_devdata(mem->spi->controller); in ti_qspi_adjust_op_size() local
583 if (op->addr.val < qspi->mmap_size) { in ti_qspi_adjust_op_size()
585 if (op->addr.val + op->data.nbytes > qspi->mmap_size) { in ti_qspi_adjust_op_size()
586 max_len = qspi->mmap_size - op->addr.val; in ti_qspi_adjust_op_size()
594 * Adjust size to comply with the QSPI max frame length. in ti_qspi_adjust_op_size()
609 struct ti_qspi *qspi = spi_controller_get_devdata(mem->spi->controller); in ti_qspi_exec_mem_op() local
620 if (from + op->data.nbytes > qspi->mmap_size) in ti_qspi_exec_mem_op()
623 mutex_lock(&qspi->list_lock); in ti_qspi_exec_mem_op()
625 if (!qspi->mmap_enabled || qspi->current_cs != spi_get_chipselect(mem->spi, 0)) { in ti_qspi_exec_mem_op()
626 ti_qspi_setup_clk(qspi, mem->spi->max_speed_hz); in ti_qspi_exec_mem_op()
632 if (qspi->rx_chan) { in ti_qspi_exec_mem_op()
638 ret = ti_qspi_dma_xfer_sg(qspi, sgt, from); in ti_qspi_exec_mem_op()
642 ret = ti_qspi_dma_bounce_buffer(qspi, from, in ti_qspi_exec_mem_op()
647 memcpy_fromio(op->data.buf.in, qspi->mmap_base + from, in ti_qspi_exec_mem_op()
651 mutex_unlock(&qspi->list_lock); in ti_qspi_exec_mem_op()
664 struct ti_qspi *qspi = spi_controller_get_devdata(host); in ti_qspi_start_transfer_one() local
672 qspi->dc = 0; in ti_qspi_start_transfer_one()
675 qspi->dc |= QSPI_CKPHA(spi_get_chipselect(spi, 0)); in ti_qspi_start_transfer_one()
677 qspi->dc |= QSPI_CKPOL(spi_get_chipselect(spi, 0)); in ti_qspi_start_transfer_one()
679 qspi->dc |= QSPI_CSPOL(spi_get_chipselect(spi, 0)); in ti_qspi_start_transfer_one()
687 qspi->cmd = 0; in ti_qspi_start_transfer_one()
688 qspi->cmd |= QSPI_EN_CS(spi_get_chipselect(spi, 0)); in ti_qspi_start_transfer_one()
689 qspi->cmd |= QSPI_FLEN(frame_len_words); in ti_qspi_start_transfer_one()
691 ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG); in ti_qspi_start_transfer_one()
693 mutex_lock(&qspi->list_lock); in ti_qspi_start_transfer_one()
695 if (qspi->mmap_enabled) in ti_qspi_start_transfer_one()
699 qspi->cmd = ((qspi->cmd & ~QSPI_WLEN_MASK) | in ti_qspi_start_transfer_one()
705 ti_qspi_setup_clk(qspi, t->speed_hz); in ti_qspi_start_transfer_one()
706 ret = qspi_transfer_msg(qspi, t, transfer_len_words * wlen); in ti_qspi_start_transfer_one()
708 dev_dbg(qspi->dev, "transfer message failed\n"); in ti_qspi_start_transfer_one()
709 mutex_unlock(&qspi->list_lock); in ti_qspi_start_transfer_one()
719 mutex_unlock(&qspi->list_lock); in ti_qspi_start_transfer_one()
721 ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG); in ti_qspi_start_transfer_one()
730 struct ti_qspi *qspi; in ti_qspi_runtime_resume() local
732 qspi = dev_get_drvdata(dev); in ti_qspi_runtime_resume()
733 ti_qspi_restore_ctx(qspi); in ti_qspi_runtime_resume()
738 static void ti_qspi_dma_cleanup(struct ti_qspi *qspi) in ti_qspi_dma_cleanup() argument
740 if (qspi->rx_bb_addr) in ti_qspi_dma_cleanup()
741 dma_free_coherent(qspi->dev, QSPI_DMA_BUFFER_SIZE, in ti_qspi_dma_cleanup()
742 qspi->rx_bb_addr, in ti_qspi_dma_cleanup()
743 qspi->rx_bb_dma_addr); in ti_qspi_dma_cleanup()
745 if (qspi->rx_chan) in ti_qspi_dma_cleanup()
746 dma_release_channel(qspi->rx_chan); in ti_qspi_dma_cleanup()
750 {.compatible = "ti,dra7xxx-qspi" },
751 {.compatible = "ti,am4372-qspi" },
758 struct ti_qspi *qspi; in ti_qspi_probe() local
766 host = spi_alloc_host(&pdev->dev, sizeof(*qspi)); in ti_qspi_probe()
784 qspi = spi_controller_get_devdata(host); in ti_qspi_probe()
785 qspi->host = host; in ti_qspi_probe()
786 qspi->dev = &pdev->dev; in ti_qspi_probe()
787 platform_set_drvdata(pdev, qspi); in ti_qspi_probe()
810 qspi->mmap_size = resource_size(res_mmap); in ti_qspi_probe()
818 mutex_init(&qspi->list_lock); in ti_qspi_probe()
820 qspi->base = devm_ioremap_resource(&pdev->dev, r); in ti_qspi_probe()
821 if (IS_ERR(qspi->base)) { in ti_qspi_probe()
822 ret = PTR_ERR(qspi->base); in ti_qspi_probe()
828 qspi->ctrl_base = in ti_qspi_probe()
831 if (IS_ERR(qspi->ctrl_base)) { in ti_qspi_probe()
832 ret = PTR_ERR(qspi->ctrl_base); in ti_qspi_probe()
837 1, &qspi->ctrl_reg); in ti_qspi_probe()
845 qspi->fclk = devm_clk_get(&pdev->dev, "fck"); in ti_qspi_probe()
846 if (IS_ERR(qspi->fclk)) { in ti_qspi_probe()
847 ret = PTR_ERR(qspi->fclk); in ti_qspi_probe()
861 qspi->rx_chan = dma_request_chan_by_mask(&mask); in ti_qspi_probe()
862 if (IS_ERR(qspi->rx_chan)) { in ti_qspi_probe()
863 dev_err(qspi->dev, in ti_qspi_probe()
865 qspi->rx_chan = NULL; in ti_qspi_probe()
869 qspi->rx_bb_addr = dma_alloc_coherent(qspi->dev, in ti_qspi_probe()
871 &qspi->rx_bb_dma_addr, in ti_qspi_probe()
873 if (!qspi->rx_bb_addr) { in ti_qspi_probe()
874 dev_err(qspi->dev, in ti_qspi_probe()
876 dma_release_channel(qspi->rx_chan); in ti_qspi_probe()
879 host->dma_rx = qspi->rx_chan; in ti_qspi_probe()
880 init_completion(&qspi->transfer_complete); in ti_qspi_probe()
882 qspi->mmap_phys_base = (dma_addr_t)res_mmap->start; in ti_qspi_probe()
885 if (!qspi->rx_chan && res_mmap) { in ti_qspi_probe()
886 qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap); in ti_qspi_probe()
887 if (IS_ERR(qspi->mmap_base)) { in ti_qspi_probe()
890 PTR_ERR(qspi->mmap_base)); in ti_qspi_probe()
891 qspi->mmap_base = NULL; in ti_qspi_probe()
895 qspi->mmap_enabled = false; in ti_qspi_probe()
896 qspi->current_cs = -1; in ti_qspi_probe()
902 ti_qspi_dma_cleanup(qspi); in ti_qspi_probe()
912 struct ti_qspi *qspi = platform_get_drvdata(pdev); in ti_qspi_remove() local
915 rc = spi_controller_suspend(qspi->host); in ti_qspi_remove()
925 ti_qspi_dma_cleanup(qspi); in ti_qspi_remove()
936 .name = "ti-qspi",
946 MODULE_DESCRIPTION("TI QSPI controller driver");
947 MODULE_ALIAS("platform:ti-qspi");