Lines Matching +full:tegra20 +full:- +full:slink
1 // SPDX-License-Identifier: GPL-2.0-only
3 * SPI driver for Nvidia's Tegra20/Tegra30 SLINK Controller.
12 #include <linux/dma-mapping.h>
212 return readl(tspi->base + reg); in tegra_slink_readl()
218 writel(val, tspi->base + reg); in tegra_slink_writel()
222 readl(tspi->base + SLINK_MAS_DATA); in tegra_slink_writel()
239 switch (tspi->bytes_per_word) { in tegra_slink_get_packed_size()
257 unsigned remain_len = t->len - tspi->cur_pos; in tegra_slink_calculate_curr_xfer_param()
263 bits_per_word = t->bits_per_word; in tegra_slink_calculate_curr_xfer_param()
264 tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8); in tegra_slink_calculate_curr_xfer_param()
267 tspi->is_packed = true; in tegra_slink_calculate_curr_xfer_param()
268 tspi->words_per_32bit = 32/bits_per_word; in tegra_slink_calculate_curr_xfer_param()
270 tspi->is_packed = false; in tegra_slink_calculate_curr_xfer_param()
271 tspi->words_per_32bit = 1; in tegra_slink_calculate_curr_xfer_param()
273 tspi->packed_size = tegra_slink_get_packed_size(tspi, t); in tegra_slink_calculate_curr_xfer_param()
275 if (tspi->is_packed) { in tegra_slink_calculate_curr_xfer_param()
276 max_len = min(remain_len, tspi->max_buf_size); in tegra_slink_calculate_curr_xfer_param()
277 tspi->curr_dma_words = max_len/tspi->bytes_per_word; in tegra_slink_calculate_curr_xfer_param()
280 max_word = (remain_len - 1) / tspi->bytes_per_word + 1; in tegra_slink_calculate_curr_xfer_param()
281 max_word = min(max_word, tspi->max_buf_size/4); in tegra_slink_calculate_curr_xfer_param()
282 tspi->curr_dma_words = max_word; in tegra_slink_calculate_curr_xfer_param()
298 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos; in tegra_slink_fill_tx_fifo_from_client_txbuf()
303 if (tspi->is_packed) { in tegra_slink_fill_tx_fifo_from_client_txbuf()
304 fifo_words_left = tx_empty_count * tspi->words_per_32bit; in tegra_slink_fill_tx_fifo_from_client_txbuf()
305 written_words = min(fifo_words_left, tspi->curr_dma_words); in tegra_slink_fill_tx_fifo_from_client_txbuf()
306 nbytes = written_words * tspi->bytes_per_word; in tegra_slink_fill_tx_fifo_from_client_txbuf()
310 for (i = 0; (i < 4) && nbytes; i++, nbytes--) in tegra_slink_fill_tx_fifo_from_client_txbuf()
315 max_n_32bit = min(tspi->curr_dma_words, tx_empty_count); in tegra_slink_fill_tx_fifo_from_client_txbuf()
317 nbytes = written_words * tspi->bytes_per_word; in tegra_slink_fill_tx_fifo_from_client_txbuf()
320 for (i = 0; nbytes && (i < tspi->bytes_per_word); in tegra_slink_fill_tx_fifo_from_client_txbuf()
321 i++, nbytes--) in tegra_slink_fill_tx_fifo_from_client_txbuf()
326 tspi->cur_tx_pos += written_words * tspi->bytes_per_word; in tegra_slink_fill_tx_fifo_from_client_txbuf()
338 u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos; in tegra_slink_read_rx_fifo_to_client_rxbuf()
342 if (tspi->is_packed) { in tegra_slink_read_rx_fifo_to_client_rxbuf()
343 len = tspi->curr_dma_words * tspi->bytes_per_word; in tegra_slink_read_rx_fifo_to_client_rxbuf()
346 for (i = 0; len && (i < 4); i++, len--) in tegra_slink_read_rx_fifo_to_client_rxbuf()
349 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word; in tegra_slink_read_rx_fifo_to_client_rxbuf()
350 read_words += tspi->curr_dma_words; in tegra_slink_read_rx_fifo_to_client_rxbuf()
354 for (i = 0; (i < tspi->bytes_per_word); i++) in tegra_slink_read_rx_fifo_to_client_rxbuf()
357 tspi->cur_rx_pos += rx_full_count * tspi->bytes_per_word; in tegra_slink_read_rx_fifo_to_client_rxbuf()
367 dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys, in tegra_slink_copy_client_txbuf_to_spi_txbuf()
368 tspi->dma_buf_size, DMA_TO_DEVICE); in tegra_slink_copy_client_txbuf_to_spi_txbuf()
370 if (tspi->is_packed) { in tegra_slink_copy_client_txbuf_to_spi_txbuf()
371 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word; in tegra_slink_copy_client_txbuf_to_spi_txbuf()
372 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len); in tegra_slink_copy_client_txbuf_to_spi_txbuf()
376 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos; in tegra_slink_copy_client_txbuf_to_spi_txbuf()
377 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word; in tegra_slink_copy_client_txbuf_to_spi_txbuf()
379 for (count = 0; count < tspi->curr_dma_words; count++) { in tegra_slink_copy_client_txbuf_to_spi_txbuf()
381 for (i = 0; consume && (i < tspi->bytes_per_word); in tegra_slink_copy_client_txbuf_to_spi_txbuf()
382 i++, consume--) in tegra_slink_copy_client_txbuf_to_spi_txbuf()
384 tspi->tx_dma_buf[count] = x; in tegra_slink_copy_client_txbuf_to_spi_txbuf()
387 tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word; in tegra_slink_copy_client_txbuf_to_spi_txbuf()
390 dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys, in tegra_slink_copy_client_txbuf_to_spi_txbuf()
391 tspi->dma_buf_size, DMA_TO_DEVICE); in tegra_slink_copy_client_txbuf_to_spi_txbuf()
400 dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys, in tegra_slink_copy_spi_rxbuf_to_client_rxbuf()
401 tspi->dma_buf_size, DMA_FROM_DEVICE); in tegra_slink_copy_spi_rxbuf_to_client_rxbuf()
403 if (tspi->is_packed) { in tegra_slink_copy_spi_rxbuf_to_client_rxbuf()
404 len = tspi->curr_dma_words * tspi->bytes_per_word; in tegra_slink_copy_spi_rxbuf_to_client_rxbuf()
405 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len); in tegra_slink_copy_spi_rxbuf_to_client_rxbuf()
409 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos; in tegra_slink_copy_spi_rxbuf_to_client_rxbuf()
410 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1; in tegra_slink_copy_spi_rxbuf_to_client_rxbuf()
412 for (count = 0; count < tspi->curr_dma_words; count++) { in tegra_slink_copy_spi_rxbuf_to_client_rxbuf()
413 u32 x = tspi->rx_dma_buf[count] & rx_mask; in tegra_slink_copy_spi_rxbuf_to_client_rxbuf()
414 for (i = 0; (i < tspi->bytes_per_word); i++) in tegra_slink_copy_spi_rxbuf_to_client_rxbuf()
418 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word; in tegra_slink_copy_spi_rxbuf_to_client_rxbuf()
421 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys, in tegra_slink_copy_spi_rxbuf_to_client_rxbuf()
422 tspi->dma_buf_size, DMA_FROM_DEVICE); in tegra_slink_copy_spi_rxbuf_to_client_rxbuf()
434 reinit_completion(&tspi->tx_dma_complete); in tegra_slink_start_tx_dma()
435 tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan, in tegra_slink_start_tx_dma()
436 tspi->tx_dma_phys, len, DMA_MEM_TO_DEV, in tegra_slink_start_tx_dma()
438 if (!tspi->tx_dma_desc) { in tegra_slink_start_tx_dma()
439 dev_err(tspi->dev, "Not able to get desc for Tx\n"); in tegra_slink_start_tx_dma()
440 return -EIO; in tegra_slink_start_tx_dma()
443 tspi->tx_dma_desc->callback = tegra_slink_dma_complete; in tegra_slink_start_tx_dma()
444 tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete; in tegra_slink_start_tx_dma()
446 dmaengine_submit(tspi->tx_dma_desc); in tegra_slink_start_tx_dma()
447 dma_async_issue_pending(tspi->tx_dma_chan); in tegra_slink_start_tx_dma()
453 reinit_completion(&tspi->rx_dma_complete); in tegra_slink_start_rx_dma()
454 tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan, in tegra_slink_start_rx_dma()
455 tspi->rx_dma_phys, len, DMA_DEV_TO_MEM, in tegra_slink_start_rx_dma()
457 if (!tspi->rx_dma_desc) { in tegra_slink_start_rx_dma()
458 dev_err(tspi->dev, "Not able to get desc for Rx\n"); in tegra_slink_start_rx_dma()
459 return -EIO; in tegra_slink_start_rx_dma()
462 tspi->rx_dma_desc->callback = tegra_slink_dma_complete; in tegra_slink_start_rx_dma()
463 tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete; in tegra_slink_start_rx_dma()
465 dmaengine_submit(tspi->rx_dma_desc); in tegra_slink_start_rx_dma()
466 dma_async_issue_pending(tspi->rx_dma_chan); in tegra_slink_start_rx_dma()
481 dev_err(tspi->dev, "Rx/Tx fifo are not empty status 0x%08x\n", in tegra_slink_start_dma_based_transfer()
483 return -EIO; in tegra_slink_start_dma_based_transfer()
486 val = SLINK_DMA_BLOCK_SIZE(tspi->curr_dma_words - 1); in tegra_slink_start_dma_based_transfer()
487 val |= tspi->packed_size; in tegra_slink_start_dma_based_transfer()
488 if (tspi->is_packed) in tegra_slink_start_dma_based_transfer()
489 len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word, in tegra_slink_start_dma_based_transfer()
492 len = tspi->curr_dma_words * 4; in tegra_slink_start_dma_based_transfer()
502 if (tspi->cur_direction & DATA_DIR_TX) in tegra_slink_start_dma_based_transfer()
505 if (tspi->cur_direction & DATA_DIR_RX) in tegra_slink_start_dma_based_transfer()
509 tspi->dma_control_reg = val; in tegra_slink_start_dma_based_transfer()
511 if (tspi->cur_direction & DATA_DIR_TX) { in tegra_slink_start_dma_based_transfer()
516 dev_err(tspi->dev, in tegra_slink_start_dma_based_transfer()
521 /* Wait for tx fifo to be fill before starting slink */ in tegra_slink_start_dma_based_transfer()
527 if (tspi->cur_direction & DATA_DIR_RX) { in tegra_slink_start_dma_based_transfer()
529 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys, in tegra_slink_start_dma_based_transfer()
530 tspi->dma_buf_size, DMA_FROM_DEVICE); in tegra_slink_start_dma_based_transfer()
534 dev_err(tspi->dev, in tegra_slink_start_dma_based_transfer()
536 if (tspi->cur_direction & DATA_DIR_TX) in tegra_slink_start_dma_based_transfer()
537 dmaengine_terminate_all(tspi->tx_dma_chan); in tegra_slink_start_dma_based_transfer()
541 tspi->is_curr_dma_xfer = true; in tegra_slink_start_dma_based_transfer()
542 if (tspi->is_packed) { in tegra_slink_start_dma_based_transfer()
548 tspi->dma_control_reg = val; in tegra_slink_start_dma_based_transfer()
561 val = tspi->packed_size; in tegra_slink_start_cpu_based_transfer()
562 if (tspi->cur_direction & DATA_DIR_TX) in tegra_slink_start_cpu_based_transfer()
565 if (tspi->cur_direction & DATA_DIR_RX) in tegra_slink_start_cpu_based_transfer()
569 tspi->dma_control_reg = val; in tegra_slink_start_cpu_based_transfer()
571 if (tspi->cur_direction & DATA_DIR_TX) in tegra_slink_start_cpu_based_transfer()
574 cur_words = tspi->curr_dma_words; in tegra_slink_start_cpu_based_transfer()
575 val |= SLINK_DMA_BLOCK_SIZE(cur_words - 1); in tegra_slink_start_cpu_based_transfer()
577 tspi->dma_control_reg = val; in tegra_slink_start_cpu_based_transfer()
579 tspi->is_curr_dma_xfer = false; in tegra_slink_start_cpu_based_transfer()
580 if (tspi->is_packed) { in tegra_slink_start_cpu_based_transfer()
586 tspi->dma_control_reg = val; in tegra_slink_start_cpu_based_transfer()
601 dma_chan = dma_request_chan(tspi->dev, dma_to_memory ? "rx" : "tx"); in tegra_slink_init_dma_param()
603 return dev_err_probe(tspi->dev, PTR_ERR(dma_chan), in tegra_slink_init_dma_param()
606 dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size, in tegra_slink_init_dma_param()
609 dev_err(tspi->dev, " Not able to allocate the dma buffer\n"); in tegra_slink_init_dma_param()
611 return -ENOMEM; in tegra_slink_init_dma_param()
615 dma_sconfig.src_addr = tspi->phys + SLINK_RX_FIFO; in tegra_slink_init_dma_param()
619 dma_sconfig.dst_addr = tspi->phys + SLINK_TX_FIFO; in tegra_slink_init_dma_param()
628 tspi->rx_dma_chan = dma_chan; in tegra_slink_init_dma_param()
629 tspi->rx_dma_buf = dma_buf; in tegra_slink_init_dma_param()
630 tspi->rx_dma_phys = dma_phys; in tegra_slink_init_dma_param()
632 tspi->tx_dma_chan = dma_chan; in tegra_slink_init_dma_param()
633 tspi->tx_dma_buf = dma_buf; in tegra_slink_init_dma_param()
634 tspi->tx_dma_phys = dma_phys; in tegra_slink_init_dma_param()
639 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys); in tegra_slink_init_dma_param()
652 dma_buf = tspi->rx_dma_buf; in tegra_slink_deinit_dma_param()
653 dma_chan = tspi->rx_dma_chan; in tegra_slink_deinit_dma_param()
654 dma_phys = tspi->rx_dma_phys; in tegra_slink_deinit_dma_param()
655 tspi->rx_dma_chan = NULL; in tegra_slink_deinit_dma_param()
656 tspi->rx_dma_buf = NULL; in tegra_slink_deinit_dma_param()
658 dma_buf = tspi->tx_dma_buf; in tegra_slink_deinit_dma_param()
659 dma_chan = tspi->tx_dma_chan; in tegra_slink_deinit_dma_param()
660 dma_phys = tspi->tx_dma_phys; in tegra_slink_deinit_dma_param()
661 tspi->tx_dma_buf = NULL; in tegra_slink_deinit_dma_param()
662 tspi->tx_dma_chan = NULL; in tegra_slink_deinit_dma_param()
667 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys); in tegra_slink_deinit_dma_param()
674 struct tegra_slink_data *tspi = spi_controller_get_devdata(spi->controller); in tegra_slink_start_transfer_one()
682 bits_per_word = t->bits_per_word; in tegra_slink_start_transfer_one()
683 speed = t->speed_hz; in tegra_slink_start_transfer_one()
684 if (speed != tspi->cur_speed) { in tegra_slink_start_transfer_one()
685 dev_pm_opp_set_rate(tspi->dev, speed * 4); in tegra_slink_start_transfer_one()
686 tspi->cur_speed = speed; in tegra_slink_start_transfer_one()
689 tspi->cur_spi = spi; in tegra_slink_start_transfer_one()
690 tspi->cur_pos = 0; in tegra_slink_start_transfer_one()
691 tspi->cur_rx_pos = 0; in tegra_slink_start_transfer_one()
692 tspi->cur_tx_pos = 0; in tegra_slink_start_transfer_one()
693 tspi->curr_xfer = t; in tegra_slink_start_transfer_one()
696 command = tspi->command_reg; in tegra_slink_start_transfer_one()
698 command |= SLINK_BIT_LENGTH(bits_per_word - 1); in tegra_slink_start_transfer_one()
700 command2 = tspi->command2_reg; in tegra_slink_start_transfer_one()
703 tspi->cur_direction = 0; in tegra_slink_start_transfer_one()
704 if (t->rx_buf) { in tegra_slink_start_transfer_one()
706 tspi->cur_direction |= DATA_DIR_RX; in tegra_slink_start_transfer_one()
708 if (t->tx_buf) { in tegra_slink_start_transfer_one()
710 tspi->cur_direction |= DATA_DIR_TX; in tegra_slink_start_transfer_one()
719 tspi->command2_reg = command2; in tegra_slink_start_transfer_one()
722 tspi->command_reg = command; in tegra_slink_start_transfer_one()
740 struct tegra_slink_data *tspi = spi_controller_get_devdata(spi->controller); in tegra_slink_setup()
745 dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n", in tegra_slink_setup()
746 spi->bits_per_word, in tegra_slink_setup()
747 spi->mode & SPI_CPOL ? "" : "~", in tegra_slink_setup()
748 spi->mode & SPI_CPHA ? "" : "~", in tegra_slink_setup()
749 spi->max_speed_hz); in tegra_slink_setup()
751 ret = pm_runtime_resume_and_get(tspi->dev); in tegra_slink_setup()
753 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret); in tegra_slink_setup()
757 spin_lock_irqsave(&tspi->lock, flags); in tegra_slink_setup()
758 val = tspi->def_command_reg; in tegra_slink_setup()
759 if (spi->mode & SPI_CS_HIGH) in tegra_slink_setup()
763 tspi->def_command_reg = val; in tegra_slink_setup()
764 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND); in tegra_slink_setup()
765 spin_unlock_irqrestore(&tspi->lock, flags); in tegra_slink_setup()
767 pm_runtime_put(tspi->dev); in tegra_slink_setup()
775 struct spi_device *spi = msg->spi; in tegra_slink_prepare_message()
779 tspi->command_reg = tspi->def_command_reg; in tegra_slink_prepare_message()
780 tspi->command_reg |= SLINK_CS_SW | SLINK_CS_VALUE; in tegra_slink_prepare_message()
782 tspi->command2_reg = tspi->def_command2_reg; in tegra_slink_prepare_message()
783 tspi->command2_reg |= SLINK_SS_EN_CS(spi_get_chipselect(spi, 0)); in tegra_slink_prepare_message()
785 tspi->command_reg &= ~SLINK_MODES; in tegra_slink_prepare_message()
786 if (spi->mode & SPI_CPHA) in tegra_slink_prepare_message()
787 tspi->command_reg |= SLINK_CK_SDA; in tegra_slink_prepare_message()
789 if (spi->mode & SPI_CPOL) in tegra_slink_prepare_message()
790 tspi->command_reg |= SLINK_IDLE_SCLK_DRIVE_HIGH; in tegra_slink_prepare_message()
792 tspi->command_reg |= SLINK_IDLE_SCLK_DRIVE_LOW; in tegra_slink_prepare_message()
804 reinit_completion(&tspi->xfer_completion); in tegra_slink_transfer_one()
807 dev_err(tspi->dev, in tegra_slink_transfer_one()
812 ret = wait_for_completion_timeout(&tspi->xfer_completion, in tegra_slink_transfer_one()
815 dev_err(tspi->dev, in tegra_slink_transfer_one()
817 return -EIO; in tegra_slink_transfer_one()
820 if (tspi->tx_status) in tegra_slink_transfer_one()
821 return tspi->tx_status; in tegra_slink_transfer_one()
822 if (tspi->rx_status) in tegra_slink_transfer_one()
823 return tspi->rx_status; in tegra_slink_transfer_one()
833 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND); in tegra_slink_unprepare_message()
834 tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2); in tegra_slink_unprepare_message()
841 struct spi_transfer *t = tspi->curr_xfer; in handle_cpu_based_xfer()
844 spin_lock_irqsave(&tspi->lock, flags); in handle_cpu_based_xfer()
845 if (tspi->tx_status || tspi->rx_status || in handle_cpu_based_xfer()
846 (tspi->status_reg & SLINK_BSY)) { in handle_cpu_based_xfer()
847 dev_err(tspi->dev, in handle_cpu_based_xfer()
848 "CpuXfer ERROR bit set 0x%x\n", tspi->status_reg); in handle_cpu_based_xfer()
849 dev_err(tspi->dev, in handle_cpu_based_xfer()
850 "CpuXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg, in handle_cpu_based_xfer()
851 tspi->command2_reg, tspi->dma_control_reg); in handle_cpu_based_xfer()
852 reset_control_assert(tspi->rst); in handle_cpu_based_xfer()
854 reset_control_deassert(tspi->rst); in handle_cpu_based_xfer()
855 complete(&tspi->xfer_completion); in handle_cpu_based_xfer()
859 if (tspi->cur_direction & DATA_DIR_RX) in handle_cpu_based_xfer()
862 if (tspi->cur_direction & DATA_DIR_TX) in handle_cpu_based_xfer()
863 tspi->cur_pos = tspi->cur_tx_pos; in handle_cpu_based_xfer()
865 tspi->cur_pos = tspi->cur_rx_pos; in handle_cpu_based_xfer()
867 if (tspi->cur_pos == t->len) { in handle_cpu_based_xfer()
868 complete(&tspi->xfer_completion); in handle_cpu_based_xfer()
872 tegra_slink_calculate_curr_xfer_param(tspi->cur_spi, tspi, t); in handle_cpu_based_xfer()
875 spin_unlock_irqrestore(&tspi->lock, flags); in handle_cpu_based_xfer()
881 struct spi_transfer *t = tspi->curr_xfer; in handle_dma_based_xfer()
888 if (tspi->cur_direction & DATA_DIR_TX) { in handle_dma_based_xfer()
889 if (tspi->tx_status) { in handle_dma_based_xfer()
890 dmaengine_terminate_all(tspi->tx_dma_chan); in handle_dma_based_xfer()
894 &tspi->tx_dma_complete, SLINK_DMA_TIMEOUT); in handle_dma_based_xfer()
896 dmaengine_terminate_all(tspi->tx_dma_chan); in handle_dma_based_xfer()
897 dev_err(tspi->dev, "TxDma Xfer failed\n"); in handle_dma_based_xfer()
903 if (tspi->cur_direction & DATA_DIR_RX) { in handle_dma_based_xfer()
904 if (tspi->rx_status) { in handle_dma_based_xfer()
905 dmaengine_terminate_all(tspi->rx_dma_chan); in handle_dma_based_xfer()
909 &tspi->rx_dma_complete, SLINK_DMA_TIMEOUT); in handle_dma_based_xfer()
911 dmaengine_terminate_all(tspi->rx_dma_chan); in handle_dma_based_xfer()
912 dev_err(tspi->dev, "RxDma Xfer failed\n"); in handle_dma_based_xfer()
918 spin_lock_irqsave(&tspi->lock, flags); in handle_dma_based_xfer()
920 dev_err(tspi->dev, in handle_dma_based_xfer()
921 "DmaXfer: ERROR bit set 0x%x\n", tspi->status_reg); in handle_dma_based_xfer()
922 dev_err(tspi->dev, in handle_dma_based_xfer()
923 "DmaXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg, in handle_dma_based_xfer()
924 tspi->command2_reg, tspi->dma_control_reg); in handle_dma_based_xfer()
925 reset_control_assert(tspi->rst); in handle_dma_based_xfer()
927 reset_control_assert(tspi->rst); in handle_dma_based_xfer()
928 complete(&tspi->xfer_completion); in handle_dma_based_xfer()
929 spin_unlock_irqrestore(&tspi->lock, flags); in handle_dma_based_xfer()
933 if (tspi->cur_direction & DATA_DIR_RX) in handle_dma_based_xfer()
936 if (tspi->cur_direction & DATA_DIR_TX) in handle_dma_based_xfer()
937 tspi->cur_pos = tspi->cur_tx_pos; in handle_dma_based_xfer()
939 tspi->cur_pos = tspi->cur_rx_pos; in handle_dma_based_xfer()
941 if (tspi->cur_pos == t->len) { in handle_dma_based_xfer()
942 complete(&tspi->xfer_completion); in handle_dma_based_xfer()
947 total_fifo_words = tegra_slink_calculate_curr_xfer_param(tspi->cur_spi, in handle_dma_based_xfer()
955 spin_unlock_irqrestore(&tspi->lock, flags); in handle_dma_based_xfer()
963 if (!tspi->is_curr_dma_xfer) in tegra_slink_isr_thread()
972 tspi->status_reg = tegra_slink_readl(tspi, SLINK_STATUS); in tegra_slink_isr()
973 if (tspi->cur_direction & DATA_DIR_TX) in tegra_slink_isr()
974 tspi->tx_status = tspi->status_reg & in tegra_slink_isr()
977 if (tspi->cur_direction & DATA_DIR_RX) in tegra_slink_isr()
978 tspi->rx_status = tspi->status_reg & in tegra_slink_isr()
994 { .compatible = "nvidia,tegra30-slink", .data = &tegra30_spi_cdata, },
995 { .compatible = "nvidia,tegra20-slink", .data = &tegra20_spi_cdata, },
1008 cdata = of_device_get_match_data(&pdev->dev); in tegra_slink_probe()
1010 host = spi_alloc_host(&pdev->dev, sizeof(*tspi)); in tegra_slink_probe()
1012 dev_err(&pdev->dev, "host allocation failed\n"); in tegra_slink_probe()
1013 return -ENOMEM; in tegra_slink_probe()
1016 /* the spi->mode bits understood by this driver: */ in tegra_slink_probe()
1017 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; in tegra_slink_probe()
1018 host->setup = tegra_slink_setup; in tegra_slink_probe()
1019 host->prepare_message = tegra_slink_prepare_message; in tegra_slink_probe()
1020 host->transfer_one = tegra_slink_transfer_one; in tegra_slink_probe()
1021 host->unprepare_message = tegra_slink_unprepare_message; in tegra_slink_probe()
1022 host->auto_runtime_pm = true; in tegra_slink_probe()
1023 host->num_chipselect = MAX_CHIP_SELECT; in tegra_slink_probe()
1027 tspi->host = host; in tegra_slink_probe()
1028 tspi->dev = &pdev->dev; in tegra_slink_probe()
1029 tspi->chip_data = cdata; in tegra_slink_probe()
1030 spin_lock_init(&tspi->lock); in tegra_slink_probe()
1032 if (of_property_read_u32(tspi->dev->of_node, "spi-max-frequency", in tegra_slink_probe()
1033 &host->max_speed_hz)) in tegra_slink_probe()
1034 host->max_speed_hz = 25000000; /* 25MHz */ in tegra_slink_probe()
1036 tspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &r); in tegra_slink_probe()
1037 if (IS_ERR(tspi->base)) { in tegra_slink_probe()
1038 ret = PTR_ERR(tspi->base); in tegra_slink_probe()
1041 tspi->phys = r->start; in tegra_slink_probe()
1044 tspi->clk = devm_clk_get(&pdev->dev, NULL); in tegra_slink_probe()
1045 if (IS_ERR(tspi->clk)) { in tegra_slink_probe()
1046 ret = PTR_ERR(tspi->clk); in tegra_slink_probe()
1047 dev_err(&pdev->dev, "Can not get clock %d\n", ret); in tegra_slink_probe()
1051 tspi->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi"); in tegra_slink_probe()
1052 if (IS_ERR(tspi->rst)) { in tegra_slink_probe()
1053 dev_err(&pdev->dev, "can not get reset\n"); in tegra_slink_probe()
1054 ret = PTR_ERR(tspi->rst); in tegra_slink_probe()
1058 ret = devm_tegra_core_dev_init_opp_table_common(&pdev->dev); in tegra_slink_probe()
1062 tspi->max_buf_size = SLINK_FIFO_DEPTH << 2; in tegra_slink_probe()
1063 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN; in tegra_slink_probe()
1071 tspi->max_buf_size = tspi->dma_buf_size; in tegra_slink_probe()
1072 init_completion(&tspi->tx_dma_complete); in tegra_slink_probe()
1073 init_completion(&tspi->rx_dma_complete); in tegra_slink_probe()
1075 init_completion(&tspi->xfer_completion); in tegra_slink_probe()
1077 pm_runtime_enable(&pdev->dev); in tegra_slink_probe()
1078 ret = pm_runtime_resume_and_get(&pdev->dev); in tegra_slink_probe()
1080 dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret); in tegra_slink_probe()
1084 reset_control_assert(tspi->rst); in tegra_slink_probe()
1086 reset_control_deassert(tspi->rst); in tegra_slink_probe()
1091 tspi->irq = spi_irq; in tegra_slink_probe()
1092 ret = request_threaded_irq(tspi->irq, tegra_slink_isr, in tegra_slink_probe()
1094 dev_name(&pdev->dev), tspi); in tegra_slink_probe()
1096 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n", in tegra_slink_probe()
1097 tspi->irq); in tegra_slink_probe()
1101 tspi->def_command_reg = SLINK_M_S; in tegra_slink_probe()
1102 tspi->def_command2_reg = SLINK_CS_ACTIVE_BETWEEN; in tegra_slink_probe()
1103 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND); in tegra_slink_probe()
1104 tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2); in tegra_slink_probe()
1106 host->dev.of_node = pdev->dev.of_node; in tegra_slink_probe()
1109 dev_err(&pdev->dev, "can not register to host err %d\n", ret); in tegra_slink_probe()
1113 pm_runtime_put(&pdev->dev); in tegra_slink_probe()
1120 pm_runtime_put(&pdev->dev); in tegra_slink_probe()
1122 pm_runtime_force_suspend(&pdev->dev); in tegra_slink_probe()
1139 free_irq(tspi->irq, tspi); in tegra_slink_remove()
1141 pm_runtime_force_suspend(&pdev->dev); in tegra_slink_remove()
1143 if (tspi->tx_dma_chan) in tegra_slink_remove()
1146 if (tspi->rx_dma_chan) in tegra_slink_remove()
1171 tegra_slink_writel(tspi, tspi->command_reg, SLINK_COMMAND); in tegra_slink_resume()
1172 tegra_slink_writel(tspi, tspi->command2_reg, SLINK_COMMAND2); in tegra_slink_resume()
1187 clk_disable_unprepare(tspi->clk); in tegra_slink_runtime_suspend()
1197 ret = clk_prepare_enable(tspi->clk); in tegra_slink_runtime_resume()
1199 dev_err(tspi->dev, "clk_prepare failed: %d\n", ret); in tegra_slink_runtime_resume()
1212 .name = "spi-tegra-slink",
1221 MODULE_ALIAS("platform:spi-tegra-slink");
1222 MODULE_DESCRIPTION("NVIDIA Tegra20/Tegra30 SLINK Controller Driver");