Lines Matching +full:rx +full:- +full:clk +full:- +full:tap +full:- +full:delay
1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk.h>
10 #include <linux/delay.h>
12 #include <linux/dma-mapping.h>
170 struct clk *clk; member
229 return readl(tspi->base + reg); in tegra_spi_readl()
235 writel(val, tspi->base + reg); in tegra_spi_writel()
239 readl(tspi->base + SPI_COMMAND1); in tegra_spi_writel()
261 unsigned remain_len = t->len - tspi->cur_pos; in tegra_spi_calculate_curr_xfer_param()
263 unsigned bits_per_word = t->bits_per_word; in tegra_spi_calculate_curr_xfer_param()
267 tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8); in tegra_spi_calculate_curr_xfer_param()
270 bits_per_word == 32) && t->len > 3) { in tegra_spi_calculate_curr_xfer_param()
271 tspi->is_packed = true; in tegra_spi_calculate_curr_xfer_param()
272 tspi->words_per_32bit = 32/bits_per_word; in tegra_spi_calculate_curr_xfer_param()
274 tspi->is_packed = false; in tegra_spi_calculate_curr_xfer_param()
275 tspi->words_per_32bit = 1; in tegra_spi_calculate_curr_xfer_param()
278 if (tspi->is_packed) { in tegra_spi_calculate_curr_xfer_param()
279 max_len = min(remain_len, tspi->max_buf_size); in tegra_spi_calculate_curr_xfer_param()
280 tspi->curr_dma_words = max_len/tspi->bytes_per_word; in tegra_spi_calculate_curr_xfer_param()
283 max_word = (remain_len - 1) / tspi->bytes_per_word + 1; in tegra_spi_calculate_curr_xfer_param()
284 max_word = min(max_word, tspi->max_buf_size/4); in tegra_spi_calculate_curr_xfer_param()
285 tspi->curr_dma_words = max_word; in tegra_spi_calculate_curr_xfer_param()
301 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos; in tegra_spi_fill_tx_fifo_from_client_txbuf()
306 if (tspi->is_packed) { in tegra_spi_fill_tx_fifo_from_client_txbuf()
307 fifo_words_left = tx_empty_count * tspi->words_per_32bit; in tegra_spi_fill_tx_fifo_from_client_txbuf()
308 written_words = min(fifo_words_left, tspi->curr_dma_words); in tegra_spi_fill_tx_fifo_from_client_txbuf()
309 nbytes = written_words * tspi->bytes_per_word; in tegra_spi_fill_tx_fifo_from_client_txbuf()
314 for (i = 0; (i < 4) && nbytes; i++, nbytes--) in tegra_spi_fill_tx_fifo_from_client_txbuf()
319 tspi->cur_tx_pos += written_words * tspi->bytes_per_word; in tegra_spi_fill_tx_fifo_from_client_txbuf()
322 max_n_32bit = min(tspi->curr_dma_words, tx_empty_count); in tegra_spi_fill_tx_fifo_from_client_txbuf()
324 nbytes = written_words * tspi->bytes_per_word; in tegra_spi_fill_tx_fifo_from_client_txbuf()
325 if (nbytes > t->len - tspi->cur_pos) in tegra_spi_fill_tx_fifo_from_client_txbuf()
326 nbytes = t->len - tspi->cur_pos; in tegra_spi_fill_tx_fifo_from_client_txbuf()
331 for (i = 0; nbytes && (i < tspi->bytes_per_word); in tegra_spi_fill_tx_fifo_from_client_txbuf()
332 i++, nbytes--) in tegra_spi_fill_tx_fifo_from_client_txbuf()
337 tspi->cur_tx_pos += write_bytes; in tegra_spi_fill_tx_fifo_from_client_txbuf()
351 u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos; in tegra_spi_read_rx_fifo_to_client_rxbuf()
355 if (tspi->is_packed) { in tegra_spi_read_rx_fifo_to_client_rxbuf()
356 len = tspi->curr_dma_words * tspi->bytes_per_word; in tegra_spi_read_rx_fifo_to_client_rxbuf()
360 for (i = 0; len && (i < 4); i++, len--) in tegra_spi_read_rx_fifo_to_client_rxbuf()
363 read_words += tspi->curr_dma_words; in tegra_spi_read_rx_fifo_to_client_rxbuf()
364 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word; in tegra_spi_read_rx_fifo_to_client_rxbuf()
366 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1; in tegra_spi_read_rx_fifo_to_client_rxbuf()
367 u8 bytes_per_word = tspi->bytes_per_word; in tegra_spi_read_rx_fifo_to_client_rxbuf()
371 if (len > t->len - tspi->cur_pos) in tegra_spi_read_rx_fifo_to_client_rxbuf()
372 len = t->len - tspi->cur_pos; in tegra_spi_read_rx_fifo_to_client_rxbuf()
377 for (i = 0; len && (i < bytes_per_word); i++, len--) in tegra_spi_read_rx_fifo_to_client_rxbuf()
381 tspi->cur_rx_pos += read_bytes; in tegra_spi_read_rx_fifo_to_client_rxbuf()
391 dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys, in tegra_spi_copy_client_txbuf_to_spi_txbuf()
392 tspi->dma_buf_size, DMA_TO_DEVICE); in tegra_spi_copy_client_txbuf_to_spi_txbuf()
394 if (tspi->is_packed) { in tegra_spi_copy_client_txbuf_to_spi_txbuf()
395 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word; in tegra_spi_copy_client_txbuf_to_spi_txbuf()
397 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len); in tegra_spi_copy_client_txbuf_to_spi_txbuf()
398 tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word; in tegra_spi_copy_client_txbuf_to_spi_txbuf()
402 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos; in tegra_spi_copy_client_txbuf_to_spi_txbuf()
403 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word; in tegra_spi_copy_client_txbuf_to_spi_txbuf()
406 if (consume > t->len - tspi->cur_pos) in tegra_spi_copy_client_txbuf_to_spi_txbuf()
407 consume = t->len - tspi->cur_pos; in tegra_spi_copy_client_txbuf_to_spi_txbuf()
409 for (count = 0; count < tspi->curr_dma_words; count++) { in tegra_spi_copy_client_txbuf_to_spi_txbuf()
412 for (i = 0; consume && (i < tspi->bytes_per_word); in tegra_spi_copy_client_txbuf_to_spi_txbuf()
413 i++, consume--) in tegra_spi_copy_client_txbuf_to_spi_txbuf()
415 tspi->tx_dma_buf[count] = x; in tegra_spi_copy_client_txbuf_to_spi_txbuf()
418 tspi->cur_tx_pos += write_bytes; in tegra_spi_copy_client_txbuf_to_spi_txbuf()
422 dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys, in tegra_spi_copy_client_txbuf_to_spi_txbuf()
423 tspi->dma_buf_size, DMA_TO_DEVICE); in tegra_spi_copy_client_txbuf_to_spi_txbuf()
430 dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys, in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
431 tspi->dma_buf_size, DMA_FROM_DEVICE); in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
433 if (tspi->is_packed) { in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
434 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word; in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
436 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len); in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
437 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word; in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
441 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos; in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
442 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1; in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
443 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word; in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
446 if (consume > t->len - tspi->cur_pos) in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
447 consume = t->len - tspi->cur_pos; in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
449 for (count = 0; count < tspi->curr_dma_words; count++) { in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
450 u32 x = tspi->rx_dma_buf[count] & rx_mask; in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
452 for (i = 0; consume && (i < tspi->bytes_per_word); in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
453 i++, consume--) in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
457 tspi->cur_rx_pos += read_bytes; in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
461 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys, in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
462 tspi->dma_buf_size, DMA_FROM_DEVICE); in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
474 reinit_completion(&tspi->tx_dma_complete); in tegra_spi_start_tx_dma()
475 tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan, in tegra_spi_start_tx_dma()
476 tspi->tx_dma_phys, len, DMA_MEM_TO_DEV, in tegra_spi_start_tx_dma()
478 if (!tspi->tx_dma_desc) { in tegra_spi_start_tx_dma()
479 dev_err(tspi->dev, "Not able to get desc for Tx\n"); in tegra_spi_start_tx_dma()
480 return -EIO; in tegra_spi_start_tx_dma()
483 tspi->tx_dma_desc->callback = tegra_spi_dma_complete; in tegra_spi_start_tx_dma()
484 tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete; in tegra_spi_start_tx_dma()
486 dmaengine_submit(tspi->tx_dma_desc); in tegra_spi_start_tx_dma()
487 dma_async_issue_pending(tspi->tx_dma_chan); in tegra_spi_start_tx_dma()
493 reinit_completion(&tspi->rx_dma_complete); in tegra_spi_start_rx_dma()
494 tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan, in tegra_spi_start_rx_dma()
495 tspi->rx_dma_phys, len, DMA_DEV_TO_MEM, in tegra_spi_start_rx_dma()
497 if (!tspi->rx_dma_desc) { in tegra_spi_start_rx_dma()
498 dev_err(tspi->dev, "Not able to get desc for Rx\n"); in tegra_spi_start_rx_dma()
499 return -EIO; in tegra_spi_start_rx_dma()
502 tspi->rx_dma_desc->callback = tegra_spi_dma_complete; in tegra_spi_start_rx_dma()
503 tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete; in tegra_spi_start_rx_dma()
505 dmaengine_submit(tspi->rx_dma_desc); in tegra_spi_start_rx_dma()
506 dma_async_issue_pending(tspi->rx_dma_chan); in tegra_spi_start_rx_dma()
522 dev_err(tspi->dev, in tegra_spi_flush_fifos()
524 return -EIO; in tegra_spi_flush_fifos()
543 val = SPI_DMA_BLK_SET(tspi->curr_dma_words - 1); in tegra_spi_start_dma_based_transfer()
546 if (tspi->is_packed) in tegra_spi_start_dma_based_transfer()
547 len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word, in tegra_spi_start_dma_based_transfer()
550 len = tspi->curr_dma_words * 4; in tegra_spi_start_dma_based_transfer()
564 if (!tspi->soc_data->has_intr_mask_reg) { in tegra_spi_start_dma_based_transfer()
565 if (tspi->cur_direction & DATA_DIR_TX) in tegra_spi_start_dma_based_transfer()
568 if (tspi->cur_direction & DATA_DIR_RX) in tegra_spi_start_dma_based_transfer()
573 tspi->dma_control_reg = val; in tegra_spi_start_dma_based_transfer()
576 if (tspi->cur_direction & DATA_DIR_TX) { in tegra_spi_start_dma_based_transfer()
577 dma_sconfig.dst_addr = tspi->phys + SPI_TX_FIFO; in tegra_spi_start_dma_based_transfer()
580 ret = dmaengine_slave_config(tspi->tx_dma_chan, &dma_sconfig); in tegra_spi_start_dma_based_transfer()
582 dev_err(tspi->dev, in tegra_spi_start_dma_based_transfer()
590 dev_err(tspi->dev, in tegra_spi_start_dma_based_transfer()
596 if (tspi->cur_direction & DATA_DIR_RX) { in tegra_spi_start_dma_based_transfer()
597 dma_sconfig.src_addr = tspi->phys + SPI_RX_FIFO; in tegra_spi_start_dma_based_transfer()
600 ret = dmaengine_slave_config(tspi->rx_dma_chan, &dma_sconfig); in tegra_spi_start_dma_based_transfer()
602 dev_err(tspi->dev, in tegra_spi_start_dma_based_transfer()
608 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys, in tegra_spi_start_dma_based_transfer()
609 tspi->dma_buf_size, DMA_FROM_DEVICE); in tegra_spi_start_dma_based_transfer()
613 dev_err(tspi->dev, in tegra_spi_start_dma_based_transfer()
614 "Starting rx dma failed, err %d\n", ret); in tegra_spi_start_dma_based_transfer()
615 if (tspi->cur_direction & DATA_DIR_TX) in tegra_spi_start_dma_based_transfer()
616 dmaengine_terminate_all(tspi->tx_dma_chan); in tegra_spi_start_dma_based_transfer()
620 tspi->is_curr_dma_xfer = true; in tegra_spi_start_dma_based_transfer()
621 tspi->dma_control_reg = val; in tegra_spi_start_dma_based_transfer()
634 if (tspi->cur_direction & DATA_DIR_TX) in tegra_spi_start_cpu_based_transfer()
637 cur_words = tspi->curr_dma_words; in tegra_spi_start_cpu_based_transfer()
639 val = SPI_DMA_BLK_SET(cur_words - 1); in tegra_spi_start_cpu_based_transfer()
643 if (tspi->cur_direction & DATA_DIR_TX) in tegra_spi_start_cpu_based_transfer()
646 if (tspi->cur_direction & DATA_DIR_RX) in tegra_spi_start_cpu_based_transfer()
650 tspi->dma_control_reg = val; in tegra_spi_start_cpu_based_transfer()
652 tspi->is_curr_dma_xfer = false; in tegra_spi_start_cpu_based_transfer()
654 val = tspi->command1_reg; in tegra_spi_start_cpu_based_transfer()
667 dma_chan = dma_request_chan(tspi->dev, dma_to_memory ? "rx" : "tx"); in tegra_spi_init_dma_param()
669 return dev_err_probe(tspi->dev, PTR_ERR(dma_chan), in tegra_spi_init_dma_param()
672 dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size, in tegra_spi_init_dma_param()
675 dev_err(tspi->dev, " Not able to allocate the dma buffer\n"); in tegra_spi_init_dma_param()
677 return -ENOMEM; in tegra_spi_init_dma_param()
681 tspi->rx_dma_chan = dma_chan; in tegra_spi_init_dma_param()
682 tspi->rx_dma_buf = dma_buf; in tegra_spi_init_dma_param()
683 tspi->rx_dma_phys = dma_phys; in tegra_spi_init_dma_param()
685 tspi->tx_dma_chan = dma_chan; in tegra_spi_init_dma_param()
686 tspi->tx_dma_buf = dma_buf; in tegra_spi_init_dma_param()
687 tspi->tx_dma_phys = dma_phys; in tegra_spi_init_dma_param()
700 dma_buf = tspi->rx_dma_buf; in tegra_spi_deinit_dma_param()
701 dma_chan = tspi->rx_dma_chan; in tegra_spi_deinit_dma_param()
702 dma_phys = tspi->rx_dma_phys; in tegra_spi_deinit_dma_param()
703 tspi->rx_dma_chan = NULL; in tegra_spi_deinit_dma_param()
704 tspi->rx_dma_buf = NULL; in tegra_spi_deinit_dma_param()
706 dma_buf = tspi->tx_dma_buf; in tegra_spi_deinit_dma_param()
707 dma_chan = tspi->tx_dma_chan; in tegra_spi_deinit_dma_param()
708 dma_phys = tspi->tx_dma_phys; in tegra_spi_deinit_dma_param()
709 tspi->tx_dma_buf = NULL; in tegra_spi_deinit_dma_param()
710 tspi->tx_dma_chan = NULL; in tegra_spi_deinit_dma_param()
715 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys); in tegra_spi_deinit_dma_param()
721 struct tegra_spi_data *tspi = spi_controller_get_devdata(spi->controller); in tegra_spi_set_hw_cs_timing()
722 struct spi_delay *setup = &spi->cs_setup; in tegra_spi_set_hw_cs_timing()
723 struct spi_delay *hold = &spi->cs_hold; in tegra_spi_set_hw_cs_timing()
724 struct spi_delay *inactive = &spi->cs_inactive; in tegra_spi_set_hw_cs_timing()
731 if (setup->unit != SPI_DELAY_UNIT_SCK || in tegra_spi_set_hw_cs_timing()
732 hold->unit != SPI_DELAY_UNIT_SCK || in tegra_spi_set_hw_cs_timing()
733 inactive->unit != SPI_DELAY_UNIT_SCK) { in tegra_spi_set_hw_cs_timing()
734 dev_err(&spi->dev, in tegra_spi_set_hw_cs_timing()
735 "Invalid delay unit %d, should be SPI_DELAY_UNIT_SCK\n", in tegra_spi_set_hw_cs_timing()
737 return -EINVAL; in tegra_spi_set_hw_cs_timing()
740 setup_dly = min_t(u8, setup->value, MAX_SETUP_HOLD_CYCLES); in tegra_spi_set_hw_cs_timing()
741 hold_dly = min_t(u8, hold->value, MAX_SETUP_HOLD_CYCLES); in tegra_spi_set_hw_cs_timing()
743 setup_hold = SPI_SETUP_HOLD(setup_dly - 1, hold_dly - 1); in tegra_spi_set_hw_cs_timing()
744 spi_cs_timing = SPI_CS_SETUP_HOLD(tspi->spi_cs_timing1, in tegra_spi_set_hw_cs_timing()
747 if (tspi->spi_cs_timing1 != spi_cs_timing) { in tegra_spi_set_hw_cs_timing()
748 tspi->spi_cs_timing1 = spi_cs_timing; in tegra_spi_set_hw_cs_timing()
753 inactive_cycles = min_t(u8, inactive->value, MAX_INACTIVE_CYCLES); in tegra_spi_set_hw_cs_timing()
755 inactive_cycles--; in tegra_spi_set_hw_cs_timing()
757 spi_cs_timing = tspi->spi_cs_timing2; in tegra_spi_set_hw_cs_timing()
762 if (tspi->spi_cs_timing2 != spi_cs_timing) { in tegra_spi_set_hw_cs_timing()
763 tspi->spi_cs_timing2 = spi_cs_timing; in tegra_spi_set_hw_cs_timing()
775 struct tegra_spi_data *tspi = spi_controller_get_devdata(spi->controller); in tegra_spi_setup_transfer_one()
776 struct tegra_spi_client_data *cdata = spi->controller_data; in tegra_spi_setup_transfer_one()
777 u32 speed = t->speed_hz; in tegra_spi_setup_transfer_one()
778 u8 bits_per_word = t->bits_per_word; in tegra_spi_setup_transfer_one()
783 if (speed != tspi->cur_speed) { in tegra_spi_setup_transfer_one()
784 clk_set_rate(tspi->clk, speed); in tegra_spi_setup_transfer_one()
785 tspi->cur_speed = speed; in tegra_spi_setup_transfer_one()
788 tspi->cur_spi = spi; in tegra_spi_setup_transfer_one()
789 tspi->cur_pos = 0; in tegra_spi_setup_transfer_one()
790 tspi->cur_rx_pos = 0; in tegra_spi_setup_transfer_one()
791 tspi->cur_tx_pos = 0; in tegra_spi_setup_transfer_one()
792 tspi->curr_xfer = t; in tegra_spi_setup_transfer_one()
797 command1 = tspi->def_command1_reg; in tegra_spi_setup_transfer_one()
798 command1 |= SPI_BIT_LENGTH(bits_per_word - 1); in tegra_spi_setup_transfer_one()
801 req_mode = spi->mode & 0x3; in tegra_spi_setup_transfer_one()
811 if (spi->mode & SPI_LSB_FIRST) in tegra_spi_setup_transfer_one()
816 if (spi->mode & SPI_3WIRE) in tegra_spi_setup_transfer_one()
821 if (tspi->cs_control) { in tegra_spi_setup_transfer_one()
822 if (tspi->cs_control != spi) in tegra_spi_setup_transfer_one()
824 tspi->cs_control = NULL; in tegra_spi_setup_transfer_one()
832 if (is_single_xfer && !(t->cs_change)) { in tegra_spi_setup_transfer_one()
833 tspi->use_hw_based_cs = true; in tegra_spi_setup_transfer_one()
836 tspi->use_hw_based_cs = false; in tegra_spi_setup_transfer_one()
838 if (spi->mode & SPI_CS_HIGH) in tegra_spi_setup_transfer_one()
844 if (tspi->last_used_cs != spi_get_chipselect(spi, 0)) { in tegra_spi_setup_transfer_one()
845 if (cdata && cdata->tx_clk_tap_delay) in tegra_spi_setup_transfer_one()
846 tx_tap = cdata->tx_clk_tap_delay; in tegra_spi_setup_transfer_one()
847 if (cdata && cdata->rx_clk_tap_delay) in tegra_spi_setup_transfer_one()
848 rx_tap = cdata->rx_clk_tap_delay; in tegra_spi_setup_transfer_one()
851 if (command2 != tspi->def_command2_reg) in tegra_spi_setup_transfer_one()
853 tspi->last_used_cs = spi_get_chipselect(spi, 0); in tegra_spi_setup_transfer_one()
857 command1 = tspi->command1_reg; in tegra_spi_setup_transfer_one()
859 command1 |= SPI_BIT_LENGTH(bits_per_word - 1); in tegra_spi_setup_transfer_one()
868 struct tegra_spi_data *tspi = spi_controller_get_devdata(spi->controller); in tegra_spi_start_transfer_one()
874 if (t->rx_nbits == SPI_NBITS_DUAL || t->tx_nbits == SPI_NBITS_DUAL) in tegra_spi_start_transfer_one()
879 if (tspi->is_packed) in tegra_spi_start_transfer_one()
885 tspi->cur_direction = 0; in tegra_spi_start_transfer_one()
886 if (t->rx_buf) { in tegra_spi_start_transfer_one()
888 tspi->cur_direction |= DATA_DIR_RX; in tegra_spi_start_transfer_one()
890 if (t->tx_buf) { in tegra_spi_start_transfer_one()
892 tspi->cur_direction |= DATA_DIR_TX; in tegra_spi_start_transfer_one()
896 tspi->command1_reg = command1; in tegra_spi_start_transfer_one()
898 dev_dbg(tspi->dev, "The def 0x%x and written 0x%x\n", in tegra_spi_start_transfer_one()
899 tspi->def_command1_reg, (unsigned)command1); in tegra_spi_start_transfer_one()
917 target_np = spi->dev.of_node; in tegra_spi_parse_cdata_dt()
919 dev_dbg(&spi->dev, "device node not found\n"); in tegra_spi_parse_cdata_dt()
927 of_property_read_u32(target_np, "nvidia,tx-clk-tap-delay", in tegra_spi_parse_cdata_dt()
928 &cdata->tx_clk_tap_delay); in tegra_spi_parse_cdata_dt()
929 of_property_read_u32(target_np, "nvidia,rx-clk-tap-delay", in tegra_spi_parse_cdata_dt()
930 &cdata->rx_clk_tap_delay); in tegra_spi_parse_cdata_dt()
936 struct tegra_spi_client_data *cdata = spi->controller_data; in tegra_spi_cleanup()
938 spi->controller_data = NULL; in tegra_spi_cleanup()
939 if (spi->dev.of_node) in tegra_spi_cleanup()
945 struct tegra_spi_data *tspi = spi_controller_get_devdata(spi->controller); in tegra_spi_setup()
946 struct tegra_spi_client_data *cdata = spi->controller_data; in tegra_spi_setup()
951 dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n", in tegra_spi_setup()
952 spi->bits_per_word, in tegra_spi_setup()
953 spi->mode & SPI_CPOL ? "" : "~", in tegra_spi_setup()
954 spi->mode & SPI_CPHA ? "" : "~", in tegra_spi_setup()
955 spi->max_speed_hz); in tegra_spi_setup()
959 spi->controller_data = cdata; in tegra_spi_setup()
962 ret = pm_runtime_resume_and_get(tspi->dev); in tegra_spi_setup()
964 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret); in tegra_spi_setup()
970 if (tspi->soc_data->has_intr_mask_reg) { in tegra_spi_setup()
976 spin_lock_irqsave(&tspi->lock, flags); in tegra_spi_setup()
981 val = tspi->def_command1_reg; in tegra_spi_setup()
982 if (spi->mode & SPI_CS_HIGH) in tegra_spi_setup()
986 tspi->def_command1_reg = val; in tegra_spi_setup()
987 tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1); in tegra_spi_setup()
988 spin_unlock_irqrestore(&tspi->lock, flags); in tegra_spi_setup()
990 pm_runtime_put(tspi->dev); in tegra_spi_setup()
996 struct tegra_spi_data *tspi = spi_controller_get_devdata(spi->controller); in tegra_spi_transfer_end()
997 int cs_val = (spi->mode & SPI_CS_HIGH) ? 0 : 1; in tegra_spi_transfer_end()
1003 if (!tspi->use_hw_based_cs) { in tegra_spi_transfer_end()
1005 tspi->command1_reg |= SPI_CS_SW_VAL; in tegra_spi_transfer_end()
1007 tspi->command1_reg &= ~SPI_CS_SW_VAL; in tegra_spi_transfer_end()
1008 tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1); in tegra_spi_transfer_end()
1011 tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1); in tegra_spi_transfer_end()
1016 dev_dbg(tspi->dev, "============ SPI REGISTER DUMP ============\n"); in tegra_spi_dump_regs()
1017 dev_dbg(tspi->dev, "Command1: 0x%08x | Command2: 0x%08x\n", in tegra_spi_dump_regs()
1020 dev_dbg(tspi->dev, "DMA_CTL: 0x%08x | DMA_BLK: 0x%08x\n", in tegra_spi_dump_regs()
1023 dev_dbg(tspi->dev, "TRANS_STAT: 0x%08x | FIFO_STATUS: 0x%08x\n", in tegra_spi_dump_regs()
1034 struct spi_device *spi = msg->spi; in tegra_spi_transfer_one_message()
1039 msg->status = 0; in tegra_spi_transfer_one_message()
1040 msg->actual_length = 0; in tegra_spi_transfer_one_message()
1042 single_xfer = list_is_singular(&msg->transfers); in tegra_spi_transfer_one_message()
1043 list_for_each_entry(xfer, &msg->transfers, transfer_list) { in tegra_spi_transfer_one_message()
1046 reinit_completion(&tspi->xfer_completion); in tegra_spi_transfer_one_message()
1051 if (!xfer->len) { in tegra_spi_transfer_one_message()
1059 dev_err(tspi->dev, in tegra_spi_transfer_one_message()
1065 ret = wait_for_completion_timeout(&tspi->xfer_completion, in tegra_spi_transfer_one_message()
1068 dev_err(tspi->dev, "spi transfer timeout\n"); in tegra_spi_transfer_one_message()
1069 if (tspi->is_curr_dma_xfer && in tegra_spi_transfer_one_message()
1070 (tspi->cur_direction & DATA_DIR_TX)) in tegra_spi_transfer_one_message()
1071 dmaengine_terminate_all(tspi->tx_dma_chan); in tegra_spi_transfer_one_message()
1072 if (tspi->is_curr_dma_xfer && in tegra_spi_transfer_one_message()
1073 (tspi->cur_direction & DATA_DIR_RX)) in tegra_spi_transfer_one_message()
1074 dmaengine_terminate_all(tspi->rx_dma_chan); in tegra_spi_transfer_one_message()
1075 ret = -EIO; in tegra_spi_transfer_one_message()
1078 reset_control_assert(tspi->rst); in tegra_spi_transfer_one_message()
1080 reset_control_deassert(tspi->rst); in tegra_spi_transfer_one_message()
1081 tspi->last_used_cs = host->num_chipselect + 1; in tegra_spi_transfer_one_message()
1085 if (tspi->tx_status || tspi->rx_status) { in tegra_spi_transfer_one_message()
1086 dev_err(tspi->dev, "Error in Transfer\n"); in tegra_spi_transfer_one_message()
1087 ret = -EIO; in tegra_spi_transfer_one_message()
1091 msg->actual_length += xfer->len; in tegra_spi_transfer_one_message()
1098 } else if (list_is_last(&xfer->transfer_list, in tegra_spi_transfer_one_message()
1099 &msg->transfers)) { in tegra_spi_transfer_one_message()
1100 if (xfer->cs_change) in tegra_spi_transfer_one_message()
1101 tspi->cs_control = spi; in tegra_spi_transfer_one_message()
1106 } else if (xfer->cs_change) { in tegra_spi_transfer_one_message()
1114 msg->status = ret; in tegra_spi_transfer_one_message()
1121 struct spi_transfer *t = tspi->curr_xfer; in handle_cpu_based_xfer()
1124 spin_lock_irqsave(&tspi->lock, flags); in handle_cpu_based_xfer()
1125 if (tspi->tx_status || tspi->rx_status) { in handle_cpu_based_xfer()
1126 dev_err(tspi->dev, "CpuXfer ERROR bit set 0x%x\n", in handle_cpu_based_xfer()
1127 tspi->status_reg); in handle_cpu_based_xfer()
1128 dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n", in handle_cpu_based_xfer()
1129 tspi->command1_reg, tspi->dma_control_reg); in handle_cpu_based_xfer()
1132 complete(&tspi->xfer_completion); in handle_cpu_based_xfer()
1133 spin_unlock_irqrestore(&tspi->lock, flags); in handle_cpu_based_xfer()
1134 reset_control_assert(tspi->rst); in handle_cpu_based_xfer()
1136 reset_control_deassert(tspi->rst); in handle_cpu_based_xfer()
1140 if (tspi->cur_direction & DATA_DIR_RX) in handle_cpu_based_xfer()
1143 if (tspi->cur_direction & DATA_DIR_TX) in handle_cpu_based_xfer()
1144 tspi->cur_pos = tspi->cur_tx_pos; in handle_cpu_based_xfer()
1146 tspi->cur_pos = tspi->cur_rx_pos; in handle_cpu_based_xfer()
1148 if (tspi->cur_pos == t->len) { in handle_cpu_based_xfer()
1149 complete(&tspi->xfer_completion); in handle_cpu_based_xfer()
1153 tegra_spi_calculate_curr_xfer_param(tspi->cur_spi, tspi, t); in handle_cpu_based_xfer()
1156 spin_unlock_irqrestore(&tspi->lock, flags); in handle_cpu_based_xfer()
1162 struct spi_transfer *t = tspi->curr_xfer; in handle_dma_based_xfer()
1169 if (tspi->cur_direction & DATA_DIR_TX) { in handle_dma_based_xfer()
1170 if (tspi->tx_status) { in handle_dma_based_xfer()
1171 dmaengine_terminate_all(tspi->tx_dma_chan); in handle_dma_based_xfer()
1175 &tspi->tx_dma_complete, SPI_DMA_TIMEOUT); in handle_dma_based_xfer()
1177 dmaengine_terminate_all(tspi->tx_dma_chan); in handle_dma_based_xfer()
1178 dev_err(tspi->dev, "TxDma Xfer failed\n"); in handle_dma_based_xfer()
1184 if (tspi->cur_direction & DATA_DIR_RX) { in handle_dma_based_xfer()
1185 if (tspi->rx_status) { in handle_dma_based_xfer()
1186 dmaengine_terminate_all(tspi->rx_dma_chan); in handle_dma_based_xfer()
1190 &tspi->rx_dma_complete, SPI_DMA_TIMEOUT); in handle_dma_based_xfer()
1192 dmaengine_terminate_all(tspi->rx_dma_chan); in handle_dma_based_xfer()
1193 dev_err(tspi->dev, "RxDma Xfer failed\n"); in handle_dma_based_xfer()
1199 spin_lock_irqsave(&tspi->lock, flags); in handle_dma_based_xfer()
1201 dev_err(tspi->dev, "DmaXfer: ERROR bit set 0x%x\n", in handle_dma_based_xfer()
1202 tspi->status_reg); in handle_dma_based_xfer()
1203 dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n", in handle_dma_based_xfer()
1204 tspi->command1_reg, tspi->dma_control_reg); in handle_dma_based_xfer()
1207 complete(&tspi->xfer_completion); in handle_dma_based_xfer()
1208 spin_unlock_irqrestore(&tspi->lock, flags); in handle_dma_based_xfer()
1209 reset_control_assert(tspi->rst); in handle_dma_based_xfer()
1211 reset_control_deassert(tspi->rst); in handle_dma_based_xfer()
1215 if (tspi->cur_direction & DATA_DIR_RX) in handle_dma_based_xfer()
1218 if (tspi->cur_direction & DATA_DIR_TX) in handle_dma_based_xfer()
1219 tspi->cur_pos = tspi->cur_tx_pos; in handle_dma_based_xfer()
1221 tspi->cur_pos = tspi->cur_rx_pos; in handle_dma_based_xfer()
1223 if (tspi->cur_pos == t->len) { in handle_dma_based_xfer()
1224 complete(&tspi->xfer_completion); in handle_dma_based_xfer()
1229 total_fifo_words = tegra_spi_calculate_curr_xfer_param(tspi->cur_spi, in handle_dma_based_xfer()
1237 spin_unlock_irqrestore(&tspi->lock, flags); in handle_dma_based_xfer()
1245 if (!tspi->is_curr_dma_xfer) in tegra_spi_isr_thread()
1254 tspi->status_reg = tegra_spi_readl(tspi, SPI_FIFO_STATUS); in tegra_spi_isr()
1255 if (tspi->cur_direction & DATA_DIR_TX) in tegra_spi_isr()
1256 tspi->tx_status = tspi->status_reg & in tegra_spi_isr()
1259 if (tspi->cur_direction & DATA_DIR_RX) in tegra_spi_isr()
1260 tspi->rx_status = tspi->status_reg & in tegra_spi_isr()
1281 .compatible = "nvidia,tegra114-spi",
1284 .compatible = "nvidia,tegra124-spi",
1287 .compatible = "nvidia,tegra210-spi",
1302 host = spi_alloc_host(&pdev->dev, sizeof(*tspi)); in tegra_spi_probe()
1304 dev_err(&pdev->dev, "host allocation failed\n"); in tegra_spi_probe()
1305 return -ENOMEM; in tegra_spi_probe()
1310 if (of_property_read_u32(pdev->dev.of_node, "spi-max-frequency", in tegra_spi_probe()
1311 &host->max_speed_hz)) in tegra_spi_probe()
1312 host->max_speed_hz = 25000000; /* 25MHz */ in tegra_spi_probe()
1314 /* the spi->mode bits understood by this driver: */ in tegra_spi_probe()
1315 host->use_gpio_descriptors = true; in tegra_spi_probe()
1316 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST | in tegra_spi_probe()
1318 host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); in tegra_spi_probe()
1319 host->setup = tegra_spi_setup; in tegra_spi_probe()
1320 host->cleanup = tegra_spi_cleanup; in tegra_spi_probe()
1321 host->transfer_one_message = tegra_spi_transfer_one_message; in tegra_spi_probe()
1322 host->set_cs_timing = tegra_spi_set_hw_cs_timing; in tegra_spi_probe()
1323 host->num_chipselect = MAX_CHIP_SELECT; in tegra_spi_probe()
1324 host->auto_runtime_pm = true; in tegra_spi_probe()
1325 bus_num = of_alias_get_id(pdev->dev.of_node, "spi"); in tegra_spi_probe()
1327 host->bus_num = bus_num; in tegra_spi_probe()
1329 tspi->host = host; in tegra_spi_probe()
1330 tspi->dev = &pdev->dev; in tegra_spi_probe()
1331 spin_lock_init(&tspi->lock); in tegra_spi_probe()
1333 tspi->soc_data = of_device_get_match_data(&pdev->dev); in tegra_spi_probe()
1334 if (!tspi->soc_data) { in tegra_spi_probe()
1335 dev_err(&pdev->dev, "unsupported tegra\n"); in tegra_spi_probe()
1336 ret = -ENODEV; in tegra_spi_probe()
1340 tspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &r); in tegra_spi_probe()
1341 if (IS_ERR(tspi->base)) { in tegra_spi_probe()
1342 ret = PTR_ERR(tspi->base); in tegra_spi_probe()
1345 tspi->phys = r->start; in tegra_spi_probe()
1352 tspi->irq = spi_irq; in tegra_spi_probe()
1354 tspi->clk = devm_clk_get(&pdev->dev, "spi"); in tegra_spi_probe()
1355 if (IS_ERR(tspi->clk)) { in tegra_spi_probe()
1356 dev_err(&pdev->dev, "can not get clock\n"); in tegra_spi_probe()
1357 ret = PTR_ERR(tspi->clk); in tegra_spi_probe()
1361 tspi->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi"); in tegra_spi_probe()
1362 if (IS_ERR(tspi->rst)) { in tegra_spi_probe()
1363 dev_err(&pdev->dev, "can not get reset\n"); in tegra_spi_probe()
1364 ret = PTR_ERR(tspi->rst); in tegra_spi_probe()
1368 tspi->max_buf_size = SPI_FIFO_DEPTH << 2; in tegra_spi_probe()
1369 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN; in tegra_spi_probe()
1377 tspi->max_buf_size = tspi->dma_buf_size; in tegra_spi_probe()
1378 init_completion(&tspi->tx_dma_complete); in tegra_spi_probe()
1379 init_completion(&tspi->rx_dma_complete); in tegra_spi_probe()
1381 init_completion(&tspi->xfer_completion); in tegra_spi_probe()
1383 pm_runtime_enable(&pdev->dev); in tegra_spi_probe()
1384 if (!pm_runtime_enabled(&pdev->dev)) { in tegra_spi_probe()
1385 ret = tegra_spi_runtime_resume(&pdev->dev); in tegra_spi_probe()
1390 ret = pm_runtime_resume_and_get(&pdev->dev); in tegra_spi_probe()
1392 dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret); in tegra_spi_probe()
1396 reset_control_assert(tspi->rst); in tegra_spi_probe()
1398 reset_control_deassert(tspi->rst); in tegra_spi_probe()
1399 tspi->def_command1_reg = SPI_M_S; in tegra_spi_probe()
1400 tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1); in tegra_spi_probe()
1401 tspi->spi_cs_timing1 = tegra_spi_readl(tspi, SPI_CS_TIMING1); in tegra_spi_probe()
1402 tspi->spi_cs_timing2 = tegra_spi_readl(tspi, SPI_CS_TIMING2); in tegra_spi_probe()
1403 tspi->def_command2_reg = tegra_spi_readl(tspi, SPI_COMMAND2); in tegra_spi_probe()
1404 tspi->last_used_cs = host->num_chipselect + 1; in tegra_spi_probe()
1405 pm_runtime_put(&pdev->dev); in tegra_spi_probe()
1406 ret = request_threaded_irq(tspi->irq, tegra_spi_isr, in tegra_spi_probe()
1408 dev_name(&pdev->dev), tspi); in tegra_spi_probe()
1410 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n", in tegra_spi_probe()
1411 tspi->irq); in tegra_spi_probe()
1415 host->dev.of_node = pdev->dev.of_node; in tegra_spi_probe()
1416 ret = devm_spi_register_controller(&pdev->dev, host); in tegra_spi_probe()
1418 dev_err(&pdev->dev, "can not register to host err %d\n", ret); in tegra_spi_probe()
1426 pm_runtime_disable(&pdev->dev); in tegra_spi_probe()
1427 if (!pm_runtime_status_suspended(&pdev->dev)) in tegra_spi_probe()
1428 tegra_spi_runtime_suspend(&pdev->dev); in tegra_spi_probe()
1442 free_irq(tspi->irq, tspi); in tegra_spi_remove()
1444 if (tspi->tx_dma_chan) in tegra_spi_remove()
1447 if (tspi->rx_dma_chan) in tegra_spi_remove()
1450 pm_runtime_disable(&pdev->dev); in tegra_spi_remove()
1451 if (!pm_runtime_status_suspended(&pdev->dev)) in tegra_spi_remove()
1452 tegra_spi_runtime_suspend(&pdev->dev); in tegra_spi_remove()
1474 tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1); in tegra_spi_resume()
1475 tegra_spi_writel(tspi, tspi->def_command2_reg, SPI_COMMAND2); in tegra_spi_resume()
1476 tspi->last_used_cs = host->num_chipselect + 1; in tegra_spi_resume()
1491 clk_disable_unprepare(tspi->clk); in tegra_spi_runtime_suspend()
1501 ret = clk_prepare_enable(tspi->clk); in tegra_spi_runtime_resume()
1503 dev_err(tspi->dev, "clk_prepare failed: %d\n", ret); in tegra_spi_runtime_resume()
1516 .name = "spi-tegra114",
1525 MODULE_ALIAS("platform:spi-tegra114");