Lines Matching refs:spi
273 int (*get_fifo_size)(struct stm32_spi *spi);
274 int (*get_bpw_mask)(struct stm32_spi *spi);
275 void (*disable)(struct stm32_spi *spi);
276 int (*config)(struct stm32_spi *spi);
277 void (*set_bpw)(struct stm32_spi *spi);
278 int (*set_mode)(struct stm32_spi *spi, unsigned int comm_type);
279 void (*set_data_idleness)(struct stm32_spi *spi, u32 length);
280 int (*set_number_of_data)(struct stm32_spi *spi, u32 length);
281 void (*write_tx)(struct stm32_spi *spi);
282 void (*read_rx)(struct stm32_spi *spi);
283 void (*transfer_one_dma_start)(struct stm32_spi *spi);
286 int (*transfer_one_irq)(struct stm32_spi *spi);
420 static inline void stm32_spi_set_bits(struct stm32_spi *spi, in stm32_spi_set_bits() argument
423 writel_relaxed(readl_relaxed(spi->base + offset) | bits, in stm32_spi_set_bits()
424 spi->base + offset); in stm32_spi_set_bits()
427 static inline void stm32_spi_clr_bits(struct stm32_spi *spi, in stm32_spi_clr_bits() argument
430 writel_relaxed(readl_relaxed(spi->base + offset) & ~bits, in stm32_spi_clr_bits()
431 spi->base + offset); in stm32_spi_clr_bits()
438 static int stm32h7_spi_get_fifo_size(struct stm32_spi *spi) in stm32h7_spi_get_fifo_size() argument
443 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_get_fifo_size()
445 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); in stm32h7_spi_get_fifo_size()
447 while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP) in stm32h7_spi_get_fifo_size()
448 writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_get_fifo_size()
450 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); in stm32h7_spi_get_fifo_size()
452 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_get_fifo_size()
454 dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count); in stm32h7_spi_get_fifo_size()
463 static int stm32f4_spi_get_bpw_mask(struct stm32_spi *spi) in stm32f4_spi_get_bpw_mask() argument
465 dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n"); in stm32f4_spi_get_bpw_mask()
473 static int stm32f7_spi_get_bpw_mask(struct stm32_spi *spi) in stm32f7_spi_get_bpw_mask() argument
475 dev_dbg(spi->dev, "16-bit maximum data frame\n"); in stm32f7_spi_get_bpw_mask()
483 static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi) in stm32h7_spi_get_bpw_mask() argument
488 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_get_bpw_mask()
494 stm32_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE); in stm32h7_spi_get_bpw_mask()
496 cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1); in stm32h7_spi_get_bpw_mask()
499 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_get_bpw_mask()
501 dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw); in stm32h7_spi_get_bpw_mask()
510 static int stm32mp25_spi_get_bpw_mask(struct stm32_spi *spi) in stm32mp25_spi_get_bpw_mask() argument
514 if (spi->feature_set == STM32_SPI_FEATURE_LIMITED) { in stm32mp25_spi_get_bpw_mask()
515 dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n"); in stm32mp25_spi_get_bpw_mask()
520 readl_relaxed(spi->base + STM32MP25_SPI_HWCFGR1)); in stm32mp25_spi_get_bpw_mask()
524 dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw); in stm32mp25_spi_get_bpw_mask()
537 static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz, in stm32_spi_prepare_mbr() argument
543 div = DIV_ROUND_CLOSEST(spi->clk_rate & ~0x1, speed_hz); in stm32_spi_prepare_mbr()
561 spi->cur_speed = spi->clk_rate / (1 << mbrdiv); in stm32_spi_prepare_mbr()
563 spi->cur_half_period = DIV_ROUND_CLOSEST(USEC_PER_SEC, 2 * spi->cur_speed); in stm32_spi_prepare_mbr()
573 static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi, u32 xfer_len) in stm32h7_spi_prepare_fthlv() argument
578 packet = clamp(xfer_len, 1U, spi->fifo_size / 2); in stm32h7_spi_prepare_fthlv()
581 bpw = DIV_ROUND_UP(spi->cur_bpw, 8); in stm32h7_spi_prepare_fthlv()
592 static void stm32f4_spi_write_tx(struct stm32_spi *spi) in stm32f4_spi_write_tx() argument
594 if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32FX_SPI_SR) & in stm32f4_spi_write_tx()
596 u32 offs = spi->cur_xferlen - spi->tx_len; in stm32f4_spi_write_tx()
598 if (spi->cur_bpw == 16) { in stm32f4_spi_write_tx()
599 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs); in stm32f4_spi_write_tx()
601 writew_relaxed(*tx_buf16, spi->base + STM32FX_SPI_DR); in stm32f4_spi_write_tx()
602 spi->tx_len -= sizeof(u16); in stm32f4_spi_write_tx()
604 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs); in stm32f4_spi_write_tx()
606 writeb_relaxed(*tx_buf8, spi->base + STM32FX_SPI_DR); in stm32f4_spi_write_tx()
607 spi->tx_len -= sizeof(u8); in stm32f4_spi_write_tx()
611 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len); in stm32f4_spi_write_tx()
621 static void stm32f7_spi_write_tx(struct stm32_spi *spi) in stm32f7_spi_write_tx() argument
623 if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32FX_SPI_SR) & in stm32f7_spi_write_tx()
625 u32 offs = spi->cur_xferlen - spi->tx_len; in stm32f7_spi_write_tx()
627 if (spi->tx_len >= sizeof(u16)) { in stm32f7_spi_write_tx()
628 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs); in stm32f7_spi_write_tx()
630 writew_relaxed(*tx_buf16, spi->base + STM32FX_SPI_DR); in stm32f7_spi_write_tx()
631 spi->tx_len -= sizeof(u16); in stm32f7_spi_write_tx()
633 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs); in stm32f7_spi_write_tx()
635 writeb_relaxed(*tx_buf8, spi->base + STM32FX_SPI_DR); in stm32f7_spi_write_tx()
636 spi->tx_len -= sizeof(u8); in stm32f7_spi_write_tx()
640 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len); in stm32f7_spi_write_tx()
650 static void stm32h7_spi_write_txfifo(struct stm32_spi *spi) in stm32h7_spi_write_txfifo() argument
652 while ((spi->tx_len > 0) && in stm32h7_spi_write_txfifo()
653 (readl_relaxed(spi->base + STM32H7_SPI_SR) & in stm32h7_spi_write_txfifo()
655 u32 offs = spi->cur_xferlen - spi->tx_len; in stm32h7_spi_write_txfifo()
657 if (spi->tx_len >= sizeof(u32)) { in stm32h7_spi_write_txfifo()
658 const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs); in stm32h7_spi_write_txfifo()
660 writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_write_txfifo()
661 spi->tx_len -= sizeof(u32); in stm32h7_spi_write_txfifo()
662 } else if (spi->tx_len >= sizeof(u16)) { in stm32h7_spi_write_txfifo()
663 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs); in stm32h7_spi_write_txfifo()
665 writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_write_txfifo()
666 spi->tx_len -= sizeof(u16); in stm32h7_spi_write_txfifo()
668 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs); in stm32h7_spi_write_txfifo()
670 writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_write_txfifo()
671 spi->tx_len -= sizeof(u8); in stm32h7_spi_write_txfifo()
675 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len); in stm32h7_spi_write_txfifo()
685 static void stm32f4_spi_read_rx(struct stm32_spi *spi) in stm32f4_spi_read_rx() argument
687 if ((spi->rx_len > 0) && (readl_relaxed(spi->base + STM32FX_SPI_SR) & in stm32f4_spi_read_rx()
689 u32 offs = spi->cur_xferlen - spi->rx_len; in stm32f4_spi_read_rx()
691 if (spi->cur_bpw == 16) { in stm32f4_spi_read_rx()
692 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs); in stm32f4_spi_read_rx()
694 *rx_buf16 = readw_relaxed(spi->base + STM32FX_SPI_DR); in stm32f4_spi_read_rx()
695 spi->rx_len -= sizeof(u16); in stm32f4_spi_read_rx()
697 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs); in stm32f4_spi_read_rx()
699 *rx_buf8 = readb_relaxed(spi->base + STM32FX_SPI_DR); in stm32f4_spi_read_rx()
700 spi->rx_len -= sizeof(u8); in stm32f4_spi_read_rx()
704 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->rx_len); in stm32f4_spi_read_rx()
714 static void stm32f7_spi_read_rx(struct stm32_spi *spi) in stm32f7_spi_read_rx() argument
716 u32 sr = readl_relaxed(spi->base + STM32FX_SPI_SR); in stm32f7_spi_read_rx()
719 while ((spi->rx_len > 0) && (frlvl > 0)) { in stm32f7_spi_read_rx()
720 u32 offs = spi->cur_xferlen - spi->rx_len; in stm32f7_spi_read_rx()
722 if ((spi->rx_len >= sizeof(u16)) && (frlvl >= 2)) { in stm32f7_spi_read_rx()
723 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs); in stm32f7_spi_read_rx()
725 *rx_buf16 = readw_relaxed(spi->base + STM32FX_SPI_DR); in stm32f7_spi_read_rx()
726 spi->rx_len -= sizeof(u16); in stm32f7_spi_read_rx()
728 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs); in stm32f7_spi_read_rx()
730 *rx_buf8 = readb_relaxed(spi->base + STM32FX_SPI_DR); in stm32f7_spi_read_rx()
731 spi->rx_len -= sizeof(u8); in stm32f7_spi_read_rx()
734 sr = readl_relaxed(spi->base + STM32FX_SPI_SR); in stm32f7_spi_read_rx()
738 if (spi->rx_len >= sizeof(u16)) in stm32f7_spi_read_rx()
739 stm32_spi_clr_bits(spi, STM32FX_SPI_CR2, STM32F7_SPI_CR2_FRXTH); in stm32f7_spi_read_rx()
741 stm32_spi_set_bits(spi, STM32FX_SPI_CR2, STM32F7_SPI_CR2_FRXTH); in stm32f7_spi_read_rx()
743 dev_dbg(spi->dev, "%s: %d bytes left (sr=%08x)\n", in stm32f7_spi_read_rx()
744 __func__, spi->rx_len, sr); in stm32f7_spi_read_rx()
754 static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi) in stm32h7_spi_read_rxfifo() argument
756 u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); in stm32h7_spi_read_rxfifo()
759 while ((spi->rx_len > 0) && in stm32h7_spi_read_rxfifo()
763 u32 offs = spi->cur_xferlen - spi->rx_len; in stm32h7_spi_read_rxfifo()
765 if ((spi->rx_len >= sizeof(u32)) || in stm32h7_spi_read_rxfifo()
767 u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs); in stm32h7_spi_read_rxfifo()
769 *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR); in stm32h7_spi_read_rxfifo()
770 spi->rx_len -= sizeof(u32); in stm32h7_spi_read_rxfifo()
771 } else if ((spi->rx_len >= sizeof(u16)) || in stm32h7_spi_read_rxfifo()
773 (rxplvl >= 2 || spi->cur_bpw > 8))) { in stm32h7_spi_read_rxfifo()
774 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs); in stm32h7_spi_read_rxfifo()
776 *rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR); in stm32h7_spi_read_rxfifo()
777 spi->rx_len -= sizeof(u16); in stm32h7_spi_read_rxfifo()
779 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs); in stm32h7_spi_read_rxfifo()
781 *rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR); in stm32h7_spi_read_rxfifo()
782 spi->rx_len -= sizeof(u8); in stm32h7_spi_read_rxfifo()
785 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); in stm32h7_spi_read_rxfifo()
789 dev_dbg(spi->dev, "%s: %d bytes left (sr=%08x)\n", in stm32h7_spi_read_rxfifo()
790 __func__, spi->rx_len, sr); in stm32h7_spi_read_rxfifo()
797 static void stm32_spi_enable(struct stm32_spi *spi) in stm32_spi_enable() argument
799 dev_dbg(spi->dev, "enable controller\n"); in stm32_spi_enable()
801 stm32_spi_set_bits(spi, spi->cfg->regs->en.reg, in stm32_spi_enable()
802 spi->cfg->regs->en.mask); in stm32_spi_enable()
809 static void stm32fx_spi_disable(struct stm32_spi *spi) in stm32fx_spi_disable() argument
814 dev_dbg(spi->dev, "disable controller\n"); in stm32fx_spi_disable()
816 spin_lock_irqsave(&spi->lock, flags); in stm32fx_spi_disable()
818 if (!(readl_relaxed(spi->base + STM32FX_SPI_CR1) & in stm32fx_spi_disable()
820 spin_unlock_irqrestore(&spi->lock, flags); in stm32fx_spi_disable()
825 stm32_spi_clr_bits(spi, STM32FX_SPI_CR2, STM32FX_SPI_CR2_TXEIE | in stm32fx_spi_disable()
830 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32FX_SPI_SR, in stm32fx_spi_disable()
833 dev_warn(spi->dev, "disabling condition timeout\n"); in stm32fx_spi_disable()
836 if (spi->cur_usedma && spi->dma_tx) in stm32fx_spi_disable()
837 dmaengine_terminate_async(spi->dma_tx); in stm32fx_spi_disable()
838 if (spi->cur_usedma && spi->dma_rx) in stm32fx_spi_disable()
839 dmaengine_terminate_async(spi->dma_rx); in stm32fx_spi_disable()
841 stm32_spi_clr_bits(spi, STM32FX_SPI_CR1, STM32FX_SPI_CR1_SPE); in stm32fx_spi_disable()
843 stm32_spi_clr_bits(spi, STM32FX_SPI_CR2, STM32FX_SPI_CR2_TXDMAEN | in stm32fx_spi_disable()
847 readl_relaxed(spi->base + STM32FX_SPI_DR); in stm32fx_spi_disable()
848 readl_relaxed(spi->base + STM32FX_SPI_SR); in stm32fx_spi_disable()
850 spin_unlock_irqrestore(&spi->lock, flags); in stm32fx_spi_disable()
859 static void stm32h7_spi_disable(struct stm32_spi *spi) in stm32h7_spi_disable() argument
864 dev_dbg(spi->dev, "disable controller\n"); in stm32h7_spi_disable()
866 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_disable()
868 cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1); in stm32h7_spi_disable()
871 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_disable()
876 if (spi->cur_half_period) in stm32h7_spi_disable()
877 udelay(spi->cur_half_period); in stm32h7_spi_disable()
879 if (spi->cur_usedma && spi->dma_tx) in stm32h7_spi_disable()
880 dmaengine_terminate_async(spi->dma_tx); in stm32h7_spi_disable()
881 if (spi->cur_usedma && spi->dma_rx) in stm32h7_spi_disable()
882 dmaengine_terminate_async(spi->dma_rx); in stm32h7_spi_disable()
884 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); in stm32h7_spi_disable()
886 stm32_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN | in stm32h7_spi_disable()
890 writel_relaxed(0, spi->base + STM32H7_SPI_IER); in stm32h7_spi_disable()
891 writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR); in stm32h7_spi_disable()
893 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_disable()
910 struct stm32_spi *spi = spi_controller_get_devdata(ctrl); in stm32_spi_can_dma() local
912 if (spi->cfg->has_fifo) in stm32_spi_can_dma()
913 dma_size = spi->fifo_size; in stm32_spi_can_dma()
917 dev_dbg(spi->dev, "%s: %s\n", __func__, in stm32_spi_can_dma()
931 struct stm32_spi *spi = spi_controller_get_devdata(ctrl); in stm32fx_spi_irq_event() local
935 spin_lock(&spi->lock); in stm32fx_spi_irq_event()
937 sr = readl_relaxed(spi->base + STM32FX_SPI_SR); in stm32fx_spi_irq_event()
944 if (!spi->cur_usedma && (spi->cur_comm == SPI_SIMPLEX_TX || in stm32fx_spi_irq_event()
945 spi->cur_comm == SPI_3WIRE_TX)) { in stm32fx_spi_irq_event()
951 if (!spi->cur_usedma && (spi->cur_comm == SPI_FULL_DUPLEX || in stm32fx_spi_irq_event()
952 spi->cur_comm == SPI_SIMPLEX_RX || in stm32fx_spi_irq_event()
953 spi->cur_comm == SPI_3WIRE_RX)) { in stm32fx_spi_irq_event()
960 dev_dbg(spi->dev, "spurious IT (sr=0x%08x)\n", sr); in stm32fx_spi_irq_event()
961 spin_unlock(&spi->lock); in stm32fx_spi_irq_event()
966 dev_warn(spi->dev, "Overrun: received value discarded\n"); in stm32fx_spi_irq_event()
969 readl_relaxed(spi->base + STM32FX_SPI_DR); in stm32fx_spi_irq_event()
970 readl_relaxed(spi->base + STM32FX_SPI_SR); in stm32fx_spi_irq_event()
982 if (spi->tx_buf) in stm32fx_spi_irq_event()
983 spi->cfg->write_tx(spi); in stm32fx_spi_irq_event()
984 if (spi->tx_len == 0) in stm32fx_spi_irq_event()
989 spi->cfg->read_rx(spi); in stm32fx_spi_irq_event()
990 if (spi->rx_len == 0) in stm32fx_spi_irq_event()
992 else if (spi->tx_buf)/* Load data for discontinuous mode */ in stm32fx_spi_irq_event()
993 spi->cfg->write_tx(spi); in stm32fx_spi_irq_event()
999 stm32_spi_clr_bits(spi, STM32FX_SPI_CR2, in stm32fx_spi_irq_event()
1003 spin_unlock(&spi->lock); in stm32fx_spi_irq_event()
1007 spin_unlock(&spi->lock); in stm32fx_spi_irq_event()
1019 struct stm32_spi *spi = spi_controller_get_devdata(ctrl); in stm32fx_spi_irq_thread() local
1022 stm32fx_spi_disable(spi); in stm32fx_spi_irq_thread()
1035 struct stm32_spi *spi = spi_controller_get_devdata(ctrl); in stm32h7_spi_irq_thread() local
1040 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_irq_thread()
1042 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); in stm32h7_spi_irq_thread()
1043 ier = readl_relaxed(spi->base + STM32H7_SPI_IER); in stm32h7_spi_irq_thread()
1056 if ((spi->cur_comm == SPI_FULL_DUPLEX) && !spi->cur_usedma) in stm32h7_spi_irq_thread()
1060 dev_vdbg(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n", in stm32h7_spi_irq_thread()
1062 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_irq_thread()
1072 dev_dbg_ratelimited(spi->dev, "Communication suspended\n"); in stm32h7_spi_irq_thread()
1073 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) in stm32h7_spi_irq_thread()
1074 stm32h7_spi_read_rxfifo(spi); in stm32h7_spi_irq_thread()
1079 if (spi->cur_usedma) in stm32h7_spi_irq_thread()
1084 dev_warn(spi->dev, "Mode fault: transfer aborted\n"); in stm32h7_spi_irq_thread()
1089 dev_err(spi->dev, "Overrun: RX data lost\n"); in stm32h7_spi_irq_thread()
1094 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) in stm32h7_spi_irq_thread()
1095 stm32h7_spi_read_rxfifo(spi); in stm32h7_spi_irq_thread()
1096 if (!spi->cur_usedma || in stm32h7_spi_irq_thread()
1097 (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX)) in stm32h7_spi_irq_thread()
1102 if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0))) in stm32h7_spi_irq_thread()
1103 stm32h7_spi_write_txfifo(spi); in stm32h7_spi_irq_thread()
1106 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) in stm32h7_spi_irq_thread()
1107 stm32h7_spi_read_rxfifo(spi); in stm32h7_spi_irq_thread()
1109 writel_relaxed(sr & mask, spi->base + STM32H7_SPI_IFCR); in stm32h7_spi_irq_thread()
1111 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_irq_thread()
1114 stm32h7_spi_disable(spi); in stm32h7_spi_irq_thread()
1123 struct spi_controller *ctrl = msg->spi->controller; in stm32_spi_optimize_message()
1124 struct stm32_spi *spi = spi_controller_get_devdata(ctrl); in stm32_spi_optimize_message() local
1130 if (spi->cfg->set_number_of_data) in stm32_spi_optimize_message()
1131 return spi_split_transfers_maxwords(ctrl, msg, spi->t_size_max); in stm32_spi_optimize_message()
1144 struct stm32_spi *spi = spi_controller_get_devdata(ctrl); in stm32_spi_prepare_msg() local
1145 struct spi_device *spi_dev = msg->spi; in stm32_spi_prepare_msg()
1151 spi->cur_midi = 0; in stm32_spi_prepare_msg()
1152 if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi)) in stm32_spi_prepare_msg()
1153 dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi); in stm32_spi_prepare_msg()
1156 setb |= spi->cfg->regs->cpol.mask; in stm32_spi_prepare_msg()
1158 clrb |= spi->cfg->regs->cpol.mask; in stm32_spi_prepare_msg()
1161 setb |= spi->cfg->regs->cpha.mask; in stm32_spi_prepare_msg()
1163 clrb |= spi->cfg->regs->cpha.mask; in stm32_spi_prepare_msg()
1166 setb |= spi->cfg->regs->lsb_first.mask; in stm32_spi_prepare_msg()
1168 clrb |= spi->cfg->regs->lsb_first.mask; in stm32_spi_prepare_msg()
1170 if (STM32_SPI_DEVICE_MODE(spi) && spi_dev->mode & SPI_CS_HIGH) in stm32_spi_prepare_msg()
1171 setb |= spi->cfg->regs->cs_high.mask; in stm32_spi_prepare_msg()
1173 clrb |= spi->cfg->regs->cs_high.mask; in stm32_spi_prepare_msg()
1175 dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n", in stm32_spi_prepare_msg()
1181 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_prepare_msg()
1186 (readl_relaxed(spi->base + spi->cfg->regs->cpol.reg) & in stm32_spi_prepare_msg()
1188 spi->base + spi->cfg->regs->cpol.reg); in stm32_spi_prepare_msg()
1190 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_prepare_msg()
1203 struct stm32_spi *spi = data; in stm32fx_spi_dma_tx_cb() local
1205 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) { in stm32fx_spi_dma_tx_cb()
1206 spi_finalize_current_transfer(spi->ctrl); in stm32fx_spi_dma_tx_cb()
1207 stm32fx_spi_disable(spi); in stm32fx_spi_dma_tx_cb()
1219 struct stm32_spi *spi = data; in stm32_spi_dma_rx_cb() local
1221 spi_finalize_current_transfer(spi->ctrl); in stm32_spi_dma_rx_cb()
1222 spi->cfg->disable(spi); in stm32_spi_dma_rx_cb()
1233 static void stm32_spi_dma_config(struct stm32_spi *spi, in stm32_spi_dma_config() argument
1243 if (spi->cur_bpw <= 8) in stm32_spi_dma_config()
1245 else if (spi->cur_bpw <= 16) in stm32_spi_dma_config()
1251 if (!spi->cfg->prevent_dma_burst && spi->cfg->has_fifo && spi->cur_fthlv != 2) in stm32_spi_dma_config()
1252 maxburst = spi->cur_fthlv; in stm32_spi_dma_config()
1262 dma_conf->src_addr = spi->phys_addr + spi->cfg->regs->rx.reg; in stm32_spi_dma_config()
1266 dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n", in stm32_spi_dma_config()
1269 dma_conf->dst_addr = spi->phys_addr + spi->cfg->regs->tx.reg; in stm32_spi_dma_config()
1273 dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n", in stm32_spi_dma_config()
1286 static int stm32fx_spi_transfer_one_irq(struct stm32_spi *spi) in stm32fx_spi_transfer_one_irq() argument
1292 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) { in stm32fx_spi_transfer_one_irq()
1294 } else if (spi->cur_comm == SPI_FULL_DUPLEX || in stm32fx_spi_transfer_one_irq()
1295 spi->cur_comm == SPI_SIMPLEX_RX || in stm32fx_spi_transfer_one_irq()
1296 spi->cur_comm == SPI_3WIRE_RX) { in stm32fx_spi_transfer_one_irq()
1306 spin_lock_irqsave(&spi->lock, flags); in stm32fx_spi_transfer_one_irq()
1308 stm32_spi_set_bits(spi, STM32FX_SPI_CR2, cr2); in stm32fx_spi_transfer_one_irq()
1310 stm32_spi_enable(spi); in stm32fx_spi_transfer_one_irq()
1313 if (spi->tx_buf) in stm32fx_spi_transfer_one_irq()
1314 spi->cfg->write_tx(spi); in stm32fx_spi_transfer_one_irq()
1316 spin_unlock_irqrestore(&spi->lock, flags); in stm32fx_spi_transfer_one_irq()
1329 static int stm32h7_spi_transfer_one_irq(struct stm32_spi *spi) in stm32h7_spi_transfer_one_irq() argument
1335 if (spi->tx_buf && spi->rx_buf) /* Full Duplex */ in stm32h7_spi_transfer_one_irq()
1337 else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */ in stm32h7_spi_transfer_one_irq()
1339 else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */ in stm32h7_spi_transfer_one_irq()
1346 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_transfer_one_irq()
1348 stm32_spi_enable(spi); in stm32h7_spi_transfer_one_irq()
1351 if (spi->tx_buf) in stm32h7_spi_transfer_one_irq()
1352 stm32h7_spi_write_txfifo(spi); in stm32h7_spi_transfer_one_irq()
1354 if (STM32_SPI_HOST_MODE(spi)) in stm32h7_spi_transfer_one_irq()
1355 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART); in stm32h7_spi_transfer_one_irq()
1357 writel_relaxed(ier, spi->base + STM32H7_SPI_IER); in stm32h7_spi_transfer_one_irq()
1359 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_transfer_one_irq()
1369 static void stm32fx_spi_transfer_one_dma_start(struct stm32_spi *spi) in stm32fx_spi_transfer_one_dma_start() argument
1372 if (spi->cur_comm == SPI_SIMPLEX_RX || spi->cur_comm == SPI_3WIRE_RX || in stm32fx_spi_transfer_one_dma_start()
1373 spi->cur_comm == SPI_FULL_DUPLEX) { in stm32fx_spi_transfer_one_dma_start()
1379 stm32_spi_set_bits(spi, STM32FX_SPI_CR2, STM32FX_SPI_CR2_ERRIE); in stm32fx_spi_transfer_one_dma_start()
1382 stm32_spi_enable(spi); in stm32fx_spi_transfer_one_dma_start()
1390 static void stm32f7_spi_transfer_one_dma_start(struct stm32_spi *spi) in stm32f7_spi_transfer_one_dma_start() argument
1393 if (spi->cur_bpw <= 8) in stm32f7_spi_transfer_one_dma_start()
1394 stm32_spi_set_bits(spi, STM32FX_SPI_CR2, STM32F7_SPI_CR2_FRXTH); in stm32f7_spi_transfer_one_dma_start()
1396 stm32_spi_clr_bits(spi, STM32FX_SPI_CR2, STM32F7_SPI_CR2_FRXTH); in stm32f7_spi_transfer_one_dma_start()
1398 stm32fx_spi_transfer_one_dma_start(spi); in stm32f7_spi_transfer_one_dma_start()
1406 static void stm32h7_spi_transfer_one_dma_start(struct stm32_spi *spi) in stm32h7_spi_transfer_one_dma_start() argument
1411 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) in stm32h7_spi_transfer_one_dma_start()
1414 stm32_spi_set_bits(spi, STM32H7_SPI_IER, ier); in stm32h7_spi_transfer_one_dma_start()
1416 stm32_spi_enable(spi); in stm32h7_spi_transfer_one_dma_start()
1418 if (STM32_SPI_HOST_MODE(spi)) in stm32h7_spi_transfer_one_dma_start()
1419 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART); in stm32h7_spi_transfer_one_dma_start()
1430 static int stm32_spi_transfer_one_dma(struct stm32_spi *spi, in stm32_spi_transfer_one_dma() argument
1437 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_transfer_one_dma()
1440 if (spi->rx_buf && spi->dma_rx) { in stm32_spi_transfer_one_dma()
1441 stm32_spi_dma_config(spi, spi->dma_rx, &rx_dma_conf, DMA_DEV_TO_MEM); in stm32_spi_transfer_one_dma()
1442 dmaengine_slave_config(spi->dma_rx, &rx_dma_conf); in stm32_spi_transfer_one_dma()
1445 stm32_spi_set_bits(spi, spi->cfg->regs->dma_rx_en.reg, in stm32_spi_transfer_one_dma()
1446 spi->cfg->regs->dma_rx_en.mask); in stm32_spi_transfer_one_dma()
1449 spi->dma_rx, xfer->rx_sg.sgl, in stm32_spi_transfer_one_dma()
1456 if (spi->tx_buf && spi->dma_tx) { in stm32_spi_transfer_one_dma()
1457 stm32_spi_dma_config(spi, spi->dma_tx, &tx_dma_conf, DMA_MEM_TO_DEV); in stm32_spi_transfer_one_dma()
1458 dmaengine_slave_config(spi->dma_tx, &tx_dma_conf); in stm32_spi_transfer_one_dma()
1461 spi->dma_tx, xfer->tx_sg.sgl, in stm32_spi_transfer_one_dma()
1467 if ((spi->tx_buf && spi->dma_tx && !tx_dma_desc) || in stm32_spi_transfer_one_dma()
1468 (spi->rx_buf && spi->dma_rx && !rx_dma_desc)) in stm32_spi_transfer_one_dma()
1471 if (spi->cur_comm == SPI_FULL_DUPLEX && (!tx_dma_desc || !rx_dma_desc)) in stm32_spi_transfer_one_dma()
1475 rx_dma_desc->callback = spi->cfg->dma_rx_cb; in stm32_spi_transfer_one_dma()
1476 rx_dma_desc->callback_param = spi; in stm32_spi_transfer_one_dma()
1479 dev_err(spi->dev, "Rx DMA submit failed\n"); in stm32_spi_transfer_one_dma()
1483 dma_async_issue_pending(spi->dma_rx); in stm32_spi_transfer_one_dma()
1487 if (spi->cur_comm == SPI_SIMPLEX_TX || in stm32_spi_transfer_one_dma()
1488 spi->cur_comm == SPI_3WIRE_TX) { in stm32_spi_transfer_one_dma()
1489 tx_dma_desc->callback = spi->cfg->dma_tx_cb; in stm32_spi_transfer_one_dma()
1490 tx_dma_desc->callback_param = spi; in stm32_spi_transfer_one_dma()
1494 dev_err(spi->dev, "Tx DMA submit failed\n"); in stm32_spi_transfer_one_dma()
1498 dma_async_issue_pending(spi->dma_tx); in stm32_spi_transfer_one_dma()
1501 stm32_spi_set_bits(spi, spi->cfg->regs->dma_tx_en.reg, in stm32_spi_transfer_one_dma()
1502 spi->cfg->regs->dma_tx_en.mask); in stm32_spi_transfer_one_dma()
1505 spi->cfg->transfer_one_dma_start(spi); in stm32_spi_transfer_one_dma()
1507 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_transfer_one_dma()
1512 if (spi->dma_rx) in stm32_spi_transfer_one_dma()
1513 dmaengine_terminate_sync(spi->dma_rx); in stm32_spi_transfer_one_dma()
1516 stm32_spi_clr_bits(spi, spi->cfg->regs->dma_rx_en.reg, in stm32_spi_transfer_one_dma()
1517 spi->cfg->regs->dma_rx_en.mask); in stm32_spi_transfer_one_dma()
1519 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_transfer_one_dma()
1521 dev_info(spi->dev, "DMA issue: fall back to irq transfer\n"); in stm32_spi_transfer_one_dma()
1523 spi->cur_usedma = false; in stm32_spi_transfer_one_dma()
1524 return spi->cfg->transfer_one_irq(spi); in stm32_spi_transfer_one_dma()
1531 static void stm32f4_spi_set_bpw(struct stm32_spi *spi) in stm32f4_spi_set_bpw() argument
1533 if (spi->cur_bpw == 16) in stm32f4_spi_set_bpw()
1534 stm32_spi_set_bits(spi, STM32FX_SPI_CR1, STM32F4_SPI_CR1_DFF); in stm32f4_spi_set_bpw()
1536 stm32_spi_clr_bits(spi, STM32FX_SPI_CR1, STM32F4_SPI_CR1_DFF); in stm32f4_spi_set_bpw()
1543 static void stm32f7_spi_set_bpw(struct stm32_spi *spi) in stm32f7_spi_set_bpw() argument
1548 bpw = spi->cur_bpw - 1; in stm32f7_spi_set_bpw()
1553 if (spi->rx_len >= sizeof(u16)) in stm32f7_spi_set_bpw()
1559 (readl_relaxed(spi->base + STM32FX_SPI_CR2) & in stm32f7_spi_set_bpw()
1561 spi->base + STM32FX_SPI_CR2); in stm32f7_spi_set_bpw()
1568 static void stm32h7_spi_set_bpw(struct stm32_spi *spi) in stm32h7_spi_set_bpw() argument
1573 bpw = spi->cur_bpw - 1; in stm32h7_spi_set_bpw()
1578 spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen); in stm32h7_spi_set_bpw()
1579 fthlv = spi->cur_fthlv - 1; in stm32h7_spi_set_bpw()
1585 (readl_relaxed(spi->base + STM32H7_SPI_CFG1) & in stm32h7_spi_set_bpw()
1587 spi->base + STM32H7_SPI_CFG1); in stm32h7_spi_set_bpw()
1595 static void stm32_spi_set_mbr(struct stm32_spi *spi, u32 mbrdiv) in stm32_spi_set_mbr() argument
1599 clrb |= spi->cfg->regs->br.mask; in stm32_spi_set_mbr()
1600 setb |= (mbrdiv << spi->cfg->regs->br.shift) & spi->cfg->regs->br.mask; in stm32_spi_set_mbr()
1602 writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) & in stm32_spi_set_mbr()
1604 spi->base + spi->cfg->regs->br.reg); in stm32_spi_set_mbr()
1643 static int stm32fx_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type) in stm32fx_spi_set_mode() argument
1646 stm32_spi_set_bits(spi, STM32FX_SPI_CR1, in stm32fx_spi_set_mode()
1651 stm32_spi_clr_bits(spi, STM32FX_SPI_CR1, in stm32fx_spi_set_mode()
1655 stm32_spi_set_bits(spi, STM32FX_SPI_CR1, in stm32fx_spi_set_mode()
1657 stm32_spi_clr_bits(spi, STM32FX_SPI_CR1, in stm32fx_spi_set_mode()
1671 static int stm32h7_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type) in stm32h7_spi_set_mode() argument
1678 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR); in stm32h7_spi_set_mode()
1681 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR); in stm32h7_spi_set_mode()
1694 (readl_relaxed(spi->base + STM32H7_SPI_CFG2) & in stm32h7_spi_set_mode()
1696 spi->base + STM32H7_SPI_CFG2); in stm32h7_spi_set_mode()
1707 static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len) in stm32h7_spi_data_idleness() argument
1712 if ((len > 1) && (spi->cur_midi > 0)) { in stm32h7_spi_data_idleness()
1713 u32 sck_period_ns = DIV_ROUND_UP(NSEC_PER_SEC, spi->cur_speed); in stm32h7_spi_data_idleness()
1715 DIV_ROUND_UP(spi->cur_midi, sck_period_ns), in stm32h7_spi_data_idleness()
1720 dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n", in stm32h7_spi_data_idleness()
1725 writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) & in stm32h7_spi_data_idleness()
1727 spi->base + STM32H7_SPI_CFG2); in stm32h7_spi_data_idleness()
1735 static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words) in stm32h7_spi_number_of_data() argument
1737 if (nb_words <= spi->t_size_max) { in stm32h7_spi_number_of_data()
1739 spi->base + STM32H7_SPI_CR2); in stm32h7_spi_number_of_data()
1755 static int stm32_spi_transfer_one_setup(struct stm32_spi *spi, in stm32_spi_transfer_one_setup() argument
1764 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_transfer_one_setup()
1766 spi->cur_xferlen = transfer->len; in stm32_spi_transfer_one_setup()
1768 spi->cur_bpw = transfer->bits_per_word; in stm32_spi_transfer_one_setup()
1769 spi->cfg->set_bpw(spi); in stm32_spi_transfer_one_setup()
1772 if (STM32_SPI_HOST_MODE(spi)) { in stm32_spi_transfer_one_setup()
1773 mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz, in stm32_spi_transfer_one_setup()
1774 spi->cfg->baud_rate_div_min, in stm32_spi_transfer_one_setup()
1775 spi->cfg->baud_rate_div_max); in stm32_spi_transfer_one_setup()
1781 transfer->speed_hz = spi->cur_speed; in stm32_spi_transfer_one_setup()
1782 stm32_spi_set_mbr(spi, mbr); in stm32_spi_transfer_one_setup()
1786 ret = spi->cfg->set_mode(spi, comm_type); in stm32_spi_transfer_one_setup()
1790 spi->cur_comm = comm_type; in stm32_spi_transfer_one_setup()
1792 if (STM32_SPI_HOST_MODE(spi) && spi->cfg->set_data_idleness) in stm32_spi_transfer_one_setup()
1793 spi->cfg->set_data_idleness(spi, transfer->len); in stm32_spi_transfer_one_setup()
1795 if (spi->cur_bpw <= 8) in stm32_spi_transfer_one_setup()
1797 else if (spi->cur_bpw <= 16) in stm32_spi_transfer_one_setup()
1802 if (spi->cfg->set_number_of_data) { in stm32_spi_transfer_one_setup()
1803 ret = spi->cfg->set_number_of_data(spi, nb_words); in stm32_spi_transfer_one_setup()
1808 dev_dbg(spi->dev, "transfer communication mode set to %d\n", in stm32_spi_transfer_one_setup()
1809 spi->cur_comm); in stm32_spi_transfer_one_setup()
1810 dev_dbg(spi->dev, in stm32_spi_transfer_one_setup()
1812 spi->cur_bpw, spi->cur_fthlv); in stm32_spi_transfer_one_setup()
1813 if (STM32_SPI_HOST_MODE(spi)) in stm32_spi_transfer_one_setup()
1814 dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed); in stm32_spi_transfer_one_setup()
1815 dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n", in stm32_spi_transfer_one_setup()
1816 spi->cur_xferlen, nb_words); in stm32_spi_transfer_one_setup()
1817 dev_dbg(spi->dev, "dma %s\n", in stm32_spi_transfer_one_setup()
1818 (spi->cur_usedma) ? "enabled" : "disabled"); in stm32_spi_transfer_one_setup()
1821 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_transfer_one_setup()
1839 struct stm32_spi *spi = spi_controller_get_devdata(ctrl); in stm32_spi_transfer_one() local
1842 spi->tx_buf = transfer->tx_buf; in stm32_spi_transfer_one()
1843 spi->rx_buf = transfer->rx_buf; in stm32_spi_transfer_one()
1844 spi->tx_len = spi->tx_buf ? transfer->len : 0; in stm32_spi_transfer_one()
1845 spi->rx_len = spi->rx_buf ? transfer->len : 0; in stm32_spi_transfer_one()
1847 spi->cur_usedma = (ctrl->can_dma && in stm32_spi_transfer_one()
1850 ret = stm32_spi_transfer_one_setup(spi, spi_dev, transfer); in stm32_spi_transfer_one()
1852 dev_err(spi->dev, "SPI transfer setup failed\n"); in stm32_spi_transfer_one()
1856 if (spi->cur_usedma) in stm32_spi_transfer_one()
1857 return stm32_spi_transfer_one_dma(spi, transfer); in stm32_spi_transfer_one()
1859 return spi->cfg->transfer_one_irq(spi); in stm32_spi_transfer_one()
1870 struct stm32_spi *spi = spi_controller_get_devdata(ctrl); in stm32_spi_unprepare_msg() local
1872 spi->cfg->disable(spi); in stm32_spi_unprepare_msg()
1881 static int stm32fx_spi_config(struct stm32_spi *spi) in stm32fx_spi_config() argument
1885 spin_lock_irqsave(&spi->lock, flags); in stm32fx_spi_config()
1888 stm32_spi_clr_bits(spi, STM32FX_SPI_I2SCFGR, in stm32fx_spi_config()
1898 stm32_spi_set_bits(spi, STM32FX_SPI_CR1, STM32FX_SPI_CR1_SSI | in stm32fx_spi_config()
1903 spin_unlock_irqrestore(&spi->lock, flags); in stm32fx_spi_config()
1912 static int stm32h7_spi_config(struct stm32_spi *spi) in stm32h7_spi_config() argument
1917 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_config()
1920 stm32_spi_clr_bits(spi, STM32H7_SPI_I2SCFGR, in stm32h7_spi_config()
1923 if (STM32_SPI_DEVICE_MODE(spi)) { in stm32h7_spi_config()
1943 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, cr1); in stm32h7_spi_config()
1944 stm32_spi_set_bits(spi, STM32H7_SPI_CFG2, cfg2); in stm32h7_spi_config()
1946 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_config()
2068 struct stm32_spi *spi; in stm32_spi_probe() local
2092 spi = spi_controller_get_devdata(ctrl); in stm32_spi_probe()
2093 spi->dev = &pdev->dev; in stm32_spi_probe()
2094 spi->ctrl = ctrl; in stm32_spi_probe()
2095 spi->device_mode = device_mode; in stm32_spi_probe()
2096 spin_lock_init(&spi->lock); in stm32_spi_probe()
2098 spi->cfg = cfg; in stm32_spi_probe()
2100 spi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in stm32_spi_probe()
2101 if (IS_ERR(spi->base)) in stm32_spi_probe()
2102 return PTR_ERR(spi->base); in stm32_spi_probe()
2104 spi->phys_addr = (dma_addr_t)res->start; in stm32_spi_probe()
2106 spi->irq = platform_get_irq(pdev, 0); in stm32_spi_probe()
2107 if (spi->irq <= 0) in stm32_spi_probe()
2108 return spi->irq; in stm32_spi_probe()
2110 ret = devm_request_threaded_irq(&pdev->dev, spi->irq, in stm32_spi_probe()
2111 spi->cfg->irq_handler_event, in stm32_spi_probe()
2112 spi->cfg->irq_handler_thread, in stm32_spi_probe()
2115 dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq, in stm32_spi_probe()
2120 spi->clk = devm_clk_get(&pdev->dev, NULL); in stm32_spi_probe()
2121 if (IS_ERR(spi->clk)) { in stm32_spi_probe()
2122 ret = PTR_ERR(spi->clk); in stm32_spi_probe()
2127 ret = clk_prepare_enable(spi->clk); in stm32_spi_probe()
2132 spi->clk_rate = clk_get_rate(spi->clk); in stm32_spi_probe()
2133 if (!spi->clk_rate) { in stm32_spi_probe()
2152 if (spi->cfg->has_fifo) in stm32_spi_probe()
2153 spi->fifo_size = spi->cfg->get_fifo_size(spi); in stm32_spi_probe()
2155 spi->feature_set = STM32_SPI_FEATURE_FULL; in stm32_spi_probe()
2156 if (spi->cfg->regs->fullcfg.reg) { in stm32_spi_probe()
2157 spi->feature_set = in stm32_spi_probe()
2159 readl_relaxed(spi->base + spi->cfg->regs->fullcfg.reg)); in stm32_spi_probe()
2161 dev_dbg(spi->dev, "%s feature set\n", in stm32_spi_probe()
2162 spi->feature_set == STM32_SPI_FEATURE_FULL ? "full" : "limited"); in stm32_spi_probe()
2166 spi->t_size_max = spi->feature_set == STM32_SPI_FEATURE_FULL ? in stm32_spi_probe()
2169 dev_dbg(spi->dev, "one message max size %d\n", spi->t_size_max); in stm32_spi_probe()
2171 ret = spi->cfg->config(spi); in stm32_spi_probe()
2183 ctrl->bits_per_word_mask = spi->cfg->get_bpw_mask(spi); in stm32_spi_probe()
2184 ctrl->max_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_min; in stm32_spi_probe()
2185 ctrl->min_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_max; in stm32_spi_probe()
2191 ctrl->flags = spi->cfg->flags; in stm32_spi_probe()
2192 if (STM32_SPI_DEVICE_MODE(spi)) in stm32_spi_probe()
2195 spi->dma_tx = dma_request_chan(spi->dev, "tx"); in stm32_spi_probe()
2196 if (IS_ERR(spi->dma_tx)) { in stm32_spi_probe()
2197 ret = PTR_ERR(spi->dma_tx); in stm32_spi_probe()
2198 spi->dma_tx = NULL; in stm32_spi_probe()
2204 ctrl->dma_tx = spi->dma_tx; in stm32_spi_probe()
2207 spi->dma_rx = dma_request_chan(spi->dev, "rx"); in stm32_spi_probe()
2208 if (IS_ERR(spi->dma_rx)) { in stm32_spi_probe()
2209 ret = PTR_ERR(spi->dma_rx); in stm32_spi_probe()
2210 spi->dma_rx = NULL; in stm32_spi_probe()
2216 ctrl->dma_rx = spi->dma_rx; in stm32_spi_probe()
2219 if (spi->dma_tx || spi->dma_rx) in stm32_spi_probe()
2240 STM32_SPI_HOST_MODE(spi) ? "host" : "device"); in stm32_spi_probe()
2250 if (spi->dma_tx) in stm32_spi_probe()
2251 dma_release_channel(spi->dma_tx); in stm32_spi_probe()
2252 if (spi->dma_rx) in stm32_spi_probe()
2253 dma_release_channel(spi->dma_rx); in stm32_spi_probe()
2255 clk_disable_unprepare(spi->clk); in stm32_spi_probe()
2263 struct stm32_spi *spi = spi_controller_get_devdata(ctrl); in stm32_spi_remove() local
2268 spi->cfg->disable(spi); in stm32_spi_remove()
2280 clk_disable_unprepare(spi->clk); in stm32_spi_remove()
2289 struct stm32_spi *spi = spi_controller_get_devdata(ctrl); in stm32_spi_runtime_suspend() local
2291 clk_disable_unprepare(spi->clk); in stm32_spi_runtime_suspend()
2299 struct stm32_spi *spi = spi_controller_get_devdata(ctrl); in stm32_spi_runtime_resume() local
2306 return clk_prepare_enable(spi->clk); in stm32_spi_runtime_resume()
2324 struct stm32_spi *spi = spi_controller_get_devdata(ctrl); in stm32_spi_resume() local
2333 clk_disable_unprepare(spi->clk); in stm32_spi_resume()
2343 spi->cfg->config(spi); in stm32_spi_resume()