Lines Matching +full:controller +full:- +full:data
1 // SPDX-License-Identifier: GPL-2.0
3 // STMicroelectronics STM32 SPI Controller driver
5 // Copyright (C) 2017, STMicroelectronics - All Rights Reserved
197 #define STM32_SPI_HOST_MODE(stm32_spi) (!(stm32_spi)->device_mode)
198 #define STM32_SPI_DEVICE_MODE(stm32_spi) ((stm32_spi)->device_mode)
201 * struct stm32_spi_reg - stm32 SPI register & bitfield desc
213 * struct stm32_spi_regspec - stm32 registers definition, compatible dependent data
222 * @rx: SPI RX data register
223 * @tx: SPI TX data register
243 * struct stm32_spi_cfg - stm32 compatible configuration data
247 * @disable: routine to disable controller
248 * @config: routine to configure controller as SPI Host
254 * number of data (if driver has this functionality)
262 * @irq_handler_event: Interrupt handler for SPI controller events
263 * @irq_handler_thread: thread of interrupt handler for SPI controller
268 * @flags: compatible specific SPI controller flags used at registration time
284 void (*dma_rx_cb)(void *data);
285 void (*dma_tx_cb)(void *data);
298 * struct stm32_spi - private data of the SPI controller
299 * @dev: driver model representation of the controller
300 * @ctrl: controller interface
301 * @cfg: compatible configuration data
306 * @irq: SPI controller interrupt line
308 * @t_size_max: maximum number of data of one transfer
310 * @cur_midi: host inter-data idleness in ns
313 * @cur_bpw: number of bits in a single SPI data frame
314 * @cur_fthlv: fifo threshold level (data frames in a single data packet)
318 * @tx_buf: data to be written, or NULL
319 * @rx_buf: data to be read, or NULL
320 * @tx_len: number of data to be written in bytes
321 * @rx_len: number of data to be read in bytes
325 * @device_mode: the controller is configured as SPI device
379 /* SPI data transfer is enabled but spi_ker_ck is idle.
399 /* SPI data transfer is enabled but spi_ker_ck is idle.
423 writel_relaxed(readl_relaxed(spi->base + offset) | bits, in stm32_spi_set_bits()
424 spi->base + offset); in stm32_spi_set_bits()
430 writel_relaxed(readl_relaxed(spi->base + offset) & ~bits, in stm32_spi_clr_bits()
431 spi->base + offset); in stm32_spi_clr_bits()
435 * stm32h7_spi_get_fifo_size - Return fifo size
436 * @spi: pointer to the spi controller data structure
443 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_get_fifo_size()
447 while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP) in stm32h7_spi_get_fifo_size()
448 writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_get_fifo_size()
452 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_get_fifo_size()
454 dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count); in stm32h7_spi_get_fifo_size()
460 * stm32f4_spi_get_bpw_mask - Return bits per word mask
461 * @spi: pointer to the spi controller data structure
465 dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n"); in stm32f4_spi_get_bpw_mask()
470 * stm32f7_spi_get_bpw_mask - Return bits per word mask
471 * @spi: pointer to the spi controller data structure
475 dev_dbg(spi->dev, "16-bit maximum data frame\n"); in stm32f7_spi_get_bpw_mask()
480 * stm32h7_spi_get_bpw_mask - Return bits per word mask
481 * @spi: pointer to the spi controller data structure
488 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_get_bpw_mask()
492 * maximum data size of periperal instances is limited to 16-bit in stm32h7_spi_get_bpw_mask()
496 cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1); in stm32h7_spi_get_bpw_mask()
499 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_get_bpw_mask()
501 dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw); in stm32h7_spi_get_bpw_mask()
507 * stm32mp25_spi_get_bpw_mask - Return bits per word mask
508 * @spi: pointer to the spi controller data structure
514 if (spi->feature_set == STM32_SPI_FEATURE_LIMITED) { in stm32mp25_spi_get_bpw_mask()
515 dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n"); in stm32mp25_spi_get_bpw_mask()
520 readl_relaxed(spi->base + STM32MP25_SPI_HWCFGR1)); in stm32mp25_spi_get_bpw_mask()
524 dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw); in stm32mp25_spi_get_bpw_mask()
529 * stm32_spi_prepare_mbr - Determine baud rate divisor value
530 * @spi: pointer to the spi controller data structure
535 * Return baud rate divisor value in case of success or -EINVAL
542 /* Ensure spi->clk_rate is even */ in stm32_spi_prepare_mbr()
543 div = DIV_ROUND_CLOSEST(spi->clk_rate & ~0x1, speed_hz); in stm32_spi_prepare_mbr()
546 * SPI framework set xfer->speed_hz to ctrl->max_speed_hz if in stm32_spi_prepare_mbr()
547 * xfer->speed_hz is greater than ctrl->max_speed_hz, and it returns in stm32_spi_prepare_mbr()
548 * an error when xfer->speed_hz is lower than ctrl->min_speed_hz, so in stm32_spi_prepare_mbr()
553 return -EINVAL; in stm32_spi_prepare_mbr()
556 if (div & (div - 1)) in stm32_spi_prepare_mbr()
559 mbrdiv = fls(div) - 1; in stm32_spi_prepare_mbr()
561 spi->cur_speed = spi->clk_rate / (1 << mbrdiv); in stm32_spi_prepare_mbr()
563 spi->cur_half_period = DIV_ROUND_CLOSEST(USEC_PER_SEC, 2 * spi->cur_speed); in stm32_spi_prepare_mbr()
565 return mbrdiv - 1; in stm32_spi_prepare_mbr()
569 * stm32h7_spi_prepare_fthlv - Determine FIFO threshold level
570 * @spi: pointer to the spi controller data structure
577 /* data packet should not exceed 1/2 of fifo space */ in stm32h7_spi_prepare_fthlv()
578 packet = clamp(xfer_len, 1U, spi->fifo_size / 2); in stm32h7_spi_prepare_fthlv()
580 /* align packet size with data registers access */ in stm32h7_spi_prepare_fthlv()
581 bpw = DIV_ROUND_UP(spi->cur_bpw, 8); in stm32h7_spi_prepare_fthlv()
586 * stm32f4_spi_write_tx - Write bytes to Transmit Data Register
587 * @spi: pointer to the spi controller data structure
594 if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32FX_SPI_SR) & in stm32f4_spi_write_tx()
596 u32 offs = spi->cur_xferlen - spi->tx_len; in stm32f4_spi_write_tx()
598 if (spi->cur_bpw == 16) { in stm32f4_spi_write_tx()
599 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs); in stm32f4_spi_write_tx()
601 writew_relaxed(*tx_buf16, spi->base + STM32FX_SPI_DR); in stm32f4_spi_write_tx()
602 spi->tx_len -= sizeof(u16); in stm32f4_spi_write_tx()
604 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs); in stm32f4_spi_write_tx()
606 writeb_relaxed(*tx_buf8, spi->base + STM32FX_SPI_DR); in stm32f4_spi_write_tx()
607 spi->tx_len -= sizeof(u8); in stm32f4_spi_write_tx()
611 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len); in stm32f4_spi_write_tx()
615 * stm32f7_spi_write_tx - Write bytes to Transmit Data Register
616 * @spi: pointer to the spi controller data structure
623 if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32FX_SPI_SR) & in stm32f7_spi_write_tx()
625 u32 offs = spi->cur_xferlen - spi->tx_len; in stm32f7_spi_write_tx()
627 if (spi->tx_len >= sizeof(u16)) { in stm32f7_spi_write_tx()
628 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs); in stm32f7_spi_write_tx()
630 writew_relaxed(*tx_buf16, spi->base + STM32FX_SPI_DR); in stm32f7_spi_write_tx()
631 spi->tx_len -= sizeof(u16); in stm32f7_spi_write_tx()
633 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs); in stm32f7_spi_write_tx()
635 writeb_relaxed(*tx_buf8, spi->base + STM32FX_SPI_DR); in stm32f7_spi_write_tx()
636 spi->tx_len -= sizeof(u8); in stm32f7_spi_write_tx()
640 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len); in stm32f7_spi_write_tx()
644 * stm32h7_spi_write_txfifo - Write bytes in Transmit Data Register
645 * @spi: pointer to the spi controller data structure
652 while ((spi->tx_len > 0) && in stm32h7_spi_write_txfifo()
653 (readl_relaxed(spi->base + STM32H7_SPI_SR) & in stm32h7_spi_write_txfifo()
655 u32 offs = spi->cur_xferlen - spi->tx_len; in stm32h7_spi_write_txfifo()
657 if (spi->tx_len >= sizeof(u32)) { in stm32h7_spi_write_txfifo()
658 const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs); in stm32h7_spi_write_txfifo()
660 writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_write_txfifo()
661 spi->tx_len -= sizeof(u32); in stm32h7_spi_write_txfifo()
662 } else if (spi->tx_len >= sizeof(u16)) { in stm32h7_spi_write_txfifo()
663 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs); in stm32h7_spi_write_txfifo()
665 writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_write_txfifo()
666 spi->tx_len -= sizeof(u16); in stm32h7_spi_write_txfifo()
668 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs); in stm32h7_spi_write_txfifo()
670 writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_write_txfifo()
671 spi->tx_len -= sizeof(u8); in stm32h7_spi_write_txfifo()
675 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len); in stm32h7_spi_write_txfifo()
679 * stm32f4_spi_read_rx - Read bytes from Receive Data Register
680 * @spi: pointer to the spi controller data structure
687 if ((spi->rx_len > 0) && (readl_relaxed(spi->base + STM32FX_SPI_SR) & in stm32f4_spi_read_rx()
689 u32 offs = spi->cur_xferlen - spi->rx_len; in stm32f4_spi_read_rx()
691 if (spi->cur_bpw == 16) { in stm32f4_spi_read_rx()
692 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs); in stm32f4_spi_read_rx()
694 *rx_buf16 = readw_relaxed(spi->base + STM32FX_SPI_DR); in stm32f4_spi_read_rx()
695 spi->rx_len -= sizeof(u16); in stm32f4_spi_read_rx()
697 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs); in stm32f4_spi_read_rx()
699 *rx_buf8 = readb_relaxed(spi->base + STM32FX_SPI_DR); in stm32f4_spi_read_rx()
700 spi->rx_len -= sizeof(u8); in stm32f4_spi_read_rx()
704 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->rx_len); in stm32f4_spi_read_rx()
708 * stm32f7_spi_read_rx - Read bytes from Receive Data Register
709 * @spi: pointer to the spi controller data structure
716 u32 sr = readl_relaxed(spi->base + STM32FX_SPI_SR); in stm32f7_spi_read_rx()
719 while ((spi->rx_len > 0) && (frlvl > 0)) { in stm32f7_spi_read_rx()
720 u32 offs = spi->cur_xferlen - spi->rx_len; in stm32f7_spi_read_rx()
722 if ((spi->rx_len >= sizeof(u16)) && (frlvl >= 2)) { in stm32f7_spi_read_rx()
723 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs); in stm32f7_spi_read_rx()
725 *rx_buf16 = readw_relaxed(spi->base + STM32FX_SPI_DR); in stm32f7_spi_read_rx()
726 spi->rx_len -= sizeof(u16); in stm32f7_spi_read_rx()
728 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs); in stm32f7_spi_read_rx()
730 *rx_buf8 = readb_relaxed(spi->base + STM32FX_SPI_DR); in stm32f7_spi_read_rx()
731 spi->rx_len -= sizeof(u8); in stm32f7_spi_read_rx()
734 sr = readl_relaxed(spi->base + STM32FX_SPI_SR); in stm32f7_spi_read_rx()
738 if (spi->rx_len >= sizeof(u16)) in stm32f7_spi_read_rx()
743 dev_dbg(spi->dev, "%s: %d bytes left (sr=%08x)\n", in stm32f7_spi_read_rx()
744 __func__, spi->rx_len, sr); in stm32f7_spi_read_rx()
748 * stm32h7_spi_read_rxfifo - Read bytes in Receive Data Register
749 * @spi: pointer to the spi controller data structure
756 u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); in stm32h7_spi_read_rxfifo()
759 while ((spi->rx_len > 0) && in stm32h7_spi_read_rxfifo()
763 u32 offs = spi->cur_xferlen - spi->rx_len; in stm32h7_spi_read_rxfifo()
765 if ((spi->rx_len >= sizeof(u32)) || in stm32h7_spi_read_rxfifo()
767 u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs); in stm32h7_spi_read_rxfifo()
769 *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR); in stm32h7_spi_read_rxfifo()
770 spi->rx_len -= sizeof(u32); in stm32h7_spi_read_rxfifo()
771 } else if ((spi->rx_len >= sizeof(u16)) || in stm32h7_spi_read_rxfifo()
773 (rxplvl >= 2 || spi->cur_bpw > 8))) { in stm32h7_spi_read_rxfifo()
774 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs); in stm32h7_spi_read_rxfifo()
776 *rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR); in stm32h7_spi_read_rxfifo()
777 spi->rx_len -= sizeof(u16); in stm32h7_spi_read_rxfifo()
779 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs); in stm32h7_spi_read_rxfifo()
781 *rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR); in stm32h7_spi_read_rxfifo()
782 spi->rx_len -= sizeof(u8); in stm32h7_spi_read_rxfifo()
785 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); in stm32h7_spi_read_rxfifo()
789 dev_dbg(spi->dev, "%s: %d bytes left (sr=%08x)\n", in stm32h7_spi_read_rxfifo()
790 __func__, spi->rx_len, sr); in stm32h7_spi_read_rxfifo()
794 * stm32_spi_enable - Enable SPI controller
795 * @spi: pointer to the spi controller data structure
799 dev_dbg(spi->dev, "enable controller\n"); in stm32_spi_enable()
801 stm32_spi_set_bits(spi, spi->cfg->regs->en.reg, in stm32_spi_enable()
802 spi->cfg->regs->en.mask); in stm32_spi_enable()
806 * stm32fx_spi_disable - Disable SPI controller
807 * @spi: pointer to the spi controller data structure
814 dev_dbg(spi->dev, "disable controller\n"); in stm32fx_spi_disable()
816 spin_lock_irqsave(&spi->lock, flags); in stm32fx_spi_disable()
818 if (!(readl_relaxed(spi->base + STM32FX_SPI_CR1) & in stm32fx_spi_disable()
820 spin_unlock_irqrestore(&spi->lock, flags); in stm32fx_spi_disable()
830 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32FX_SPI_SR, in stm32fx_spi_disable()
833 dev_warn(spi->dev, "disabling condition timeout\n"); in stm32fx_spi_disable()
836 if (spi->cur_usedma && spi->dma_tx) in stm32fx_spi_disable()
837 dmaengine_terminate_async(spi->dma_tx); in stm32fx_spi_disable()
838 if (spi->cur_usedma && spi->dma_rx) in stm32fx_spi_disable()
839 dmaengine_terminate_async(spi->dma_rx); in stm32fx_spi_disable()
847 readl_relaxed(spi->base + STM32FX_SPI_DR); in stm32fx_spi_disable()
848 readl_relaxed(spi->base + STM32FX_SPI_SR); in stm32fx_spi_disable()
850 spin_unlock_irqrestore(&spi->lock, flags); in stm32fx_spi_disable()
854 * stm32h7_spi_disable - Disable SPI controller
855 * @spi: pointer to the spi controller data structure
857 * RX-Fifo is flushed when SPI controller is disabled.
864 dev_dbg(spi->dev, "disable controller\n"); in stm32h7_spi_disable()
866 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_disable()
868 cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1); in stm32h7_spi_disable()
871 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_disable()
876 if (spi->cur_half_period) in stm32h7_spi_disable()
877 udelay(spi->cur_half_period); in stm32h7_spi_disable()
879 if (spi->cur_usedma && spi->dma_tx) in stm32h7_spi_disable()
880 dmaengine_terminate_async(spi->dma_tx); in stm32h7_spi_disable()
881 if (spi->cur_usedma && spi->dma_rx) in stm32h7_spi_disable()
882 dmaengine_terminate_async(spi->dma_rx); in stm32h7_spi_disable()
890 writel_relaxed(0, spi->base + STM32H7_SPI_IER); in stm32h7_spi_disable()
891 writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR); in stm32h7_spi_disable()
893 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_disable()
897 * stm32_spi_can_dma - Determine if the transfer is eligible for DMA use
898 * @ctrl: controller interface
912 if (spi->cfg->has_fifo) in stm32_spi_can_dma()
913 dma_size = spi->fifo_size; in stm32_spi_can_dma()
917 dev_dbg(spi->dev, "%s: %s\n", __func__, in stm32_spi_can_dma()
918 (transfer->len > dma_size) ? "true" : "false"); in stm32_spi_can_dma()
920 return (transfer->len > dma_size); in stm32_spi_can_dma()
924 * stm32fx_spi_irq_event - Interrupt handler for SPI controller events
926 * @dev_id: SPI controller ctrl interface
935 spin_lock(&spi->lock); in stm32fx_spi_irq_event()
937 sr = readl_relaxed(spi->base + STM32FX_SPI_SR); in stm32fx_spi_irq_event()
944 if (!spi->cur_usedma && (spi->cur_comm == SPI_SIMPLEX_TX || in stm32fx_spi_irq_event()
945 spi->cur_comm == SPI_3WIRE_TX)) { in stm32fx_spi_irq_event()
951 if (!spi->cur_usedma && (spi->cur_comm == SPI_FULL_DUPLEX || in stm32fx_spi_irq_event()
952 spi->cur_comm == SPI_SIMPLEX_RX || in stm32fx_spi_irq_event()
953 spi->cur_comm == SPI_3WIRE_RX)) { in stm32fx_spi_irq_event()
960 dev_dbg(spi->dev, "spurious IT (sr=0x%08x)\n", sr); in stm32fx_spi_irq_event()
961 spin_unlock(&spi->lock); in stm32fx_spi_irq_event()
966 dev_warn(spi->dev, "Overrun: received value discarded\n"); in stm32fx_spi_irq_event()
969 readl_relaxed(spi->base + STM32FX_SPI_DR); in stm32fx_spi_irq_event()
970 readl_relaxed(spi->base + STM32FX_SPI_SR); in stm32fx_spi_irq_event()
982 if (spi->tx_buf) in stm32fx_spi_irq_event()
983 spi->cfg->write_tx(spi); in stm32fx_spi_irq_event()
984 if (spi->tx_len == 0) in stm32fx_spi_irq_event()
989 spi->cfg->read_rx(spi); in stm32fx_spi_irq_event()
990 if (spi->rx_len == 0) in stm32fx_spi_irq_event()
992 else if (spi->tx_buf)/* Load data for discontinuous mode */ in stm32fx_spi_irq_event()
993 spi->cfg->write_tx(spi); in stm32fx_spi_irq_event()
1003 spin_unlock(&spi->lock); in stm32fx_spi_irq_event()
1007 spin_unlock(&spi->lock); in stm32fx_spi_irq_event()
1012 * stm32fx_spi_irq_thread - Thread of interrupt handler for SPI controller
1014 * @dev_id: SPI controller interface
1028 * stm32h7_spi_irq_thread - Thread of interrupt handler for SPI controller
1030 * @dev_id: SPI controller interface
1040 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_irq_thread()
1042 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); in stm32h7_spi_irq_thread()
1043 ier = readl_relaxed(spi->base + STM32H7_SPI_IER); in stm32h7_spi_irq_thread()
1053 * DXPIE is set in Full-Duplex, one IT will be raised if TXP and RXP in stm32h7_spi_irq_thread()
1054 * are set. So in case of Full-Duplex, need to poll TXP and RXP event. in stm32h7_spi_irq_thread()
1056 if ((spi->cur_comm == SPI_FULL_DUPLEX) && !spi->cur_usedma) in stm32h7_spi_irq_thread()
1060 dev_vdbg(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n", in stm32h7_spi_irq_thread()
1062 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_irq_thread()
1072 dev_dbg_ratelimited(spi->dev, "Communication suspended\n"); in stm32h7_spi_irq_thread()
1073 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) in stm32h7_spi_irq_thread()
1079 if (spi->cur_usedma) in stm32h7_spi_irq_thread()
1084 dev_warn(spi->dev, "Mode fault: transfer aborted\n"); in stm32h7_spi_irq_thread()
1089 dev_err(spi->dev, "Overrun: RX data lost\n"); in stm32h7_spi_irq_thread()
1094 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) in stm32h7_spi_irq_thread()
1096 if (!spi->cur_usedma || in stm32h7_spi_irq_thread()
1097 (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX)) in stm32h7_spi_irq_thread()
1102 if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0))) in stm32h7_spi_irq_thread()
1106 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) in stm32h7_spi_irq_thread()
1109 writel_relaxed(sr & mask, spi->base + STM32H7_SPI_IFCR); in stm32h7_spi_irq_thread()
1111 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_irq_thread()
1123 struct spi_controller *ctrl = msg->spi->controller; in stm32_spi_optimize_message()
1130 if (spi->cfg->set_number_of_data) in stm32_spi_optimize_message()
1131 return spi_split_transfers_maxwords(ctrl, msg, spi->t_size_max); in stm32_spi_optimize_message()
1137 * stm32_spi_prepare_msg - set up the controller to transfer a single message
1138 * @ctrl: controller interface
1145 struct spi_device *spi_dev = msg->spi; in stm32_spi_prepare_msg()
1146 struct device_node *np = spi_dev->dev.of_node; in stm32_spi_prepare_msg()
1150 /* SPI target device may need time between data frames */ in stm32_spi_prepare_msg()
1151 spi->cur_midi = 0; in stm32_spi_prepare_msg()
1152 if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi)) in stm32_spi_prepare_msg()
1153 dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi); in stm32_spi_prepare_msg()
1155 if (spi_dev->mode & SPI_CPOL) in stm32_spi_prepare_msg()
1156 setb |= spi->cfg->regs->cpol.mask; in stm32_spi_prepare_msg()
1158 clrb |= spi->cfg->regs->cpol.mask; in stm32_spi_prepare_msg()
1160 if (spi_dev->mode & SPI_CPHA) in stm32_spi_prepare_msg()
1161 setb |= spi->cfg->regs->cpha.mask; in stm32_spi_prepare_msg()
1163 clrb |= spi->cfg->regs->cpha.mask; in stm32_spi_prepare_msg()
1165 if (spi_dev->mode & SPI_LSB_FIRST) in stm32_spi_prepare_msg()
1166 setb |= spi->cfg->regs->lsb_first.mask; in stm32_spi_prepare_msg()
1168 clrb |= spi->cfg->regs->lsb_first.mask; in stm32_spi_prepare_msg()
1170 if (STM32_SPI_DEVICE_MODE(spi) && spi_dev->mode & SPI_CS_HIGH) in stm32_spi_prepare_msg()
1171 setb |= spi->cfg->regs->cs_high.mask; in stm32_spi_prepare_msg()
1173 clrb |= spi->cfg->regs->cs_high.mask; in stm32_spi_prepare_msg()
1175 dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n", in stm32_spi_prepare_msg()
1176 !!(spi_dev->mode & SPI_CPOL), in stm32_spi_prepare_msg()
1177 !!(spi_dev->mode & SPI_CPHA), in stm32_spi_prepare_msg()
1178 !!(spi_dev->mode & SPI_LSB_FIRST), in stm32_spi_prepare_msg()
1179 !!(spi_dev->mode & SPI_CS_HIGH)); in stm32_spi_prepare_msg()
1181 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_prepare_msg()
1186 (readl_relaxed(spi->base + spi->cfg->regs->cpol.reg) & in stm32_spi_prepare_msg()
1188 spi->base + spi->cfg->regs->cpol.reg); in stm32_spi_prepare_msg()
1190 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_prepare_msg()
1196 * stm32fx_spi_dma_tx_cb - dma callback
1197 * @data: pointer to the spi controller data structure
1201 static void stm32fx_spi_dma_tx_cb(void *data) in stm32fx_spi_dma_tx_cb() argument
1203 struct stm32_spi *spi = data; in stm32fx_spi_dma_tx_cb()
1205 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) { in stm32fx_spi_dma_tx_cb()
1206 spi_finalize_current_transfer(spi->ctrl); in stm32fx_spi_dma_tx_cb()
1212 * stm32_spi_dma_rx_cb - dma callback
1213 * @data: pointer to the spi controller data structure
1217 static void stm32_spi_dma_rx_cb(void *data) in stm32_spi_dma_rx_cb() argument
1219 struct stm32_spi *spi = data; in stm32_spi_dma_rx_cb()
1221 spi_finalize_current_transfer(spi->ctrl); in stm32_spi_dma_rx_cb()
1222 spi->cfg->disable(spi); in stm32_spi_dma_rx_cb()
1226 * stm32_spi_dma_config - configure dma slave channel depending on current
1228 * @spi: pointer to the spi controller data structure
1243 if (spi->cur_bpw <= 8) in stm32_spi_dma_config()
1245 else if (spi->cur_bpw <= 16) in stm32_spi_dma_config()
1251 if (!spi->cfg->prevent_dma_burst && spi->cfg->has_fifo && spi->cur_fthlv != 2) in stm32_spi_dma_config()
1252 maxburst = spi->cur_fthlv; in stm32_spi_dma_config()
1260 dma_conf->direction = dir; in stm32_spi_dma_config()
1261 if (dma_conf->direction == DMA_DEV_TO_MEM) { /* RX */ in stm32_spi_dma_config()
1262 dma_conf->src_addr = spi->phys_addr + spi->cfg->regs->rx.reg; in stm32_spi_dma_config()
1263 dma_conf->src_addr_width = buswidth; in stm32_spi_dma_config()
1264 dma_conf->src_maxburst = maxburst; in stm32_spi_dma_config()
1266 dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n", in stm32_spi_dma_config()
1268 } else if (dma_conf->direction == DMA_MEM_TO_DEV) { /* TX */ in stm32_spi_dma_config()
1269 dma_conf->dst_addr = spi->phys_addr + spi->cfg->regs->tx.reg; in stm32_spi_dma_config()
1270 dma_conf->dst_addr_width = buswidth; in stm32_spi_dma_config()
1271 dma_conf->dst_maxburst = maxburst; in stm32_spi_dma_config()
1273 dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n", in stm32_spi_dma_config()
1279 * stm32fx_spi_transfer_one_irq - transfer a single spi_transfer using
1281 * @spi: pointer to the spi controller data structure
1292 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) { in stm32fx_spi_transfer_one_irq()
1294 } else if (spi->cur_comm == SPI_FULL_DUPLEX || in stm32fx_spi_transfer_one_irq()
1295 spi->cur_comm == SPI_SIMPLEX_RX || in stm32fx_spi_transfer_one_irq()
1296 spi->cur_comm == SPI_3WIRE_RX) { in stm32fx_spi_transfer_one_irq()
1297 /* In transmit-only mode, the OVR flag is set in the SR register in stm32fx_spi_transfer_one_irq()
1298 * since the received data are never read. Therefore set OVR in stm32fx_spi_transfer_one_irq()
1303 return -EINVAL; in stm32fx_spi_transfer_one_irq()
1306 spin_lock_irqsave(&spi->lock, flags); in stm32fx_spi_transfer_one_irq()
1312 /* starting data transfer when buffer is loaded */ in stm32fx_spi_transfer_one_irq()
1313 if (spi->tx_buf) in stm32fx_spi_transfer_one_irq()
1314 spi->cfg->write_tx(spi); in stm32fx_spi_transfer_one_irq()
1316 spin_unlock_irqrestore(&spi->lock, flags); in stm32fx_spi_transfer_one_irq()
1322 * stm32h7_spi_transfer_one_irq - transfer a single spi_transfer using
1324 * @spi: pointer to the spi controller data structure
1335 if (spi->tx_buf && spi->rx_buf) /* Full Duplex */ in stm32h7_spi_transfer_one_irq()
1337 else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */ in stm32h7_spi_transfer_one_irq()
1339 else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */ in stm32h7_spi_transfer_one_irq()
1346 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_transfer_one_irq()
1350 /* Be sure to have data in fifo before starting data transfer */ in stm32h7_spi_transfer_one_irq()
1351 if (spi->tx_buf) in stm32h7_spi_transfer_one_irq()
1357 writel_relaxed(ier, spi->base + STM32H7_SPI_IER); in stm32h7_spi_transfer_one_irq()
1359 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_transfer_one_irq()
1365 * stm32fx_spi_transfer_one_dma_start - Set SPI driver registers to start
1367 * @spi: pointer to the spi controller data structure
1372 if (spi->cur_comm == SPI_SIMPLEX_RX || spi->cur_comm == SPI_3WIRE_RX || in stm32fx_spi_transfer_one_dma_start()
1373 spi->cur_comm == SPI_FULL_DUPLEX) { in stm32fx_spi_transfer_one_dma_start()
1375 * In transmit-only mode, the OVR flag is set in the SR register in stm32fx_spi_transfer_one_dma_start()
1376 * since the received data are never read. Therefore set OVR in stm32fx_spi_transfer_one_dma_start()
1386 * stm32f7_spi_transfer_one_dma_start - Set SPI driver registers to start
1388 * @spi: pointer to the spi controller data structure
1393 if (spi->cur_bpw <= 8) in stm32f7_spi_transfer_one_dma_start()
1402 * stm32h7_spi_transfer_one_dma_start - Set SPI driver registers to start
1404 * @spi: pointer to the spi controller data structure
1411 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) in stm32h7_spi_transfer_one_dma_start()
1423 * stm32_spi_transfer_one_dma - transfer a single spi_transfer using DMA
1424 * @spi: pointer to the spi controller data structure
1437 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_transfer_one_dma()
1440 if (spi->rx_buf && spi->dma_rx) { in stm32_spi_transfer_one_dma()
1441 stm32_spi_dma_config(spi, spi->dma_rx, &rx_dma_conf, DMA_DEV_TO_MEM); in stm32_spi_transfer_one_dma()
1442 dmaengine_slave_config(spi->dma_rx, &rx_dma_conf); in stm32_spi_transfer_one_dma()
1445 stm32_spi_set_bits(spi, spi->cfg->regs->dma_rx_en.reg, in stm32_spi_transfer_one_dma()
1446 spi->cfg->regs->dma_rx_en.mask); in stm32_spi_transfer_one_dma()
1449 spi->dma_rx, xfer->rx_sg.sgl, in stm32_spi_transfer_one_dma()
1450 xfer->rx_sg.nents, in stm32_spi_transfer_one_dma()
1456 if (spi->tx_buf && spi->dma_tx) { in stm32_spi_transfer_one_dma()
1457 stm32_spi_dma_config(spi, spi->dma_tx, &tx_dma_conf, DMA_MEM_TO_DEV); in stm32_spi_transfer_one_dma()
1458 dmaengine_slave_config(spi->dma_tx, &tx_dma_conf); in stm32_spi_transfer_one_dma()
1461 spi->dma_tx, xfer->tx_sg.sgl, in stm32_spi_transfer_one_dma()
1462 xfer->tx_sg.nents, in stm32_spi_transfer_one_dma()
1467 if ((spi->tx_buf && spi->dma_tx && !tx_dma_desc) || in stm32_spi_transfer_one_dma()
1468 (spi->rx_buf && spi->dma_rx && !rx_dma_desc)) in stm32_spi_transfer_one_dma()
1471 if (spi->cur_comm == SPI_FULL_DUPLEX && (!tx_dma_desc || !rx_dma_desc)) in stm32_spi_transfer_one_dma()
1475 rx_dma_desc->callback = spi->cfg->dma_rx_cb; in stm32_spi_transfer_one_dma()
1476 rx_dma_desc->callback_param = spi; in stm32_spi_transfer_one_dma()
1479 dev_err(spi->dev, "Rx DMA submit failed\n"); in stm32_spi_transfer_one_dma()
1483 dma_async_issue_pending(spi->dma_rx); in stm32_spi_transfer_one_dma()
1487 if (spi->cur_comm == SPI_SIMPLEX_TX || in stm32_spi_transfer_one_dma()
1488 spi->cur_comm == SPI_3WIRE_TX) { in stm32_spi_transfer_one_dma()
1489 tx_dma_desc->callback = spi->cfg->dma_tx_cb; in stm32_spi_transfer_one_dma()
1490 tx_dma_desc->callback_param = spi; in stm32_spi_transfer_one_dma()
1494 dev_err(spi->dev, "Tx DMA submit failed\n"); in stm32_spi_transfer_one_dma()
1498 dma_async_issue_pending(spi->dma_tx); in stm32_spi_transfer_one_dma()
1501 stm32_spi_set_bits(spi, spi->cfg->regs->dma_tx_en.reg, in stm32_spi_transfer_one_dma()
1502 spi->cfg->regs->dma_tx_en.mask); in stm32_spi_transfer_one_dma()
1505 spi->cfg->transfer_one_dma_start(spi); in stm32_spi_transfer_one_dma()
1507 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_transfer_one_dma()
1512 if (spi->dma_rx) in stm32_spi_transfer_one_dma()
1513 dmaengine_terminate_sync(spi->dma_rx); in stm32_spi_transfer_one_dma()
1516 stm32_spi_clr_bits(spi, spi->cfg->regs->dma_rx_en.reg, in stm32_spi_transfer_one_dma()
1517 spi->cfg->regs->dma_rx_en.mask); in stm32_spi_transfer_one_dma()
1519 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_transfer_one_dma()
1521 dev_info(spi->dev, "DMA issue: fall back to irq transfer\n"); in stm32_spi_transfer_one_dma()
1523 spi->cur_usedma = false; in stm32_spi_transfer_one_dma()
1524 return spi->cfg->transfer_one_irq(spi); in stm32_spi_transfer_one_dma()
1528 * stm32f4_spi_set_bpw - Configure bits per word
1529 * @spi: pointer to the spi controller data structure
1533 if (spi->cur_bpw == 16) in stm32f4_spi_set_bpw()
1540 * stm32f7_spi_set_bpw - Configure bits per word
1541 * @spi: pointer to the spi controller data structure
1548 bpw = spi->cur_bpw - 1; in stm32f7_spi_set_bpw()
1553 if (spi->rx_len >= sizeof(u16)) in stm32f7_spi_set_bpw()
1559 (readl_relaxed(spi->base + STM32FX_SPI_CR2) & in stm32f7_spi_set_bpw()
1561 spi->base + STM32FX_SPI_CR2); in stm32f7_spi_set_bpw()
1565 * stm32h7_spi_set_bpw - configure bits per word
1566 * @spi: pointer to the spi controller data structure
1573 bpw = spi->cur_bpw - 1; in stm32h7_spi_set_bpw()
1578 spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen); in stm32h7_spi_set_bpw()
1579 fthlv = spi->cur_fthlv - 1; in stm32h7_spi_set_bpw()
1585 (readl_relaxed(spi->base + STM32H7_SPI_CFG1) & in stm32h7_spi_set_bpw()
1587 spi->base + STM32H7_SPI_CFG1); in stm32h7_spi_set_bpw()
1591 * stm32_spi_set_mbr - Configure baud rate divisor in host mode
1592 * @spi: pointer to the spi controller data structure
1599 clrb |= spi->cfg->regs->br.mask; in stm32_spi_set_mbr()
1600 setb |= (mbrdiv << spi->cfg->regs->br.shift) & spi->cfg->regs->br.mask; in stm32_spi_set_mbr()
1602 writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) & in stm32_spi_set_mbr()
1604 spi->base + spi->cfg->regs->br.reg); in stm32_spi_set_mbr()
1608 * stm32_spi_communication_type - return transfer communication type
1617 if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */ in stm32_spi_communication_type()
1619 * SPI_3WIRE and xfer->tx_buf != NULL and xfer->rx_buf != NULL in stm32_spi_communication_type()
1624 if (!transfer->tx_buf) in stm32_spi_communication_type()
1629 if (!transfer->tx_buf) in stm32_spi_communication_type()
1631 else if (!transfer->rx_buf) in stm32_spi_communication_type()
1639 * stm32fx_spi_set_mode - configure communication mode
1640 * @spi: pointer to the spi controller data structure
1660 return -EINVAL; in stm32fx_spi_set_mode()
1667 * stm32h7_spi_set_mode - configure communication mode
1668 * @spi: pointer to the spi controller data structure
1694 (readl_relaxed(spi->base + STM32H7_SPI_CFG2) & in stm32h7_spi_set_mode()
1696 spi->base + STM32H7_SPI_CFG2); in stm32h7_spi_set_mode()
1702 * stm32h7_spi_data_idleness - configure minimum time delay inserted between two
1703 * consecutive data frames in host mode
1704 * @spi: pointer to the spi controller data structure
1712 if ((len > 1) && (spi->cur_midi > 0)) { in stm32h7_spi_data_idleness()
1713 u32 sck_period_ns = DIV_ROUND_UP(NSEC_PER_SEC, spi->cur_speed); in stm32h7_spi_data_idleness()
1715 DIV_ROUND_UP(spi->cur_midi, sck_period_ns), in stm32h7_spi_data_idleness()
1720 dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n", in stm32h7_spi_data_idleness()
1725 writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) & in stm32h7_spi_data_idleness()
1727 spi->base + STM32H7_SPI_CFG2); in stm32h7_spi_data_idleness()
1731 * stm32h7_spi_number_of_data - configure number of data at current transfer
1732 * @spi: pointer to the spi controller data structure
1737 if (nb_words <= spi->t_size_max) { in stm32h7_spi_number_of_data()
1739 spi->base + STM32H7_SPI_CR2); in stm32h7_spi_number_of_data()
1741 return -EMSGSIZE; in stm32h7_spi_number_of_data()
1748 * stm32_spi_transfer_one_setup - common setup to transfer a single
1751 * @spi: pointer to the spi controller data structure
1764 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_transfer_one_setup()
1766 spi->cur_xferlen = transfer->len; in stm32_spi_transfer_one_setup()
1768 spi->cur_bpw = transfer->bits_per_word; in stm32_spi_transfer_one_setup()
1769 spi->cfg->set_bpw(spi); in stm32_spi_transfer_one_setup()
1771 /* Update spi->cur_speed with real clock speed */ in stm32_spi_transfer_one_setup()
1773 mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz, in stm32_spi_transfer_one_setup()
1774 spi->cfg->baud_rate_div_min, in stm32_spi_transfer_one_setup()
1775 spi->cfg->baud_rate_div_max); in stm32_spi_transfer_one_setup()
1781 transfer->speed_hz = spi->cur_speed; in stm32_spi_transfer_one_setup()
1786 ret = spi->cfg->set_mode(spi, comm_type); in stm32_spi_transfer_one_setup()
1790 spi->cur_comm = comm_type; in stm32_spi_transfer_one_setup()
1792 if (STM32_SPI_HOST_MODE(spi) && spi->cfg->set_data_idleness) in stm32_spi_transfer_one_setup()
1793 spi->cfg->set_data_idleness(spi, transfer->len); in stm32_spi_transfer_one_setup()
1795 if (spi->cur_bpw <= 8) in stm32_spi_transfer_one_setup()
1796 nb_words = transfer->len; in stm32_spi_transfer_one_setup()
1797 else if (spi->cur_bpw <= 16) in stm32_spi_transfer_one_setup()
1798 nb_words = DIV_ROUND_UP(transfer->len * 8, 16); in stm32_spi_transfer_one_setup()
1800 nb_words = DIV_ROUND_UP(transfer->len * 8, 32); in stm32_spi_transfer_one_setup()
1802 if (spi->cfg->set_number_of_data) { in stm32_spi_transfer_one_setup()
1803 ret = spi->cfg->set_number_of_data(spi, nb_words); in stm32_spi_transfer_one_setup()
1808 dev_dbg(spi->dev, "transfer communication mode set to %d\n", in stm32_spi_transfer_one_setup()
1809 spi->cur_comm); in stm32_spi_transfer_one_setup()
1810 dev_dbg(spi->dev, in stm32_spi_transfer_one_setup()
1811 "data frame of %d-bit, data packet of %d data frames\n", in stm32_spi_transfer_one_setup()
1812 spi->cur_bpw, spi->cur_fthlv); in stm32_spi_transfer_one_setup()
1814 dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed); in stm32_spi_transfer_one_setup()
1815 dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n", in stm32_spi_transfer_one_setup()
1816 spi->cur_xferlen, nb_words); in stm32_spi_transfer_one_setup()
1817 dev_dbg(spi->dev, "dma %s\n", in stm32_spi_transfer_one_setup()
1818 (spi->cur_usedma) ? "enabled" : "disabled"); in stm32_spi_transfer_one_setup()
1821 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_transfer_one_setup()
1827 * stm32_spi_transfer_one - transfer a single spi_transfer
1828 * @ctrl: controller interface
1842 spi->tx_buf = transfer->tx_buf; in stm32_spi_transfer_one()
1843 spi->rx_buf = transfer->rx_buf; in stm32_spi_transfer_one()
1844 spi->tx_len = spi->tx_buf ? transfer->len : 0; in stm32_spi_transfer_one()
1845 spi->rx_len = spi->rx_buf ? transfer->len : 0; in stm32_spi_transfer_one()
1847 spi->cur_usedma = (ctrl->can_dma && in stm32_spi_transfer_one()
1848 ctrl->can_dma(ctrl, spi_dev, transfer)); in stm32_spi_transfer_one()
1852 dev_err(spi->dev, "SPI transfer setup failed\n"); in stm32_spi_transfer_one()
1856 if (spi->cur_usedma) in stm32_spi_transfer_one()
1859 return spi->cfg->transfer_one_irq(spi); in stm32_spi_transfer_one()
1863 * stm32_spi_unprepare_msg - relax the hardware
1864 * @ctrl: controller interface
1872 spi->cfg->disable(spi); in stm32_spi_unprepare_msg()
1878 * stm32fx_spi_config - Configure SPI controller as SPI host
1879 * @spi: pointer to the spi controller data structure
1885 spin_lock_irqsave(&spi->lock, flags); in stm32fx_spi_config()
1892 * - SS input value high in stm32fx_spi_config()
1893 * - transmitter half duplex direction in stm32fx_spi_config()
1894 * - Set the host mode (default Motorola mode) in stm32fx_spi_config()
1895 * - Consider 1 host/n targets configuration and in stm32fx_spi_config()
1903 spin_unlock_irqrestore(&spi->lock, flags); in stm32fx_spi_config()
1909 * stm32h7_spi_config - Configure SPI controller
1910 * @spi: pointer to the spi controller data structure
1917 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_config()
1928 * - Transmitter half duplex direction in stm32h7_spi_config()
1929 * - Automatic communication suspend when RX-Fifo is full in stm32h7_spi_config()
1930 * - SS input value high in stm32h7_spi_config()
1935 * - Set the host mode (default Motorola mode) in stm32h7_spi_config()
1936 * - Consider 1 host/n devices configuration and in stm32h7_spi_config()
1938 * - keep control of all associated GPIOs in stm32h7_spi_config()
1946 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_config()
2022 * - enforce the DMA maxburst value to 1
2023 * - spi8 have limited feature set (TSIZE_MAX = 1024, BPW of 8 OR 16)
2051 { .compatible = "st,stm32mp25-spi", .data = (void *)&stm32mp25_spi_cfg },
2052 { .compatible = "st,stm32h7-spi", .data = (void *)&stm32h7_spi_cfg },
2053 { .compatible = "st,stm32f4-spi", .data = (void *)&stm32f4_spi_cfg },
2054 { .compatible = "st,stm32f7-spi", .data = (void *)&stm32f7_spi_cfg },
2071 struct device_node *np = pdev->dev.of_node; in stm32_spi_probe()
2074 const struct stm32_spi_cfg *cfg = of_device_get_match_data(&pdev->dev); in stm32_spi_probe()
2076 device_mode = of_property_read_bool(np, "spi-slave"); in stm32_spi_probe()
2077 if (!cfg->has_device_mode && device_mode) { in stm32_spi_probe()
2078 dev_err(&pdev->dev, "spi-slave not supported\n"); in stm32_spi_probe()
2079 return -EPERM; in stm32_spi_probe()
2083 ctrl = devm_spi_alloc_target(&pdev->dev, sizeof(struct stm32_spi)); in stm32_spi_probe()
2085 ctrl = devm_spi_alloc_host(&pdev->dev, sizeof(struct stm32_spi)); in stm32_spi_probe()
2087 dev_err(&pdev->dev, "spi controller allocation failed\n"); in stm32_spi_probe()
2088 return -ENOMEM; in stm32_spi_probe()
2093 spi->dev = &pdev->dev; in stm32_spi_probe()
2094 spi->ctrl = ctrl; in stm32_spi_probe()
2095 spi->device_mode = device_mode; in stm32_spi_probe()
2096 spin_lock_init(&spi->lock); in stm32_spi_probe()
2098 spi->cfg = cfg; in stm32_spi_probe()
2100 spi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in stm32_spi_probe()
2101 if (IS_ERR(spi->base)) in stm32_spi_probe()
2102 return PTR_ERR(spi->base); in stm32_spi_probe()
2104 spi->phys_addr = (dma_addr_t)res->start; in stm32_spi_probe()
2106 spi->irq = platform_get_irq(pdev, 0); in stm32_spi_probe()
2107 if (spi->irq <= 0) in stm32_spi_probe()
2108 return spi->irq; in stm32_spi_probe()
2110 ret = devm_request_threaded_irq(&pdev->dev, spi->irq, in stm32_spi_probe()
2111 spi->cfg->irq_handler_event, in stm32_spi_probe()
2112 spi->cfg->irq_handler_thread, in stm32_spi_probe()
2113 IRQF_ONESHOT, pdev->name, ctrl); in stm32_spi_probe()
2115 dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq, in stm32_spi_probe()
2120 spi->clk = devm_clk_get(&pdev->dev, NULL); in stm32_spi_probe()
2121 if (IS_ERR(spi->clk)) { in stm32_spi_probe()
2122 ret = PTR_ERR(spi->clk); in stm32_spi_probe()
2123 dev_err(&pdev->dev, "clk get failed: %d\n", ret); in stm32_spi_probe()
2127 ret = clk_prepare_enable(spi->clk); in stm32_spi_probe()
2129 dev_err(&pdev->dev, "clk enable failed: %d\n", ret); in stm32_spi_probe()
2132 spi->clk_rate = clk_get_rate(spi->clk); in stm32_spi_probe()
2133 if (!spi->clk_rate) { in stm32_spi_probe()
2134 dev_err(&pdev->dev, "clk rate = 0\n"); in stm32_spi_probe()
2135 ret = -EINVAL; in stm32_spi_probe()
2139 rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); in stm32_spi_probe()
2142 ret = dev_err_probe(&pdev->dev, PTR_ERR(rst), in stm32_spi_probe()
2152 if (spi->cfg->has_fifo) in stm32_spi_probe()
2153 spi->fifo_size = spi->cfg->get_fifo_size(spi); in stm32_spi_probe()
2155 spi->feature_set = STM32_SPI_FEATURE_FULL; in stm32_spi_probe()
2156 if (spi->cfg->regs->fullcfg.reg) { in stm32_spi_probe()
2157 spi->feature_set = in stm32_spi_probe()
2159 readl_relaxed(spi->base + spi->cfg->regs->fullcfg.reg)); in stm32_spi_probe()
2161 dev_dbg(spi->dev, "%s feature set\n", in stm32_spi_probe()
2162 spi->feature_set == STM32_SPI_FEATURE_FULL ? "full" : "limited"); in stm32_spi_probe()
2166 spi->t_size_max = spi->feature_set == STM32_SPI_FEATURE_FULL ? in stm32_spi_probe()
2169 dev_dbg(spi->dev, "one message max size %d\n", spi->t_size_max); in stm32_spi_probe()
2171 ret = spi->cfg->config(spi); in stm32_spi_probe()
2173 dev_err(&pdev->dev, "controller configuration failed: %d\n", in stm32_spi_probe()
2178 ctrl->dev.of_node = pdev->dev.of_node; in stm32_spi_probe()
2179 ctrl->auto_runtime_pm = true; in stm32_spi_probe()
2180 ctrl->bus_num = pdev->id; in stm32_spi_probe()
2181 ctrl->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST | in stm32_spi_probe()
2183 ctrl->bits_per_word_mask = spi->cfg->get_bpw_mask(spi); in stm32_spi_probe()
2184 ctrl->max_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_min; in stm32_spi_probe()
2185 ctrl->min_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_max; in stm32_spi_probe()
2186 ctrl->use_gpio_descriptors = true; in stm32_spi_probe()
2187 ctrl->optimize_message = stm32_spi_optimize_message; in stm32_spi_probe()
2188 ctrl->prepare_message = stm32_spi_prepare_msg; in stm32_spi_probe()
2189 ctrl->transfer_one = stm32_spi_transfer_one; in stm32_spi_probe()
2190 ctrl->unprepare_message = stm32_spi_unprepare_msg; in stm32_spi_probe()
2191 ctrl->flags = spi->cfg->flags; in stm32_spi_probe()
2193 ctrl->target_abort = stm32h7_spi_device_abort; in stm32_spi_probe()
2195 spi->dma_tx = dma_request_chan(spi->dev, "tx"); in stm32_spi_probe()
2196 if (IS_ERR(spi->dma_tx)) { in stm32_spi_probe()
2197 ret = PTR_ERR(spi->dma_tx); in stm32_spi_probe()
2198 spi->dma_tx = NULL; in stm32_spi_probe()
2199 if (ret == -EPROBE_DEFER) in stm32_spi_probe()
2202 dev_warn(&pdev->dev, "failed to request tx dma channel\n"); in stm32_spi_probe()
2204 ctrl->dma_tx = spi->dma_tx; in stm32_spi_probe()
2207 spi->dma_rx = dma_request_chan(spi->dev, "rx"); in stm32_spi_probe()
2208 if (IS_ERR(spi->dma_rx)) { in stm32_spi_probe()
2209 ret = PTR_ERR(spi->dma_rx); in stm32_spi_probe()
2210 spi->dma_rx = NULL; in stm32_spi_probe()
2211 if (ret == -EPROBE_DEFER) in stm32_spi_probe()
2214 dev_warn(&pdev->dev, "failed to request rx dma channel\n"); in stm32_spi_probe()
2216 ctrl->dma_rx = spi->dma_rx; in stm32_spi_probe()
2219 if (spi->dma_tx || spi->dma_rx) in stm32_spi_probe()
2220 ctrl->can_dma = stm32_spi_can_dma; in stm32_spi_probe()
2222 pm_runtime_set_autosuspend_delay(&pdev->dev, in stm32_spi_probe()
2224 pm_runtime_use_autosuspend(&pdev->dev); in stm32_spi_probe()
2225 pm_runtime_set_active(&pdev->dev); in stm32_spi_probe()
2226 pm_runtime_get_noresume(&pdev->dev); in stm32_spi_probe()
2227 pm_runtime_enable(&pdev->dev); in stm32_spi_probe()
2231 dev_err(&pdev->dev, "spi controller registration failed: %d\n", in stm32_spi_probe()
2236 pm_runtime_mark_last_busy(&pdev->dev); in stm32_spi_probe()
2237 pm_runtime_put_autosuspend(&pdev->dev); in stm32_spi_probe()
2239 dev_info(&pdev->dev, "driver initialized (%s mode)\n", in stm32_spi_probe()
2245 pm_runtime_disable(&pdev->dev); in stm32_spi_probe()
2246 pm_runtime_put_noidle(&pdev->dev); in stm32_spi_probe()
2247 pm_runtime_set_suspended(&pdev->dev); in stm32_spi_probe()
2248 pm_runtime_dont_use_autosuspend(&pdev->dev); in stm32_spi_probe()
2250 if (spi->dma_tx) in stm32_spi_probe()
2251 dma_release_channel(spi->dma_tx); in stm32_spi_probe()
2252 if (spi->dma_rx) in stm32_spi_probe()
2253 dma_release_channel(spi->dma_rx); in stm32_spi_probe()
2255 clk_disable_unprepare(spi->clk); in stm32_spi_probe()
2265 pm_runtime_get_sync(&pdev->dev); in stm32_spi_remove()
2268 spi->cfg->disable(spi); in stm32_spi_remove()
2270 pm_runtime_disable(&pdev->dev); in stm32_spi_remove()
2271 pm_runtime_put_noidle(&pdev->dev); in stm32_spi_remove()
2272 pm_runtime_set_suspended(&pdev->dev); in stm32_spi_remove()
2273 pm_runtime_dont_use_autosuspend(&pdev->dev); in stm32_spi_remove()
2275 if (ctrl->dma_tx) in stm32_spi_remove()
2276 dma_release_channel(ctrl->dma_tx); in stm32_spi_remove()
2277 if (ctrl->dma_rx) in stm32_spi_remove()
2278 dma_release_channel(ctrl->dma_rx); in stm32_spi_remove()
2280 clk_disable_unprepare(spi->clk); in stm32_spi_remove()
2283 pinctrl_pm_select_sleep_state(&pdev->dev); in stm32_spi_remove()
2291 clk_disable_unprepare(spi->clk); in stm32_spi_runtime_suspend()
2306 return clk_prepare_enable(spi->clk); in stm32_spi_runtime_resume()
2333 clk_disable_unprepare(spi->clk); in stm32_spi_resume()
2343 spi->cfg->config(spi); in stm32_spi_resume()
2370 MODULE_DESCRIPTION("STMicroelectronics STM32 SPI Controller driver");