Lines Matching +full:stm32f469 +full:- +full:qspi
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
9 #include <linux/dma-mapping.h>
23 #include <linux/spi/spi-mem.h>
93 #define STM32_AUTOSUSPEND_DELAY -1
131 struct stm32_qspi *qspi = (struct stm32_qspi *)dev_id; in stm32_qspi_irq() local
134 cr = readl_relaxed(qspi->io_base + QSPI_CR); in stm32_qspi_irq()
135 sr = readl_relaxed(qspi->io_base + QSPI_SR); in stm32_qspi_irq()
140 writel_relaxed(cr, qspi->io_base + QSPI_CR); in stm32_qspi_irq()
141 complete(&qspi->match_completion); in stm32_qspi_irq()
149 writel_relaxed(cr, qspi->io_base + QSPI_CR); in stm32_qspi_irq()
150 complete(&qspi->data_completion); in stm32_qspi_irq()
166 static int stm32_qspi_tx_poll(struct stm32_qspi *qspi, in stm32_qspi_tx_poll() argument
170 u32 len = op->data.nbytes, sr; in stm32_qspi_tx_poll()
174 if (op->data.dir == SPI_MEM_DATA_IN) { in stm32_qspi_tx_poll()
176 buf = op->data.buf.in; in stm32_qspi_tx_poll()
180 buf = (u8 *)op->data.buf.out; in stm32_qspi_tx_poll()
183 while (len--) { in stm32_qspi_tx_poll()
184 ret = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, in stm32_qspi_tx_poll()
188 dev_err(qspi->dev, "fifo timeout (len:%d stat:%#x)\n", in stm32_qspi_tx_poll()
192 tx_fifo(buf++, qspi->io_base + QSPI_DR); in stm32_qspi_tx_poll()
198 static int stm32_qspi_tx_mm(struct stm32_qspi *qspi, in stm32_qspi_tx_mm() argument
201 memcpy_fromio(op->data.buf.in, qspi->mm_base + op->addr.val, in stm32_qspi_tx_mm()
202 op->data.nbytes); in stm32_qspi_tx_mm()
213 static int stm32_qspi_tx_dma(struct stm32_qspi *qspi, in stm32_qspi_tx_dma() argument
224 if (op->data.dir == SPI_MEM_DATA_IN) { in stm32_qspi_tx_dma()
226 dma_ch = qspi->dma_chrx; in stm32_qspi_tx_dma()
229 dma_ch = qspi->dma_chtx; in stm32_qspi_tx_dma()
233 * spi_map_buf return -EINVAL if the buffer is not DMA-able in stm32_qspi_tx_dma()
234 * (DMA-able: in vmalloc | kmap | virt_addr_valid) in stm32_qspi_tx_dma()
236 err = spi_controller_dma_map_mem_op_data(qspi->ctrl, op, &sgt); in stm32_qspi_tx_dma()
243 err = -ENOMEM; in stm32_qspi_tx_dma()
247 cr = readl_relaxed(qspi->io_base + QSPI_CR); in stm32_qspi_tx_dma()
249 reinit_completion(&qspi->dma_completion); in stm32_qspi_tx_dma()
250 desc->callback = stm32_qspi_dma_callback; in stm32_qspi_tx_dma()
251 desc->callback_param = &qspi->dma_completion; in stm32_qspi_tx_dma()
259 writel_relaxed(cr | CR_DMAEN, qspi->io_base + QSPI_CR); in stm32_qspi_tx_dma()
262 if (!wait_for_completion_timeout(&qspi->dma_completion, in stm32_qspi_tx_dma()
264 err = -ETIMEDOUT; in stm32_qspi_tx_dma()
270 writel_relaxed(cr & ~CR_DMAEN, qspi->io_base + QSPI_CR); in stm32_qspi_tx_dma()
272 spi_controller_dma_unmap_mem_op_data(qspi->ctrl, op, &sgt); in stm32_qspi_tx_dma()
277 static int stm32_qspi_tx(struct stm32_qspi *qspi, const struct spi_mem_op *op) in stm32_qspi_tx() argument
279 if (!op->data.nbytes) in stm32_qspi_tx()
282 if (qspi->fmode == CCR_FMODE_MM) in stm32_qspi_tx()
283 return stm32_qspi_tx_mm(qspi, op); in stm32_qspi_tx()
284 else if (((op->data.dir == SPI_MEM_DATA_IN && qspi->dma_chrx) || in stm32_qspi_tx()
285 (op->data.dir == SPI_MEM_DATA_OUT && qspi->dma_chtx)) && in stm32_qspi_tx()
286 op->data.nbytes > 4) in stm32_qspi_tx()
287 if (!stm32_qspi_tx_dma(qspi, op)) in stm32_qspi_tx()
290 return stm32_qspi_tx_poll(qspi, op); in stm32_qspi_tx()
293 static int stm32_qspi_wait_nobusy(struct stm32_qspi *qspi) in stm32_qspi_wait_nobusy() argument
297 return readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, sr, in stm32_qspi_wait_nobusy()
302 static int stm32_qspi_wait_cmd(struct stm32_qspi *qspi) in stm32_qspi_wait_cmd() argument
307 if ((readl_relaxed(qspi->io_base + QSPI_SR) & SR_TCF) || in stm32_qspi_wait_cmd()
308 qspi->fmode == CCR_FMODE_APM) in stm32_qspi_wait_cmd()
311 reinit_completion(&qspi->data_completion); in stm32_qspi_wait_cmd()
312 cr = readl_relaxed(qspi->io_base + QSPI_CR); in stm32_qspi_wait_cmd()
313 writel_relaxed(cr | CR_TCIE | CR_TEIE, qspi->io_base + QSPI_CR); in stm32_qspi_wait_cmd()
315 if (!wait_for_completion_timeout(&qspi->data_completion, in stm32_qspi_wait_cmd()
317 err = -ETIMEDOUT; in stm32_qspi_wait_cmd()
319 sr = readl_relaxed(qspi->io_base + QSPI_SR); in stm32_qspi_wait_cmd()
321 err = -EIO; in stm32_qspi_wait_cmd()
326 writel_relaxed(FCR_CTCF | FCR_CTEF, qspi->io_base + QSPI_FCR); in stm32_qspi_wait_cmd()
328 err = stm32_qspi_wait_nobusy(qspi); in stm32_qspi_wait_cmd()
333 static int stm32_qspi_wait_poll_status(struct stm32_qspi *qspi) in stm32_qspi_wait_poll_status() argument
337 reinit_completion(&qspi->match_completion); in stm32_qspi_wait_poll_status()
338 cr = readl_relaxed(qspi->io_base + QSPI_CR); in stm32_qspi_wait_poll_status()
339 writel_relaxed(cr | CR_SMIE, qspi->io_base + QSPI_CR); in stm32_qspi_wait_poll_status()
341 if (!wait_for_completion_timeout(&qspi->match_completion, in stm32_qspi_wait_poll_status()
342 msecs_to_jiffies(qspi->status_timeout))) in stm32_qspi_wait_poll_status()
343 return -ETIMEDOUT; in stm32_qspi_wait_poll_status()
345 writel_relaxed(FCR_CSMF, qspi->io_base + QSPI_FCR); in stm32_qspi_wait_poll_status()
360 struct stm32_qspi *qspi = spi_controller_get_devdata(spi->controller); in stm32_qspi_send() local
361 struct stm32_qspi_flash *flash = &qspi->flash[spi_get_chipselect(spi, 0)]; in stm32_qspi_send()
365 dev_dbg(qspi->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n", in stm32_qspi_send()
366 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth, in stm32_qspi_send()
367 op->dummy.buswidth, op->data.buswidth, in stm32_qspi_send()
368 op->addr.val, op->data.nbytes); in stm32_qspi_send()
370 cr = readl_relaxed(qspi->io_base + QSPI_CR); in stm32_qspi_send()
372 cr |= FIELD_PREP(CR_PRESC_MASK, flash->presc); in stm32_qspi_send()
373 cr |= FIELD_PREP(CR_FSEL, flash->cs); in stm32_qspi_send()
374 writel_relaxed(cr, qspi->io_base + QSPI_CR); in stm32_qspi_send()
376 if (op->data.nbytes) in stm32_qspi_send()
377 writel_relaxed(op->data.nbytes - 1, in stm32_qspi_send()
378 qspi->io_base + QSPI_DLR); in stm32_qspi_send()
380 ccr = qspi->fmode; in stm32_qspi_send()
381 ccr |= FIELD_PREP(CCR_INST_MASK, op->cmd.opcode); in stm32_qspi_send()
383 stm32_qspi_get_mode(op->cmd.buswidth)); in stm32_qspi_send()
385 if (op->addr.nbytes) { in stm32_qspi_send()
387 stm32_qspi_get_mode(op->addr.buswidth)); in stm32_qspi_send()
388 ccr |= FIELD_PREP(CCR_ADSIZE_MASK, op->addr.nbytes - 1); in stm32_qspi_send()
391 if (op->dummy.nbytes) in stm32_qspi_send()
393 op->dummy.nbytes * 8 / op->dummy.buswidth); in stm32_qspi_send()
395 if (op->data.nbytes) { in stm32_qspi_send()
397 stm32_qspi_get_mode(op->data.buswidth)); in stm32_qspi_send()
400 writel_relaxed(ccr, qspi->io_base + QSPI_CCR); in stm32_qspi_send()
402 if (op->addr.nbytes && qspi->fmode != CCR_FMODE_MM) in stm32_qspi_send()
403 writel_relaxed(op->addr.val, qspi->io_base + QSPI_AR); in stm32_qspi_send()
405 if (qspi->fmode == CCR_FMODE_APM) in stm32_qspi_send()
406 err_poll_status = stm32_qspi_wait_poll_status(qspi); in stm32_qspi_send()
408 err = stm32_qspi_tx(qspi, op); in stm32_qspi_send()
412 * -error case in stm32_qspi_send()
413 * -read memory map: prefetching must be stopped if we read the last in stm32_qspi_send()
414 * byte of device (device size - fifo size). like device size is not in stm32_qspi_send()
417 if (err || err_poll_status || qspi->fmode == CCR_FMODE_MM) in stm32_qspi_send()
421 err = stm32_qspi_wait_cmd(qspi); in stm32_qspi_send()
428 cr = readl_relaxed(qspi->io_base + QSPI_CR) | CR_ABORT; in stm32_qspi_send()
429 writel_relaxed(cr, qspi->io_base + QSPI_CR); in stm32_qspi_send()
432 timeout = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_CR, in stm32_qspi_send()
436 writel_relaxed(FCR_CTCF | FCR_CSMF, qspi->io_base + QSPI_FCR); in stm32_qspi_send()
439 dev_err(qspi->dev, "%s err:%d err_poll_status:%d abort timeout:%d\n", in stm32_qspi_send()
451 struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->controller); in stm32_qspi_poll_status() local
455 return -EOPNOTSUPP; in stm32_qspi_poll_status()
457 ret = pm_runtime_resume_and_get(qspi->dev); in stm32_qspi_poll_status()
461 mutex_lock(&qspi->lock); in stm32_qspi_poll_status()
463 writel_relaxed(mask, qspi->io_base + QSPI_PSMKR); in stm32_qspi_poll_status()
464 writel_relaxed(match, qspi->io_base + QSPI_PSMAR); in stm32_qspi_poll_status()
465 qspi->fmode = CCR_FMODE_APM; in stm32_qspi_poll_status()
466 qspi->status_timeout = timeout_ms; in stm32_qspi_poll_status()
468 ret = stm32_qspi_send(mem->spi, op); in stm32_qspi_poll_status()
469 mutex_unlock(&qspi->lock); in stm32_qspi_poll_status()
471 pm_runtime_mark_last_busy(qspi->dev); in stm32_qspi_poll_status()
472 pm_runtime_put_autosuspend(qspi->dev); in stm32_qspi_poll_status()
479 struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->controller); in stm32_qspi_exec_op() local
482 ret = pm_runtime_resume_and_get(qspi->dev); in stm32_qspi_exec_op()
486 mutex_lock(&qspi->lock); in stm32_qspi_exec_op()
487 if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes) in stm32_qspi_exec_op()
488 qspi->fmode = CCR_FMODE_INDR; in stm32_qspi_exec_op()
490 qspi->fmode = CCR_FMODE_INDW; in stm32_qspi_exec_op()
492 ret = stm32_qspi_send(mem->spi, op); in stm32_qspi_exec_op()
493 mutex_unlock(&qspi->lock); in stm32_qspi_exec_op()
495 pm_runtime_mark_last_busy(qspi->dev); in stm32_qspi_exec_op()
496 pm_runtime_put_autosuspend(qspi->dev); in stm32_qspi_exec_op()
503 struct stm32_qspi *qspi = spi_controller_get_devdata(desc->mem->spi->controller); in stm32_qspi_dirmap_create() local
505 if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT) in stm32_qspi_dirmap_create()
506 return -EOPNOTSUPP; in stm32_qspi_dirmap_create()
509 if (!qspi->mm_base && desc->info.op_tmpl.data.dir == SPI_MEM_DATA_IN) in stm32_qspi_dirmap_create()
510 return -EOPNOTSUPP; in stm32_qspi_dirmap_create()
512 if (!qspi->mm_size) in stm32_qspi_dirmap_create()
513 return -EOPNOTSUPP; in stm32_qspi_dirmap_create()
521 struct stm32_qspi *qspi = spi_controller_get_devdata(desc->mem->spi->controller); in stm32_qspi_dirmap_read() local
526 ret = pm_runtime_resume_and_get(qspi->dev); in stm32_qspi_dirmap_read()
530 mutex_lock(&qspi->lock); in stm32_qspi_dirmap_read()
535 memcpy(&op, &desc->info.op_tmpl, sizeof(struct spi_mem_op)); in stm32_qspi_dirmap_read()
536 dev_dbg(qspi->dev, "%s len = 0x%zx offs = 0x%llx buf = 0x%p\n", __func__, len, offs, buf); in stm32_qspi_dirmap_read()
539 op.addr.val = desc->info.offset + offs; in stm32_qspi_dirmap_read()
543 if (addr_max < qspi->mm_size && op.addr.buswidth) in stm32_qspi_dirmap_read()
544 qspi->fmode = CCR_FMODE_MM; in stm32_qspi_dirmap_read()
546 qspi->fmode = CCR_FMODE_INDR; in stm32_qspi_dirmap_read()
548 ret = stm32_qspi_send(desc->mem->spi, &op); in stm32_qspi_dirmap_read()
549 mutex_unlock(&qspi->lock); in stm32_qspi_dirmap_read()
551 pm_runtime_mark_last_busy(qspi->dev); in stm32_qspi_dirmap_read()
552 pm_runtime_put_autosuspend(qspi->dev); in stm32_qspi_dirmap_read()
560 struct stm32_qspi *qspi = spi_controller_get_devdata(ctrl); in stm32_qspi_transfer_one_message() local
562 struct spi_device *spi = msg->spi; in stm32_qspi_transfer_one_message()
567 return -EOPNOTSUPP; in stm32_qspi_transfer_one_message()
569 ret = pm_runtime_resume_and_get(qspi->dev); in stm32_qspi_transfer_one_message()
573 mutex_lock(&qspi->lock); in stm32_qspi_transfer_one_message()
577 list_for_each_entry(transfer, &msg->transfers, transfer_list) { in stm32_qspi_transfer_one_message()
582 dev_dbg(qspi->dev, "tx_buf:%p tx_nbits:%d rx_buf:%p rx_nbits:%d len:%d dummy_data:%d\n", in stm32_qspi_transfer_one_message()
583 transfer->tx_buf, transfer->tx_nbits, in stm32_qspi_transfer_one_message()
584 transfer->rx_buf, transfer->rx_nbits, in stm32_qspi_transfer_one_message()
585 transfer->len, transfer->dummy_data); in stm32_qspi_transfer_one_message()
588 * QSPI hardware supports dummy bytes transfer. in stm32_qspi_transfer_one_message()
590 * transfer in order to take into account QSPI block constraint in stm32_qspi_transfer_one_message()
592 if (transfer->dummy_data) { in stm32_qspi_transfer_one_message()
593 op.dummy.buswidth = transfer->tx_nbits; in stm32_qspi_transfer_one_message()
594 op.dummy.nbytes = transfer->len; in stm32_qspi_transfer_one_message()
595 dummy_bytes = transfer->len; in stm32_qspi_transfer_one_message()
598 if (list_is_last(&transfer->transfer_list, &msg->transfers)) { in stm32_qspi_transfer_one_message()
599 ret = -EINVAL; in stm32_qspi_transfer_one_message()
606 op.data.nbytes = transfer->len; in stm32_qspi_transfer_one_message()
608 if (transfer->rx_buf) { in stm32_qspi_transfer_one_message()
609 qspi->fmode = CCR_FMODE_INDR; in stm32_qspi_transfer_one_message()
610 op.data.buswidth = transfer->rx_nbits; in stm32_qspi_transfer_one_message()
612 op.data.buf.in = transfer->rx_buf; in stm32_qspi_transfer_one_message()
614 qspi->fmode = CCR_FMODE_INDW; in stm32_qspi_transfer_one_message()
615 op.data.buswidth = transfer->tx_nbits; in stm32_qspi_transfer_one_message()
617 op.data.buf.out = transfer->tx_buf; in stm32_qspi_transfer_one_message()
624 msg->actual_length += transfer->len + dummy_bytes; in stm32_qspi_transfer_one_message()
630 mutex_unlock(&qspi->lock); in stm32_qspi_transfer_one_message()
632 msg->status = ret; in stm32_qspi_transfer_one_message()
635 pm_runtime_mark_last_busy(qspi->dev); in stm32_qspi_transfer_one_message()
636 pm_runtime_put_autosuspend(qspi->dev); in stm32_qspi_transfer_one_message()
643 struct spi_controller *ctrl = spi->controller; in stm32_qspi_setup()
644 struct stm32_qspi *qspi = spi_controller_get_devdata(ctrl); in stm32_qspi_setup() local
649 if (ctrl->busy) in stm32_qspi_setup()
650 return -EBUSY; in stm32_qspi_setup()
652 if (!spi->max_speed_hz) in stm32_qspi_setup()
653 return -EINVAL; in stm32_qspi_setup()
655 mode = spi->mode & (SPI_TX_OCTAL | SPI_RX_OCTAL); in stm32_qspi_setup()
656 if (mode && gpiod_count(qspi->dev, "cs") == -ENOENT) { in stm32_qspi_setup()
657 dev_err(qspi->dev, "spi-rx-bus-width\\/spi-tx-bus-width\\/cs-gpios\n"); in stm32_qspi_setup()
658 dev_err(qspi->dev, "configuration not supported\n"); in stm32_qspi_setup()
660 return -EINVAL; in stm32_qspi_setup()
663 ret = pm_runtime_resume_and_get(qspi->dev); in stm32_qspi_setup()
667 presc = DIV_ROUND_UP(qspi->clk_rate, spi->max_speed_hz) - 1; in stm32_qspi_setup()
669 flash = &qspi->flash[spi_get_chipselect(spi, 0)]; in stm32_qspi_setup()
670 flash->cs = spi_get_chipselect(spi, 0); in stm32_qspi_setup()
671 flash->presc = presc; in stm32_qspi_setup()
673 mutex_lock(&qspi->lock); in stm32_qspi_setup()
674 qspi->cr_reg = CR_APMS | 3 << CR_FTHRES_SHIFT | CR_SSHIFT | CR_EN; in stm32_qspi_setup()
678 * is set in spi->mode and "cs-gpios" properties is found in DT in stm32_qspi_setup()
681 qspi->cr_reg |= CR_DFM; in stm32_qspi_setup()
682 dev_dbg(qspi->dev, "Dual flash mode enable"); in stm32_qspi_setup()
685 writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR); in stm32_qspi_setup()
688 qspi->dcr_reg = DCR_FSIZE_MASK; in stm32_qspi_setup()
689 writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR); in stm32_qspi_setup()
690 mutex_unlock(&qspi->lock); in stm32_qspi_setup()
692 pm_runtime_mark_last_busy(qspi->dev); in stm32_qspi_setup()
693 pm_runtime_put_autosuspend(qspi->dev); in stm32_qspi_setup()
698 static int stm32_qspi_dma_setup(struct stm32_qspi *qspi) in stm32_qspi_dma_setup() argument
701 struct device *dev = qspi->dev; in stm32_qspi_dma_setup()
708 dma_cfg.src_addr = qspi->phys_base + QSPI_DR; in stm32_qspi_dma_setup()
709 dma_cfg.dst_addr = qspi->phys_base + QSPI_DR; in stm32_qspi_dma_setup()
713 qspi->dma_chrx = dma_request_chan(dev, "rx"); in stm32_qspi_dma_setup()
714 if (IS_ERR(qspi->dma_chrx)) { in stm32_qspi_dma_setup()
715 ret = PTR_ERR(qspi->dma_chrx); in stm32_qspi_dma_setup()
716 qspi->dma_chrx = NULL; in stm32_qspi_dma_setup()
717 if (ret == -EPROBE_DEFER) in stm32_qspi_dma_setup()
720 if (dmaengine_slave_config(qspi->dma_chrx, &dma_cfg)) { in stm32_qspi_dma_setup()
722 dma_release_channel(qspi->dma_chrx); in stm32_qspi_dma_setup()
723 qspi->dma_chrx = NULL; in stm32_qspi_dma_setup()
727 qspi->dma_chtx = dma_request_chan(dev, "tx"); in stm32_qspi_dma_setup()
728 if (IS_ERR(qspi->dma_chtx)) { in stm32_qspi_dma_setup()
729 ret = PTR_ERR(qspi->dma_chtx); in stm32_qspi_dma_setup()
730 qspi->dma_chtx = NULL; in stm32_qspi_dma_setup()
732 if (dmaengine_slave_config(qspi->dma_chtx, &dma_cfg)) { in stm32_qspi_dma_setup()
734 dma_release_channel(qspi->dma_chtx); in stm32_qspi_dma_setup()
735 qspi->dma_chtx = NULL; in stm32_qspi_dma_setup()
740 init_completion(&qspi->dma_completion); in stm32_qspi_dma_setup()
742 if (ret != -EPROBE_DEFER) in stm32_qspi_dma_setup()
748 static void stm32_qspi_dma_free(struct stm32_qspi *qspi) in stm32_qspi_dma_free() argument
750 if (qspi->dma_chtx) in stm32_qspi_dma_free()
751 dma_release_channel(qspi->dma_chtx); in stm32_qspi_dma_free()
752 if (qspi->dma_chrx) in stm32_qspi_dma_free()
753 dma_release_channel(qspi->dma_chrx); in stm32_qspi_dma_free()
769 struct device *dev = &pdev->dev; in stm32_qspi_probe()
772 struct stm32_qspi *qspi; in stm32_qspi_probe() local
776 ctrl = devm_spi_alloc_host(dev, sizeof(*qspi)); in stm32_qspi_probe()
778 return -ENOMEM; in stm32_qspi_probe()
780 qspi = spi_controller_get_devdata(ctrl); in stm32_qspi_probe()
781 qspi->ctrl = ctrl; in stm32_qspi_probe()
783 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi"); in stm32_qspi_probe()
784 qspi->io_base = devm_ioremap_resource(dev, res); in stm32_qspi_probe()
785 if (IS_ERR(qspi->io_base)) in stm32_qspi_probe()
786 return PTR_ERR(qspi->io_base); in stm32_qspi_probe()
788 qspi->phys_base = res->start; in stm32_qspi_probe()
791 qspi->mm_base = devm_ioremap_resource(dev, res); in stm32_qspi_probe()
792 if (IS_ERR(qspi->mm_base)) in stm32_qspi_probe()
793 return PTR_ERR(qspi->mm_base); in stm32_qspi_probe()
795 qspi->mm_size = resource_size(res); in stm32_qspi_probe()
796 if (qspi->mm_size > STM32_QSPI_MAX_MMAP_SZ) in stm32_qspi_probe()
797 return -EINVAL; in stm32_qspi_probe()
804 dev_name(dev), qspi); in stm32_qspi_probe()
810 init_completion(&qspi->data_completion); in stm32_qspi_probe()
811 init_completion(&qspi->match_completion); in stm32_qspi_probe()
813 qspi->clk = devm_clk_get(dev, NULL); in stm32_qspi_probe()
814 if (IS_ERR(qspi->clk)) in stm32_qspi_probe()
815 return PTR_ERR(qspi->clk); in stm32_qspi_probe()
817 qspi->clk_rate = clk_get_rate(qspi->clk); in stm32_qspi_probe()
818 if (!qspi->clk_rate) in stm32_qspi_probe()
819 return -EINVAL; in stm32_qspi_probe()
821 ret = clk_prepare_enable(qspi->clk); in stm32_qspi_probe()
830 if (ret == -EPROBE_DEFER) in stm32_qspi_probe()
838 qspi->dev = dev; in stm32_qspi_probe()
839 platform_set_drvdata(pdev, qspi); in stm32_qspi_probe()
840 ret = stm32_qspi_dma_setup(qspi); in stm32_qspi_probe()
844 mutex_init(&qspi->lock); in stm32_qspi_probe()
846 ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_OCTAL in stm32_qspi_probe()
848 ctrl->setup = stm32_qspi_setup; in stm32_qspi_probe()
849 ctrl->bus_num = -1; in stm32_qspi_probe()
850 ctrl->mem_ops = &stm32_qspi_mem_ops; in stm32_qspi_probe()
851 ctrl->use_gpio_descriptors = true; in stm32_qspi_probe()
852 ctrl->transfer_one_message = stm32_qspi_transfer_one_message; in stm32_qspi_probe()
853 ctrl->num_chipselect = STM32_QSPI_MAX_NORCHIP; in stm32_qspi_probe()
854 ctrl->dev.of_node = dev->of_node; in stm32_qspi_probe()
872 pm_runtime_get_sync(qspi->dev); in stm32_qspi_probe()
873 /* disable qspi */ in stm32_qspi_probe()
874 writel_relaxed(0, qspi->io_base + QSPI_CR); in stm32_qspi_probe()
875 mutex_destroy(&qspi->lock); in stm32_qspi_probe()
876 pm_runtime_put_noidle(qspi->dev); in stm32_qspi_probe()
877 pm_runtime_disable(qspi->dev); in stm32_qspi_probe()
878 pm_runtime_set_suspended(qspi->dev); in stm32_qspi_probe()
879 pm_runtime_dont_use_autosuspend(qspi->dev); in stm32_qspi_probe()
881 stm32_qspi_dma_free(qspi); in stm32_qspi_probe()
883 clk_disable_unprepare(qspi->clk); in stm32_qspi_probe()
890 struct stm32_qspi *qspi = platform_get_drvdata(pdev); in stm32_qspi_remove() local
892 pm_runtime_get_sync(qspi->dev); in stm32_qspi_remove()
893 spi_unregister_controller(qspi->ctrl); in stm32_qspi_remove()
894 /* disable qspi */ in stm32_qspi_remove()
895 writel_relaxed(0, qspi->io_base + QSPI_CR); in stm32_qspi_remove()
896 stm32_qspi_dma_free(qspi); in stm32_qspi_remove()
897 mutex_destroy(&qspi->lock); in stm32_qspi_remove()
898 pm_runtime_put_noidle(qspi->dev); in stm32_qspi_remove()
899 pm_runtime_disable(qspi->dev); in stm32_qspi_remove()
900 pm_runtime_set_suspended(qspi->dev); in stm32_qspi_remove()
901 pm_runtime_dont_use_autosuspend(qspi->dev); in stm32_qspi_remove()
902 clk_disable_unprepare(qspi->clk); in stm32_qspi_remove()
907 struct stm32_qspi *qspi = dev_get_drvdata(dev); in stm32_qspi_runtime_suspend() local
909 clk_disable_unprepare(qspi->clk); in stm32_qspi_runtime_suspend()
916 struct stm32_qspi *qspi = dev_get_drvdata(dev); in stm32_qspi_runtime_resume() local
918 return clk_prepare_enable(qspi->clk); in stm32_qspi_runtime_resume()
930 struct stm32_qspi *qspi = dev_get_drvdata(dev); in stm32_qspi_resume() local
943 writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR); in stm32_qspi_resume()
944 writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR); in stm32_qspi_resume()
959 {.compatible = "st,stm32f469-qspi"},
968 .name = "stm32-qspi",