102 #define SIMDR2_BITLEN1(i)	(((i) - 1) << 24) /* Data Size (8-32 bits) */
107 #define SISCR_BRPS_MASK		GENMASK(12, 8)	/* Prescaler Setting (1-32) */
140 #define SIFCTR_TFWM_32		(1UL << 29)	/*  Transfer Request when 32 empty stages */
155 #define SIFCTR_RFWM_32		(4 << 13)	/*  Transfer Request when 32 valid stages */
281 		if (!div_pow && div <= 32 && div > 2)  in sh_msiof_spi_set_clk_regs()
289 		for (; brps > 32; div_pow++)  in sh_msiof_spi_set_clk_regs()
292 		/* Set transfer rate composite divisor to 2^5 * 32 = 1024 */  in sh_msiof_spi_set_clk_regs()
296 		brps = 32;  in sh_msiof_spi_set_clk_regs()
417 	int k;  in sh_msiof_spi_write_fifo_8()  local
419 	for (k = 0; k < words; k++)  in sh_msiof_spi_write_fifo_8()
420 		sh_msiof_write(p, SITFDR, buf_8[k] << fs);  in sh_msiof_spi_write_fifo_8()
427 	int k;  in sh_msiof_spi_write_fifo_16()  local
429 	for (k = 0; k < words; k++)  in sh_msiof_spi_write_fifo_16()
430 		sh_msiof_write(p, SITFDR, buf_16[k] << fs);  in sh_msiof_spi_write_fifo_16()
437 	int k;  in sh_msiof_spi_write_fifo_16u()  local
439 	for (k = 0; k < words; k++)  in sh_msiof_spi_write_fifo_16u()
440 		sh_msiof_write(p, SITFDR, get_unaligned(&buf_16[k]) << fs);  in sh_msiof_spi_write_fifo_16u()
447 	int k;  in sh_msiof_spi_write_fifo_32()  local
449 	for (k = 0; k < words; k++)  in sh_msiof_spi_write_fifo_32()
450 		sh_msiof_write(p, SITFDR, buf_32[k] << fs);  in sh_msiof_spi_write_fifo_32()
457 	int k;  in sh_msiof_spi_write_fifo_32u()  local
459 	for (k = 0; k < words; k++)  in sh_msiof_spi_write_fifo_32u()
460 		sh_msiof_write(p, SITFDR, get_unaligned(&buf_32[k]) << fs);  in sh_msiof_spi_write_fifo_32u()
467 	int k;  in sh_msiof_spi_write_fifo_s32()  local
469 	for (k = 0; k < words; k++)  in sh_msiof_spi_write_fifo_s32()
470 		sh_msiof_write(p, SITFDR, swab32(buf_32[k] << fs));  in sh_msiof_spi_write_fifo_s32()
477 	int k;  in sh_msiof_spi_write_fifo_s32u()  local
479 	for (k = 0; k < words; k++)  in sh_msiof_spi_write_fifo_s32u()
480 		sh_msiof_write(p, SITFDR, swab32(get_unaligned(&buf_32[k]) << fs));  in sh_msiof_spi_write_fifo_s32u()
487 	int k;  in sh_msiof_spi_read_fifo_8()  local
489 	for (k = 0; k < words; k++)  in sh_msiof_spi_read_fifo_8()
490 		buf_8[k] = sh_msiof_read(p, SIRFDR) >> fs;  in sh_msiof_spi_read_fifo_8()
497 	int k;  in sh_msiof_spi_read_fifo_16()  local
499 	for (k = 0; k < words; k++)  in sh_msiof_spi_read_fifo_16()
500 		buf_16[k] = sh_msiof_read(p, SIRFDR) >> fs;  in sh_msiof_spi_read_fifo_16()
507 	int k;  in sh_msiof_spi_read_fifo_16u()  local
509 	for (k = 0; k < words; k++)  in sh_msiof_spi_read_fifo_16u()
510 		put_unaligned(sh_msiof_read(p, SIRFDR) >> fs, &buf_16[k]);  in sh_msiof_spi_read_fifo_16u()
517 	int k;  in sh_msiof_spi_read_fifo_32()  local
519 	for (k = 0; k < words; k++)  in sh_msiof_spi_read_fifo_32()
520 		buf_32[k] = sh_msiof_read(p, SIRFDR) >> fs;  in sh_msiof_spi_read_fifo_32()
527 	int k;  in sh_msiof_spi_read_fifo_32u()  local
529 	for (k = 0; k < words; k++)  in sh_msiof_spi_read_fifo_32u()
530 		put_unaligned(sh_msiof_read(p, SIRFDR) >> fs, &buf_32[k]);  in sh_msiof_spi_read_fifo_32u()
537 	int k;  in sh_msiof_spi_read_fifo_s32()  local
539 	for (k = 0; k < words; k++)  in sh_msiof_spi_read_fifo_s32()
540 		buf_32[k] = swab32(sh_msiof_read(p, SIRFDR) >> fs);  in sh_msiof_spi_read_fifo_s32()
547 	int k;  in sh_msiof_spi_read_fifo_s32u()  local
549 	for (k = 0; k < words; k++)  in sh_msiof_spi_read_fifo_s32u()
550 		put_unaligned(swab32(sh_msiof_read(p, SIRFDR) >> fs), &buf_32[k]);  in sh_msiof_spi_read_fifo_s32u()
691 	fifo_shift = 32 - bits;  in sh_msiof_spi_txrx_once()
794 	/* setup msiof transfer mode registers (32-bit words) */  in sh_msiof_dma_once()
795 	sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4);  in sh_msiof_dma_once()
936 		 *  DMA supports 32-bit words only, hence pack 8-bit and 16-bit  in sh_msiof_transfer_one()
979 		bits = 32;  in sh_msiof_transfer_one()
1053 	.bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32),
1062 			      SPI_BPW_MASK(24) | SPI_BPW_MASK(32),
1071 			      SPI_BPW_MASK(24) | SPI_BPW_MASK(32),
1080 			      SPI_BPW_MASK(24) | SPI_BPW_MASK(32),