Lines Matching refs:sdd
115 #define TX_FIFO_LVL(v, sdd) (((v) & (sdd)->tx_fifomask) >> \ argument
116 __ffs((sdd)->tx_fifomask))
117 #define RX_FIFO_LVL(v, sdd) (((v) & (sdd)->rx_fifomask) >> \ argument
118 __ffs((sdd)->rx_fifomask))
227 static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd) in s3c64xx_flush_fifo() argument
229 void __iomem *regs = sdd->regs; in s3c64xx_flush_fifo()
248 } while (TX_FIFO_LVL(val, sdd) && --loops); in s3c64xx_flush_fifo()
251 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n"); in s3c64xx_flush_fifo()
257 if (RX_FIFO_LVL(val, sdd)) in s3c64xx_flush_fifo()
264 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n"); in s3c64xx_flush_fifo()
277 struct s3c64xx_spi_driver_data *sdd; in s3c64xx_spi_dmacb() local
282 sdd = container_of(data, in s3c64xx_spi_dmacb()
285 sdd = container_of(data, in s3c64xx_spi_dmacb()
288 spin_lock_irqsave(&sdd->lock, flags); in s3c64xx_spi_dmacb()
291 sdd->state &= ~RXBUSY; in s3c64xx_spi_dmacb()
292 if (!(sdd->state & TXBUSY)) in s3c64xx_spi_dmacb()
293 complete(&sdd->xfer_completion); in s3c64xx_spi_dmacb()
295 sdd->state &= ~TXBUSY; in s3c64xx_spi_dmacb()
296 if (!(sdd->state & RXBUSY)) in s3c64xx_spi_dmacb()
297 complete(&sdd->xfer_completion); in s3c64xx_spi_dmacb()
300 spin_unlock_irqrestore(&sdd->lock, flags); in s3c64xx_spi_dmacb()
306 struct s3c64xx_spi_driver_data *sdd; in s3c64xx_prepare_dma() local
314 sdd = container_of((void *)dma, in s3c64xx_prepare_dma()
316 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA; in s3c64xx_prepare_dma()
317 config.src_addr_width = sdd->cur_bpw / 8; in s3c64xx_prepare_dma()
320 sdd = container_of((void *)dma, in s3c64xx_prepare_dma()
322 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA; in s3c64xx_prepare_dma()
323 config.dst_addr_width = sdd->cur_bpw / 8; in s3c64xx_prepare_dma()
334 dev_err(&sdd->pdev->dev, "unable to prepare %s scatterlist", in s3c64xx_prepare_dma()
345 dev_err(&sdd->pdev->dev, "DMA submission failed"); in s3c64xx_prepare_dma()
355 struct s3c64xx_spi_driver_data *sdd = in s3c64xx_spi_set_cs() local
358 if (sdd->cntrlr_info->no_cs) in s3c64xx_spi_set_cs()
362 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) { in s3c64xx_spi_set_cs()
363 writel(0, sdd->regs + S3C64XX_SPI_CS_REG); in s3c64xx_spi_set_cs()
365 u32 ssel = readl(sdd->regs + S3C64XX_SPI_CS_REG); in s3c64xx_spi_set_cs()
369 writel(ssel, sdd->regs + S3C64XX_SPI_CS_REG); in s3c64xx_spi_set_cs()
372 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) in s3c64xx_spi_set_cs()
374 sdd->regs + S3C64XX_SPI_CS_REG); in s3c64xx_spi_set_cs()
380 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(spi); in s3c64xx_spi_prepare_transfer() local
382 if (is_polling(sdd)) in s3c64xx_spi_prepare_transfer()
386 sdd->rx_dma.ch = dma_request_chan(&sdd->pdev->dev, "rx"); in s3c64xx_spi_prepare_transfer()
387 if (IS_ERR(sdd->rx_dma.ch)) { in s3c64xx_spi_prepare_transfer()
388 dev_err(&sdd->pdev->dev, "Failed to get RX DMA channel\n"); in s3c64xx_spi_prepare_transfer()
389 sdd->rx_dma.ch = NULL; in s3c64xx_spi_prepare_transfer()
393 sdd->tx_dma.ch = dma_request_chan(&sdd->pdev->dev, "tx"); in s3c64xx_spi_prepare_transfer()
394 if (IS_ERR(sdd->tx_dma.ch)) { in s3c64xx_spi_prepare_transfer()
395 dev_err(&sdd->pdev->dev, "Failed to get TX DMA channel\n"); in s3c64xx_spi_prepare_transfer()
396 dma_release_channel(sdd->rx_dma.ch); in s3c64xx_spi_prepare_transfer()
397 sdd->tx_dma.ch = NULL; in s3c64xx_spi_prepare_transfer()
398 sdd->rx_dma.ch = NULL; in s3c64xx_spi_prepare_transfer()
402 spi->dma_rx = sdd->rx_dma.ch; in s3c64xx_spi_prepare_transfer()
403 spi->dma_tx = sdd->tx_dma.ch; in s3c64xx_spi_prepare_transfer()
410 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(spi); in s3c64xx_spi_unprepare_transfer() local
412 if (is_polling(sdd)) in s3c64xx_spi_unprepare_transfer()
416 if (sdd->rx_dma.ch && sdd->tx_dma.ch) { in s3c64xx_spi_unprepare_transfer()
417 dma_release_channel(sdd->rx_dma.ch); in s3c64xx_spi_unprepare_transfer()
418 dma_release_channel(sdd->tx_dma.ch); in s3c64xx_spi_unprepare_transfer()
419 sdd->rx_dma.ch = NULL; in s3c64xx_spi_unprepare_transfer()
420 sdd->tx_dma.ch = NULL; in s3c64xx_spi_unprepare_transfer()
430 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); in s3c64xx_spi_can_dma() local
432 if (sdd->rx_dma.ch && sdd->tx_dma.ch) in s3c64xx_spi_can_dma()
433 return xfer->len >= sdd->fifo_depth; in s3c64xx_spi_can_dma()
462 static void s3c64xx_iowrite_rep(const struct s3c64xx_spi_driver_data *sdd, in s3c64xx_iowrite_rep() argument
465 void __iomem *addr = sdd->regs + S3C64XX_SPI_TX_DATA; in s3c64xx_iowrite_rep()
469 switch (sdd->cur_bpw) { in s3c64xx_iowrite_rep()
474 if (sdd->port_conf->use_32bit_io) in s3c64xx_iowrite_rep()
480 if (sdd->port_conf->use_32bit_io) in s3c64xx_iowrite_rep()
488 static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd, in s3c64xx_enable_datapath() argument
491 void __iomem *regs = sdd->regs; in s3c64xx_enable_datapath()
509 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) in s3c64xx_enable_datapath()
515 sdd->state |= TXBUSY; in s3c64xx_enable_datapath()
519 ret = s3c64xx_prepare_dma(&sdd->tx_dma, &xfer->tx_sg); in s3c64xx_enable_datapath()
521 s3c64xx_iowrite_rep(sdd, xfer); in s3c64xx_enable_datapath()
526 sdd->state |= RXBUSY; in s3c64xx_enable_datapath()
528 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL in s3c64xx_enable_datapath()
529 && !(sdd->cur_mode & SPI_CPHA)) in s3c64xx_enable_datapath()
535 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) in s3c64xx_enable_datapath()
538 ret = s3c64xx_prepare_dma(&sdd->rx_dma, &xfer->rx_sg); in s3c64xx_enable_datapath()
551 static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd, in s3c64xx_spi_wait_for_timeout() argument
554 void __iomem *regs = sdd->regs; in s3c64xx_spi_wait_for_timeout()
557 u32 max_fifo = sdd->fifo_depth; in s3c64xx_spi_wait_for_timeout()
564 } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val); in s3c64xx_spi_wait_for_timeout()
567 return RX_FIFO_LVL(status, sdd); in s3c64xx_spi_wait_for_timeout()
570 static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd, in s3c64xx_wait_for_dma() argument
573 void __iomem *regs = sdd->regs; in s3c64xx_wait_for_dma()
579 ms = xfer->len * 8 * 1000 / sdd->cur_speed; in s3c64xx_wait_for_dma()
584 val = wait_for_completion_timeout(&sdd->xfer_completion, val); in s3c64xx_wait_for_dma()
598 while ((TX_FIFO_LVL(status, sdd) in s3c64xx_wait_for_dma()
599 || !S3C64XX_SPI_ST_TX_DONE(status, sdd)) in s3c64xx_wait_for_dma()
614 static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd, in s3c64xx_wait_for_pio() argument
617 void __iomem *regs = sdd->regs; in s3c64xx_wait_for_pio()
627 time_us = (xfer->len * 8 * 1000 * 1000) / sdd->cur_speed; in s3c64xx_wait_for_pio()
633 if (RX_FIFO_LVL(status, sdd) < xfer->len) in s3c64xx_wait_for_pio()
638 if (!wait_for_completion_timeout(&sdd->xfer_completion, val)) in s3c64xx_wait_for_pio()
645 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val); in s3c64xx_wait_for_pio()
652 sdd->state &= ~TXBUSY; in s3c64xx_wait_for_pio()
664 loops = xfer->len / sdd->fifo_depth; in s3c64xx_wait_for_pio()
668 cpy_len = s3c64xx_spi_wait_for_timeout(sdd, in s3c64xx_wait_for_pio()
671 switch (sdd->cur_bpw) { in s3c64xx_wait_for_pio()
688 sdd->state &= ~RXBUSY; in s3c64xx_wait_for_pio()
693 static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) in s3c64xx_spi_config() argument
695 void __iomem *regs = sdd->regs; in s3c64xx_spi_config()
698 int div = sdd->port_conf->clk_div; in s3c64xx_spi_config()
701 if (!sdd->port_conf->clk_from_cmu) { in s3c64xx_spi_config()
713 if (sdd->cur_mode & SPI_CPOL) in s3c64xx_spi_config()
716 if (sdd->cur_mode & SPI_CPHA) in s3c64xx_spi_config()
726 switch (sdd->cur_bpw) { in s3c64xx_spi_config()
741 if ((sdd->cur_mode & SPI_LOOP) && sdd->port_conf->has_loopback) in s3c64xx_spi_config()
748 if (sdd->port_conf->clk_from_cmu) { in s3c64xx_spi_config()
749 ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * div); in s3c64xx_spi_config()
752 sdd->cur_speed = clk_get_rate(sdd->src_clk) / div; in s3c64xx_spi_config()
757 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / div - 1) in s3c64xx_spi_config()
775 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); in s3c64xx_spi_prepare_message() local
782 writel(0, sdd->regs + S3C64XX_SPI_FB_CLK); in s3c64xx_spi_prepare_message()
784 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK); in s3c64xx_spi_prepare_message()
800 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); in s3c64xx_spi_transfer_one() local
801 const unsigned int fifo_len = sdd->fifo_depth; in s3c64xx_spi_transfer_one()
814 reinit_completion(&sdd->xfer_completion); in s3c64xx_spi_transfer_one()
820 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) { in s3c64xx_spi_transfer_one()
821 sdd->cur_bpw = bpw; in s3c64xx_spi_transfer_one()
822 sdd->cur_speed = speed; in s3c64xx_spi_transfer_one()
823 sdd->cur_mode = spi->mode; in s3c64xx_spi_transfer_one()
824 status = s3c64xx_spi_config(sdd); in s3c64xx_spi_transfer_one()
829 if (!is_polling(sdd) && xfer->len >= fifo_len && in s3c64xx_spi_transfer_one()
830 sdd->rx_dma.ch && sdd->tx_dma.ch) { in s3c64xx_spi_transfer_one()
846 reinit_completion(&sdd->xfer_completion); in s3c64xx_spi_transfer_one()
860 val = readl(sdd->regs + S3C64XX_SPI_MODE_CFG); in s3c64xx_spi_transfer_one()
863 writel(val, sdd->regs + S3C64XX_SPI_MODE_CFG); in s3c64xx_spi_transfer_one()
866 val = readl(sdd->regs + S3C64XX_SPI_INT_EN); in s3c64xx_spi_transfer_one()
868 sdd->regs + S3C64XX_SPI_INT_EN); in s3c64xx_spi_transfer_one()
872 spin_lock_irqsave(&sdd->lock, flags); in s3c64xx_spi_transfer_one()
875 sdd->state &= ~RXBUSY; in s3c64xx_spi_transfer_one()
876 sdd->state &= ~TXBUSY; in s3c64xx_spi_transfer_one()
881 status = s3c64xx_enable_datapath(sdd, xfer, use_dma); in s3c64xx_spi_transfer_one()
883 spin_unlock_irqrestore(&sdd->lock, flags); in s3c64xx_spi_transfer_one()
891 status = s3c64xx_wait_for_dma(sdd, xfer); in s3c64xx_spi_transfer_one()
893 status = s3c64xx_wait_for_pio(sdd, xfer, use_irq); in s3c64xx_spi_transfer_one()
899 (sdd->state & RXBUSY) ? 'f' : 'p', in s3c64xx_spi_transfer_one()
900 (sdd->state & TXBUSY) ? 'f' : 'p', in s3c64xx_spi_transfer_one()
906 if (xfer->tx_buf && (sdd->state & TXBUSY)) { in s3c64xx_spi_transfer_one()
907 dmaengine_pause(sdd->tx_dma.ch); in s3c64xx_spi_transfer_one()
908 dmaengine_tx_status(sdd->tx_dma.ch, sdd->tx_dma.cookie, &s); in s3c64xx_spi_transfer_one()
909 dmaengine_terminate_all(sdd->tx_dma.ch); in s3c64xx_spi_transfer_one()
913 if (xfer->rx_buf && (sdd->state & RXBUSY)) { in s3c64xx_spi_transfer_one()
914 dmaengine_pause(sdd->rx_dma.ch); in s3c64xx_spi_transfer_one()
915 dmaengine_tx_status(sdd->rx_dma.ch, sdd->rx_dma.cookie, &s); in s3c64xx_spi_transfer_one()
916 dmaengine_terminate_all(sdd->rx_dma.ch); in s3c64xx_spi_transfer_one()
921 s3c64xx_flush_fifo(sdd); in s3c64xx_spi_transfer_one()
987 struct s3c64xx_spi_driver_data *sdd; in s3c64xx_spi_setup() local
991 sdd = spi_controller_get_devdata(spi->controller); in s3c64xx_spi_setup()
1006 pm_runtime_get_sync(&sdd->pdev->dev); in s3c64xx_spi_setup()
1008 div = sdd->port_conf->clk_div; in s3c64xx_spi_setup()
1011 if (!sdd->port_conf->clk_from_cmu) { in s3c64xx_spi_setup()
1015 speed = clk_get_rate(sdd->src_clk) / div / (0 + 1); in s3c64xx_spi_setup()
1020 psr = clk_get_rate(sdd->src_clk) / div / spi->max_speed_hz - 1; in s3c64xx_spi_setup()
1025 speed = clk_get_rate(sdd->src_clk) / div / (psr + 1); in s3c64xx_spi_setup()
1035 speed = clk_get_rate(sdd->src_clk) / div / (psr + 1); in s3c64xx_spi_setup()
1046 pm_runtime_mark_last_busy(&sdd->pdev->dev); in s3c64xx_spi_setup()
1047 pm_runtime_put_autosuspend(&sdd->pdev->dev); in s3c64xx_spi_setup()
1053 pm_runtime_mark_last_busy(&sdd->pdev->dev); in s3c64xx_spi_setup()
1054 pm_runtime_put_autosuspend(&sdd->pdev->dev); in s3c64xx_spi_setup()
1080 struct s3c64xx_spi_driver_data *sdd = data; in s3c64xx_spi_irq() local
1081 struct spi_controller *spi = sdd->host; in s3c64xx_spi_irq()
1084 val = readl(sdd->regs + S3C64XX_SPI_STATUS); in s3c64xx_spi_irq()
1104 complete(&sdd->xfer_completion); in s3c64xx_spi_irq()
1106 val = readl(sdd->regs + S3C64XX_SPI_INT_EN); in s3c64xx_spi_irq()
1108 sdd->regs + S3C64XX_SPI_INT_EN); in s3c64xx_spi_irq()
1112 writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR); in s3c64xx_spi_irq()
1113 writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR); in s3c64xx_spi_irq()
1118 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd) in s3c64xx_spi_hwinit() argument
1120 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; in s3c64xx_spi_hwinit()
1121 void __iomem *regs = sdd->regs; in s3c64xx_spi_hwinit()
1124 sdd->cur_speed = 0; in s3c64xx_spi_hwinit()
1127 writel(0, sdd->regs + S3C64XX_SPI_CS_REG); in s3c64xx_spi_hwinit()
1128 else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) in s3c64xx_spi_hwinit()
1129 writel(S3C64XX_SPI_CS_SIG_INACT, sdd->regs + S3C64XX_SPI_CS_REG); in s3c64xx_spi_hwinit()
1134 if (!sdd->port_conf->clk_from_cmu) in s3c64xx_spi_hwinit()
1155 s3c64xx_flush_fifo(sdd); in s3c64xx_spi_hwinit()
1205 struct s3c64xx_spi_driver_data *sdd) in s3c64xx_spi_set_port_id() argument
1207 const struct s3c64xx_spi_port_config *port_conf = sdd->port_conf; in s3c64xx_spi_set_port_id()
1218 sdd->port_id = ret; in s3c64xx_spi_set_port_id()
1223 sdd->port_id = pdev->id; in s3c64xx_spi_set_port_id()
1229 static void s3c64xx_spi_set_fifomask(struct s3c64xx_spi_driver_data *sdd) in s3c64xx_spi_set_fifomask() argument
1231 const struct s3c64xx_spi_port_config *port_conf = sdd->port_conf; in s3c64xx_spi_set_fifomask()
1234 sdd->rx_fifomask = port_conf->rx_fifomask; in s3c64xx_spi_set_fifomask()
1236 sdd->rx_fifomask = FIFO_LVL_MASK(sdd) << in s3c64xx_spi_set_fifomask()
1240 sdd->tx_fifomask = port_conf->tx_fifomask; in s3c64xx_spi_set_fifomask()
1242 sdd->tx_fifomask = FIFO_LVL_MASK(sdd) << in s3c64xx_spi_set_fifomask()
1249 struct s3c64xx_spi_driver_data *sdd; in s3c64xx_spi_probe() local
1269 host = devm_spi_alloc_host(&pdev->dev, sizeof(*sdd)); in s3c64xx_spi_probe()
1276 sdd = spi_controller_get_devdata(host); in s3c64xx_spi_probe()
1277 sdd->port_conf = s3c64xx_spi_get_port_config(pdev); in s3c64xx_spi_probe()
1278 sdd->host = host; in s3c64xx_spi_probe()
1279 sdd->cntrlr_info = sci; in s3c64xx_spi_probe()
1280 sdd->pdev = pdev; in s3c64xx_spi_probe()
1282 ret = s3c64xx_spi_set_port_id(pdev, sdd); in s3c64xx_spi_probe()
1286 if (sdd->port_conf->fifo_depth) in s3c64xx_spi_probe()
1287 sdd->fifo_depth = sdd->port_conf->fifo_depth; in s3c64xx_spi_probe()
1289 &sdd->fifo_depth)) in s3c64xx_spi_probe()
1290 sdd->fifo_depth = FIFO_DEPTH(sdd); in s3c64xx_spi_probe()
1292 s3c64xx_spi_set_fifomask(sdd); in s3c64xx_spi_probe()
1294 sdd->cur_bpw = 8; in s3c64xx_spi_probe()
1296 sdd->tx_dma.direction = DMA_MEM_TO_DEV; in s3c64xx_spi_probe()
1297 sdd->rx_dma.direction = DMA_DEV_TO_MEM; in s3c64xx_spi_probe()
1315 if (sdd->port_conf->has_loopback) in s3c64xx_spi_probe()
1318 if (!is_polling(sdd)) in s3c64xx_spi_probe()
1321 sdd->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem_res); in s3c64xx_spi_probe()
1322 if (IS_ERR(sdd->regs)) in s3c64xx_spi_probe()
1323 return PTR_ERR(sdd->regs); in s3c64xx_spi_probe()
1324 sdd->sfr_start = mem_res->start; in s3c64xx_spi_probe()
1331 sdd->clk = devm_clk_get_enabled(&pdev->dev, "spi"); in s3c64xx_spi_probe()
1332 if (IS_ERR(sdd->clk)) in s3c64xx_spi_probe()
1333 return dev_err_probe(&pdev->dev, PTR_ERR(sdd->clk), in s3c64xx_spi_probe()
1337 sdd->src_clk = devm_clk_get_enabled(&pdev->dev, clk_name); in s3c64xx_spi_probe()
1338 if (IS_ERR(sdd->src_clk)) in s3c64xx_spi_probe()
1339 return dev_err_probe(&pdev->dev, PTR_ERR(sdd->src_clk), in s3c64xx_spi_probe()
1343 if (sdd->port_conf->clk_ioclk) { in s3c64xx_spi_probe()
1344 sdd->ioclk = devm_clk_get_enabled(&pdev->dev, "spi_ioclk"); in s3c64xx_spi_probe()
1345 if (IS_ERR(sdd->ioclk)) in s3c64xx_spi_probe()
1346 return dev_err_probe(&pdev->dev, PTR_ERR(sdd->ioclk), in s3c64xx_spi_probe()
1357 s3c64xx_spi_hwinit(sdd); in s3c64xx_spi_probe()
1359 spin_lock_init(&sdd->lock); in s3c64xx_spi_probe()
1360 init_completion(&sdd->xfer_completion); in s3c64xx_spi_probe()
1363 "spi-s3c64xx", sdd); in s3c64xx_spi_probe()
1372 sdd->regs + S3C64XX_SPI_INT_EN); in s3c64xx_spi_probe()
1383 mem_res, sdd->fifo_depth); in s3c64xx_spi_probe()
1401 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); in s3c64xx_spi_remove() local
1405 writel(0, sdd->regs + S3C64XX_SPI_INT_EN); in s3c64xx_spi_remove()
1407 if (!is_polling(sdd)) { in s3c64xx_spi_remove()
1408 dma_release_channel(sdd->rx_dma.ch); in s3c64xx_spi_remove()
1409 dma_release_channel(sdd->tx_dma.ch); in s3c64xx_spi_remove()
1421 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); in s3c64xx_spi_suspend() local
1432 sdd->cur_speed = 0; /* Output Clock is stopped */ in s3c64xx_spi_suspend()
1440 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); in s3c64xx_spi_resume() local
1441 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; in s3c64xx_spi_resume()
1459 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); in s3c64xx_spi_runtime_suspend() local
1461 clk_disable_unprepare(sdd->clk); in s3c64xx_spi_runtime_suspend()
1462 clk_disable_unprepare(sdd->src_clk); in s3c64xx_spi_runtime_suspend()
1463 clk_disable_unprepare(sdd->ioclk); in s3c64xx_spi_runtime_suspend()
1471 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); in s3c64xx_spi_runtime_resume() local
1474 if (sdd->port_conf->clk_ioclk) { in s3c64xx_spi_runtime_resume()
1475 ret = clk_prepare_enable(sdd->ioclk); in s3c64xx_spi_runtime_resume()
1480 ret = clk_prepare_enable(sdd->src_clk); in s3c64xx_spi_runtime_resume()
1484 ret = clk_prepare_enable(sdd->clk); in s3c64xx_spi_runtime_resume()
1488 s3c64xx_spi_hwinit(sdd); in s3c64xx_spi_runtime_resume()
1492 sdd->regs + S3C64XX_SPI_INT_EN); in s3c64xx_spi_runtime_resume()
1497 clk_disable_unprepare(sdd->src_clk); in s3c64xx_spi_runtime_resume()
1499 clk_disable_unprepare(sdd->ioclk); in s3c64xx_spi_runtime_resume()