Lines Matching +full:quad +full:- +full:phase
1 // SPDX-License-Identifier: GPL-2.0
8 * Based on spi-sh.c:
21 #include <linux/dma-mapping.h>
40 #define RSPI_SPND 0x0e /* Next-Access Delay Register */
68 /* SPCR - Control Register */
77 #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */
78 /* QSPI on R-Car Gen2 only */
79 #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */
80 #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */
82 /* SSLP - Slave Select Polarity Register */
85 /* SPPCR - Pin Control Register */
89 #define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */
92 #define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */
93 #define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */
95 /* SPSR - Status Register */
104 /* SPSCR - Sequence Control Register */
107 /* SPSSR - Sequence Status Register */
111 /* SPDCR - Data Control Register */
125 #define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) (SH) */
127 /* SPCKD - Clock Delay Register */
128 #define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */
130 /* SSLND - Slave Select Negation Delay Register */
131 #define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */
133 /* SPND - Next-Access Delay Register */
134 #define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */
136 /* SPCR2 - Control Register 2 */
137 #define SPCR2_PTE 0x08 /* Parity Self-Test Enable */
142 /* SPCMDn - Command Registers */
145 #define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */
148 #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK)
161 #define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */
166 #define SPCMD_CPHA 0x0001 /* Clock Phase Setting */
168 /* SPBFCR - Buffer Control Register */
173 /* QSPI on R-Car Gen2 */
187 spinlock_t lock; /* Protects RMW-access to RSPI_SSLP */
201 iowrite8(data, rspi->addr + offset); in rspi_write8()
206 iowrite16(data, rspi->addr + offset); in rspi_write16()
211 iowrite32(data, rspi->addr + offset); in rspi_write32()
216 return ioread8(rspi->addr + offset); in rspi_read8()
221 return ioread16(rspi->addr + offset); in rspi_read16()
226 if (rspi->byte_access) in rspi_write_data()
234 if (rspi->byte_access) in rspi_read_data()
258 clksrc = clk_get_rate(rspi->clk); in rspi_set_rate()
259 spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz) - 1; in rspi_set_rate()
262 spbr = DIV_ROUND_UP(spbr + 1, 2) - 1; in rspi_set_rate()
266 rspi->spcmd |= SPCMD_BRDV(brdv); in rspi_set_rate()
267 rspi->speed_hz = DIV_ROUND_UP(clksrc, (2U << brdv) * (spbr + 1)); in rspi_set_rate()
276 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); in rspi_set_config_register()
281 /* Disable dummy transmission, set 16-bit word access, 1 frame */ in rspi_set_config_register()
283 rspi->byte_access = 0; in rspi_set_config_register()
285 /* Sets RSPCK, SSL, next-access delay value */ in rspi_set_config_register()
295 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size); in rspi_set_config_register()
296 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); in rspi_set_config_register()
310 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); in rspi_rz_set_config_register()
317 rspi->byte_access = 1; in rspi_rz_set_config_register()
319 /* Sets RSPCK, SSL, next-access delay value */ in rspi_rz_set_config_register()
326 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size); in rspi_rz_set_config_register()
327 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); in rspi_rz_set_config_register()
344 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); in qspi_set_config_register()
347 clksrc = clk_get_rate(rspi->clk); in qspi_set_config_register()
348 if (rspi->speed_hz >= clksrc) { in qspi_set_config_register()
350 rspi->speed_hz = clksrc; in qspi_set_config_register()
352 spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz); in qspi_set_config_register()
358 rspi->speed_hz = DIV_ROUND_UP(clksrc, (2U << brdv) * spbr); in qspi_set_config_register()
361 rspi->spcmd |= SPCMD_BRDV(brdv); in qspi_set_config_register()
365 rspi->byte_access = 1; in qspi_set_config_register()
367 /* Sets RSPCK, SSL, next-access delay value */ in qspi_set_config_register()
374 rspi->spcmd |= SPCMD_SPB_8BIT; in qspi_set_config_register()
376 rspi->spcmd |= SPCMD_SPB_16BIT; in qspi_set_config_register()
378 rspi->spcmd |= SPCMD_SPB_32BIT; in qspi_set_config_register()
380 rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN; in qspi_set_config_register()
392 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); in qspi_set_config_register()
463 rspi->spsr = rspi_read8(rspi, RSPI_SPSR); in rspi_wait_for_interrupt()
464 if (rspi->spsr & wait_mask) in rspi_wait_for_interrupt()
468 ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ); in rspi_wait_for_interrupt()
469 if (ret == 0 && !(rspi->spsr & wait_mask)) in rspi_wait_for_interrupt()
470 return -ETIMEDOUT; in rspi_wait_for_interrupt()
489 dev_err(&rspi->ctlr->dev, "transmit timeout\n"); in rspi_data_out()
503 dev_err(&rspi->ctlr->dev, "receive timeout\n"); in rspi_data_in()
513 while (n-- > 0) { in rspi_pio_transfer()
534 rspi->dma_callbacked = 1; in rspi_dma_complete()
535 wake_up_interruptible(&rspi->wait); in rspi_dma_complete()
549 desc_rx = dmaengine_prep_slave_sg(rspi->ctlr->dma_rx, rx->sgl, in rspi_dma_transfer()
550 rx->nents, DMA_DEV_TO_MEM, in rspi_dma_transfer()
553 ret = -EAGAIN; in rspi_dma_transfer()
557 desc_rx->callback = rspi_dma_complete; in rspi_dma_transfer()
558 desc_rx->callback_param = rspi; in rspi_dma_transfer()
569 desc_tx = dmaengine_prep_slave_sg(rspi->ctlr->dma_tx, tx->sgl, in rspi_dma_transfer()
570 tx->nents, DMA_MEM_TO_DEV, in rspi_dma_transfer()
573 ret = -EAGAIN; in rspi_dma_transfer()
579 desc_tx->callback = NULL; in rspi_dma_transfer()
581 desc_tx->callback = rspi_dma_complete; in rspi_dma_transfer()
582 desc_tx->callback_param = rspi; in rspi_dma_transfer()
598 disable_irq(other_irq = rspi->tx_irq); in rspi_dma_transfer()
599 if (rx && rspi->rx_irq != other_irq) in rspi_dma_transfer()
600 disable_irq(rspi->rx_irq); in rspi_dma_transfer()
603 rspi->dma_callbacked = 0; in rspi_dma_transfer()
607 dma_async_issue_pending(rspi->ctlr->dma_rx); in rspi_dma_transfer()
609 dma_async_issue_pending(rspi->ctlr->dma_tx); in rspi_dma_transfer()
611 ret = wait_event_interruptible_timeout(rspi->wait, in rspi_dma_transfer()
612 rspi->dma_callbacked, HZ); in rspi_dma_transfer()
613 if (ret > 0 && rspi->dma_callbacked) { in rspi_dma_transfer()
616 dmaengine_synchronize(rspi->ctlr->dma_tx); in rspi_dma_transfer()
618 dmaengine_synchronize(rspi->ctlr->dma_rx); in rspi_dma_transfer()
621 dev_err(&rspi->ctlr->dev, "DMA timeout\n"); in rspi_dma_transfer()
622 ret = -ETIMEDOUT; in rspi_dma_transfer()
625 dmaengine_terminate_sync(rspi->ctlr->dma_tx); in rspi_dma_transfer()
627 dmaengine_terminate_sync(rspi->ctlr->dma_rx); in rspi_dma_transfer()
633 enable_irq(rspi->tx_irq); in rspi_dma_transfer()
634 if (rx && rspi->rx_irq != other_irq) in rspi_dma_transfer()
635 enable_irq(rspi->rx_irq); in rspi_dma_transfer()
641 dmaengine_terminate_sync(rspi->ctlr->dma_rx); in rspi_dma_transfer()
643 if (ret == -EAGAIN) { in rspi_dma_transfer()
644 dev_warn_once(&rspi->ctlr->dev, in rspi_dma_transfer()
683 return xfer->len > rspi->ops->fifo_size; in __rspi_can_dma()
697 if (!rspi->ctlr->can_dma || !__rspi_can_dma(rspi, xfer)) in rspi_dma_check_then_transfer()
698 return -EAGAIN; in rspi_dma_check_then_transfer()
700 /* rx_buf can be NULL on RSPI on SH in TX-only Mode */ in rspi_dma_check_then_transfer()
701 return rspi_dma_transfer(rspi, &xfer->tx_sg, in rspi_dma_check_then_transfer()
702 xfer->rx_buf ? &xfer->rx_sg : NULL); in rspi_dma_check_then_transfer()
710 xfer->effective_speed_hz = rspi->speed_hz; in rspi_common_transfer()
713 if (ret != -EAGAIN) in rspi_common_transfer()
716 ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len); in rspi_common_transfer()
733 if (xfer->rx_buf) { in rspi_transfer_one()
766 dev_err(&rspi->ctlr->dev, "transmit timeout\n"); in qspi_trigger_transfer_out_in()
774 dev_err(&rspi->ctlr->dev, "receive timeout\n"); in qspi_trigger_transfer_out_in()
780 len -= n; in qspi_trigger_transfer_out_in()
794 if (ret != -EAGAIN) in qspi_transfer_out_in()
797 return qspi_trigger_transfer_out_in(rspi, xfer->tx_buf, in qspi_transfer_out_in()
798 xfer->rx_buf, xfer->len); in qspi_transfer_out_in()
803 const u8 *tx = xfer->tx_buf; in qspi_transfer_out()
804 unsigned int n = xfer->len; in qspi_transfer_out()
808 if (rspi->ctlr->can_dma && __rspi_can_dma(rspi, xfer)) { in qspi_transfer_out()
809 ret = rspi_dma_transfer(rspi, &xfer->tx_sg, NULL); in qspi_transfer_out()
810 if (ret != -EAGAIN) in qspi_transfer_out()
818 dev_err(&rspi->ctlr->dev, "transmit timeout\n"); in qspi_transfer_out()
824 n -= len; in qspi_transfer_out()
835 u8 *rx = xfer->rx_buf; in qspi_transfer_in()
836 unsigned int n = xfer->len; in qspi_transfer_in()
840 if (rspi->ctlr->can_dma && __rspi_can_dma(rspi, xfer)) { in qspi_transfer_in()
841 ret = rspi_dma_transfer(rspi, NULL, &xfer->rx_sg); in qspi_transfer_in()
842 if (ret != -EAGAIN) in qspi_transfer_in()
850 dev_err(&rspi->ctlr->dev, "receive timeout\n"); in qspi_transfer_in()
856 n -= len; in qspi_transfer_in()
867 xfer->effective_speed_hz = rspi->speed_hz; in qspi_transfer_one()
868 if (spi->mode & SPI_LOOP) { in qspi_transfer_one()
870 } else if (xfer->tx_nbits > SPI_NBITS_SINGLE) { in qspi_transfer_one()
871 /* Quad or Dual SPI Write */ in qspi_transfer_one()
873 } else if (xfer->rx_nbits > SPI_NBITS_SINGLE) { in qspi_transfer_one()
874 /* Quad or Dual SPI Read */ in qspi_transfer_one()
884 if (xfer->tx_buf) in qspi_transfer_mode()
885 switch (xfer->tx_nbits) { in qspi_transfer_mode()
893 if (xfer->rx_buf) in qspi_transfer_mode()
894 switch (xfer->rx_nbits) { in qspi_transfer_mode()
913 list_for_each_entry(xfer, &msg->transfers, transfer_list) { in qspi_setup_sequencer()
916 len += xfer->len; in qspi_setup_sequencer()
923 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1)); in qspi_setup_sequencer()
927 dev_err(&msg->spi->dev, in qspi_setup_sequencer()
929 return -EINVAL; in qspi_setup_sequencer()
933 rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i)); in qspi_setup_sequencer()
935 len = xfer->len; in qspi_setup_sequencer()
940 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1)); in qspi_setup_sequencer()
941 rspi_write8(rspi, i - 1, RSPI_SPSCR); in qspi_setup_sequencer()
949 struct rspi_data *rspi = spi_controller_get_devdata(spi->controller); in rspi_setup()
955 pm_runtime_get_sync(&rspi->pdev->dev); in rspi_setup()
956 spin_lock_irq(&rspi->lock); in rspi_setup()
959 if (spi->mode & SPI_CS_HIGH) in rspi_setup()
965 spin_unlock_irq(&rspi->lock); in rspi_setup()
966 pm_runtime_put(&rspi->pdev->dev); in rspi_setup()
974 struct spi_device *spi = msg->spi; in rspi_prepare_message()
988 rspi->speed_hz = spi->max_speed_hz; in rspi_prepare_message()
989 list_for_each_entry(xfer, &msg->transfers, transfer_list) { in rspi_prepare_message()
990 if (xfer->speed_hz < rspi->speed_hz) in rspi_prepare_message()
991 rspi->speed_hz = xfer->speed_hz; in rspi_prepare_message()
994 rspi->spcmd = SPCMD_SSLKP; in rspi_prepare_message()
995 if (spi->mode & SPI_CPOL) in rspi_prepare_message()
996 rspi->spcmd |= SPCMD_CPOL; in rspi_prepare_message()
997 if (spi->mode & SPI_CPHA) in rspi_prepare_message()
998 rspi->spcmd |= SPCMD_CPHA; in rspi_prepare_message()
999 if (spi->mode & SPI_LSB_FIRST) in rspi_prepare_message()
1000 rspi->spcmd |= SPCMD_LSBF; in rspi_prepare_message()
1003 rspi->spcmd |= SPCMD_SSLA(spi_get_csgpiod(spi, 0) ? rspi->ctlr->unused_native_cs in rspi_prepare_message()
1007 rspi->sppcr = 0; in rspi_prepare_message()
1008 if (spi->mode & SPI_LOOP) in rspi_prepare_message()
1009 rspi->sppcr |= SPPCR_SPLP; in rspi_prepare_message()
1011 rspi->ops->set_config_register(rspi, 8); in rspi_prepare_message()
1013 if (msg->spi->mode & in rspi_prepare_message()
1035 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); in rspi_unprepare_message()
1047 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); in rspi_irq_mux()
1056 wake_up(&rspi->wait); in rspi_irq_mux()
1067 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); in rspi_irq_rx()
1070 wake_up(&rspi->wait); in rspi_irq_rx()
1082 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); in rspi_irq_tx()
1085 wake_up(&rspi->wait); in rspi_irq_tx()
1135 if (dev->of_node) { in rspi_request_dma()
1144 ctlr->dma_tx = rspi_request_dma_chan(dev, DMA_MEM_TO_DEV, dma_tx_id, in rspi_request_dma()
1145 res->start); in rspi_request_dma()
1146 if (!ctlr->dma_tx) in rspi_request_dma()
1147 return -ENODEV; in rspi_request_dma()
1149 ctlr->dma_rx = rspi_request_dma_chan(dev, DMA_DEV_TO_MEM, dma_rx_id, in rspi_request_dma()
1150 res->start); in rspi_request_dma()
1151 if (!ctlr->dma_rx) { in rspi_request_dma()
1152 dma_release_channel(ctlr->dma_tx); in rspi_request_dma()
1153 ctlr->dma_tx = NULL; in rspi_request_dma()
1154 return -ENODEV; in rspi_request_dma()
1157 ctlr->can_dma = rspi_can_dma; in rspi_request_dma()
1164 if (ctlr->dma_tx) in rspi_release_dma()
1165 dma_release_channel(ctlr->dma_tx); in rspi_release_dma()
1166 if (ctlr->dma_rx) in rspi_release_dma()
1167 dma_release_channel(ctlr->dma_rx); in rspi_release_dma()
1174 rspi_release_dma(rspi->ctlr); in rspi_remove()
1175 pm_runtime_disable(&pdev->dev); in rspi_remove()
1214 { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops },
1215 /* QSPI on R-Car Gen2 */
1235 error = of_property_read_u32(dev->of_node, "num-cs", &num_cs); in rspi_parse_dt()
1237 dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error); in rspi_parse_dt()
1241 ctlr->num_chipselect = num_cs; in rspi_parse_dt()
1266 return -EINVAL; in rspi_parse_dt()
1277 return -ENOMEM; in rspi_request_irq()
1291 ctlr = spi_alloc_host(&pdev->dev, sizeof(struct rspi_data)); in rspi_probe()
1293 return -ENOMEM; in rspi_probe()
1295 ops = of_device_get_match_data(&pdev->dev); in rspi_probe()
1297 ret = rspi_parse_dt(&pdev->dev, ctlr); in rspi_probe()
1301 ops = (struct spi_ops *)pdev->id_entry->driver_data; in rspi_probe()
1302 ctlr->num_chipselect = 2; /* default */ in rspi_probe()
1307 rspi->ops = ops; in rspi_probe()
1308 rspi->ctlr = ctlr; in rspi_probe()
1310 rspi->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in rspi_probe()
1311 if (IS_ERR(rspi->addr)) { in rspi_probe()
1312 ret = PTR_ERR(rspi->addr); in rspi_probe()
1316 rspi->clk = devm_clk_get(&pdev->dev, NULL); in rspi_probe()
1317 if (IS_ERR(rspi->clk)) { in rspi_probe()
1318 dev_err(&pdev->dev, "cannot get clock\n"); in rspi_probe()
1319 ret = PTR_ERR(rspi->clk); in rspi_probe()
1323 rspi->pdev = pdev; in rspi_probe()
1324 pm_runtime_enable(&pdev->dev); in rspi_probe()
1326 init_waitqueue_head(&rspi->wait); in rspi_probe()
1327 spin_lock_init(&rspi->lock); in rspi_probe()
1329 ctlr->bus_num = pdev->id; in rspi_probe()
1330 ctlr->setup = rspi_setup; in rspi_probe()
1331 ctlr->auto_runtime_pm = true; in rspi_probe()
1332 ctlr->transfer_one = ops->transfer_one; in rspi_probe()
1333 ctlr->prepare_message = rspi_prepare_message; in rspi_probe()
1334 ctlr->unprepare_message = rspi_unprepare_message; in rspi_probe()
1335 ctlr->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST | in rspi_probe()
1336 SPI_LOOP | ops->extra_mode_bits; in rspi_probe()
1337 clksrc = clk_get_rate(rspi->clk); in rspi_probe()
1338 ctlr->min_speed_hz = DIV_ROUND_UP(clksrc, ops->max_div); in rspi_probe()
1339 ctlr->max_speed_hz = DIV_ROUND_UP(clksrc, ops->min_div); in rspi_probe()
1340 ctlr->flags = ops->flags; in rspi_probe()
1341 ctlr->dev.of_node = pdev->dev.of_node; in rspi_probe()
1342 ctlr->use_gpio_descriptors = true; in rspi_probe()
1343 ctlr->max_native_cs = rspi->ops->num_hw_ss; in rspi_probe()
1351 rspi->rx_irq = rspi->tx_irq = ret; in rspi_probe()
1353 rspi->rx_irq = ret; in rspi_probe()
1356 rspi->tx_irq = ret; in rspi_probe()
1359 if (rspi->rx_irq == rspi->tx_irq) { in rspi_probe()
1361 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux, in rspi_probe()
1364 /* Multi-interrupt mode, only SPRI and SPTI are used */ in rspi_probe()
1365 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx, in rspi_probe()
1368 ret = rspi_request_irq(&pdev->dev, rspi->tx_irq, in rspi_probe()
1372 dev_err(&pdev->dev, "request_irq error\n"); in rspi_probe()
1376 ret = rspi_request_dma(&pdev->dev, ctlr, res); in rspi_probe()
1378 dev_warn(&pdev->dev, "DMA not available, using PIO\n"); in rspi_probe()
1380 ret = devm_spi_register_controller(&pdev->dev, ctlr); in rspi_probe()
1382 dev_err(&pdev->dev, "devm_spi_register_controller error.\n"); in rspi_probe()
1386 dev_info(&pdev->dev, "probed\n"); in rspi_probe()
1393 pm_runtime_disable(&pdev->dev); in rspi_probe()
1412 return spi_controller_suspend(rspi->ctlr); in rspi_suspend()
1419 return spi_controller_resume(rspi->ctlr); in rspi_resume()