Lines Matching full:controller
163 static inline bool spi_qup_is_flag_set(struct spi_qup *controller, u32 flag) in spi_qup_is_flag_set() argument
165 u32 opflag = readl_relaxed(controller->base + QUP_OPERATIONAL); in spi_qup_is_flag_set()
179 static inline unsigned int spi_qup_len(struct spi_qup *controller) in spi_qup_len() argument
181 return controller->n_words * controller->w_size; in spi_qup_len()
184 static inline bool spi_qup_is_valid_state(struct spi_qup *controller) in spi_qup_is_valid_state() argument
186 u32 opstate = readl_relaxed(controller->base + QUP_STATE); in spi_qup_is_valid_state()
191 static int spi_qup_vote_bw(struct spi_qup *controller, u32 speed_hz) in spi_qup_vote_bw() argument
196 if (controller->bw_speed_hz == speed_hz) in spi_qup_vote_bw()
200 ret = icc_set_bw(controller->icc_path, 0, needed_peak_bw); in spi_qup_vote_bw()
204 controller->bw_speed_hz = speed_hz; in spi_qup_vote_bw()
208 static int spi_qup_set_state(struct spi_qup *controller, u32 state) in spi_qup_set_state() argument
214 while (!spi_qup_is_valid_state(controller)) { in spi_qup_set_state()
223 dev_dbg(controller->dev, "invalid state for %ld,us %d\n", in spi_qup_set_state()
226 cur_state = readl_relaxed(controller->base + QUP_STATE); in spi_qup_set_state()
233 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE); in spi_qup_set_state()
234 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE); in spi_qup_set_state()
238 writel_relaxed(cur_state, controller->base + QUP_STATE); in spi_qup_set_state()
242 while (!spi_qup_is_valid_state(controller)) { in spi_qup_set_state()
253 static void spi_qup_read_from_fifo(struct spi_qup *controller, u32 num_words) in spi_qup_read_from_fifo() argument
255 u8 *rx_buf = controller->rx_buf; in spi_qup_read_from_fifo()
261 word = readl_relaxed(controller->base + QUP_INPUT_FIFO); in spi_qup_read_from_fifo()
263 num_bytes = min_t(int, spi_qup_len(controller) - in spi_qup_read_from_fifo()
264 controller->rx_bytes, in spi_qup_read_from_fifo()
265 controller->w_size); in spi_qup_read_from_fifo()
268 controller->rx_bytes += num_bytes; in spi_qup_read_from_fifo()
272 for (i = 0; i < num_bytes; i++, controller->rx_bytes++) { in spi_qup_read_from_fifo()
280 shift *= (controller->w_size - i - 1); in spi_qup_read_from_fifo()
281 rx_buf[controller->rx_bytes] = word >> shift; in spi_qup_read_from_fifo()
286 static void spi_qup_read(struct spi_qup *controller, u32 *opflags) in spi_qup_read() argument
289 bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK; in spi_qup_read()
291 remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->rx_bytes, in spi_qup_read()
292 controller->w_size); in spi_qup_read()
293 words_per_block = controller->in_blk_sz >> 2; in spi_qup_read()
298 controller->base + QUP_OPERATIONAL); in spi_qup_read()
307 if (!spi_qup_is_flag_set(controller, in spi_qup_read()
315 spi_qup_read_from_fifo(controller, num_words); in spi_qup_read()
320 if (is_block_mode && !spi_qup_is_flag_set(controller, in spi_qup_read()
334 *opflags = readl_relaxed(controller->base + QUP_OPERATIONAL); in spi_qup_read()
337 controller->base + QUP_OPERATIONAL); in spi_qup_read()
341 static void spi_qup_write_to_fifo(struct spi_qup *controller, u32 num_words) in spi_qup_write_to_fifo() argument
343 const u8 *tx_buf = controller->tx_buf; in spi_qup_write_to_fifo()
350 num_bytes = min_t(int, spi_qup_len(controller) - in spi_qup_write_to_fifo()
351 controller->tx_bytes, in spi_qup_write_to_fifo()
352 controller->w_size); in spi_qup_write_to_fifo()
355 data = tx_buf[controller->tx_bytes + i]; in spi_qup_write_to_fifo()
359 controller->tx_bytes += num_bytes; in spi_qup_write_to_fifo()
361 writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO); in spi_qup_write_to_fifo()
372 static void spi_qup_write(struct spi_qup *controller) in spi_qup_write() argument
374 bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK; in spi_qup_write()
377 remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->tx_bytes, in spi_qup_write()
378 controller->w_size); in spi_qup_write()
379 words_per_block = controller->out_blk_sz >> 2; in spi_qup_write()
384 controller->base + QUP_OPERATIONAL); in spi_qup_write()
394 if (spi_qup_is_flag_set(controller, in spi_qup_write()
401 spi_qup_write_to_fifo(controller, num_words); in spi_qup_write()
406 if (is_block_mode && !spi_qup_is_flag_set(controller, in spi_qup_write()
473 struct spi_controller *host = spi->controller; in spi_qup_do_dma()
547 struct spi_controller *host = spi->controller; in spi_qup_do_pio()
609 static bool spi_qup_data_pending(struct spi_qup *controller) in spi_qup_data_pending() argument
613 remainder_tx = DIV_ROUND_UP(spi_qup_len(controller) - in spi_qup_data_pending()
614 controller->tx_bytes, controller->w_size); in spi_qup_data_pending()
616 remainder_rx = DIV_ROUND_UP(spi_qup_len(controller) - in spi_qup_data_pending()
617 controller->rx_bytes, controller->w_size); in spi_qup_data_pending()
624 struct spi_qup *controller = dev_id; in spi_qup_qup_irq() local
628 qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS); in spi_qup_qup_irq()
629 spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS); in spi_qup_qup_irq()
630 opflags = readl_relaxed(controller->base + QUP_OPERATIONAL); in spi_qup_qup_irq()
632 writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS); in spi_qup_qup_irq()
633 writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS); in spi_qup_qup_irq()
637 dev_warn(controller->dev, "OUTPUT_OVER_RUN\n"); in spi_qup_qup_irq()
639 dev_warn(controller->dev, "INPUT_UNDER_RUN\n"); in spi_qup_qup_irq()
641 dev_warn(controller->dev, "OUTPUT_UNDER_RUN\n"); in spi_qup_qup_irq()
643 dev_warn(controller->dev, "INPUT_OVER_RUN\n"); in spi_qup_qup_irq()
650 dev_warn(controller->dev, "CLK_OVER_RUN\n"); in spi_qup_qup_irq()
652 dev_warn(controller->dev, "CLK_UNDER_RUN\n"); in spi_qup_qup_irq()
657 spin_lock(&controller->lock); in spi_qup_qup_irq()
658 if (!controller->error) in spi_qup_qup_irq()
659 controller->error = error; in spi_qup_qup_irq()
660 spin_unlock(&controller->lock); in spi_qup_qup_irq()
662 if (spi_qup_is_dma_xfer(controller->mode)) { in spi_qup_qup_irq()
663 writel_relaxed(opflags, controller->base + QUP_OPERATIONAL); in spi_qup_qup_irq()
666 spi_qup_read(controller, &opflags); in spi_qup_qup_irq()
669 spi_qup_write(controller); in spi_qup_qup_irq()
671 if (!spi_qup_data_pending(controller)) in spi_qup_qup_irq()
672 complete(&controller->done); in spi_qup_qup_irq()
676 complete(&controller->done); in spi_qup_qup_irq()
679 if (!spi_qup_is_dma_xfer(controller->mode)) { in spi_qup_qup_irq()
680 if (spi_qup_data_pending(controller)) in spi_qup_qup_irq()
683 complete(&controller->done); in spi_qup_qup_irq()
692 struct spi_qup *controller = spi_controller_get_devdata(spi->controller); in spi_qup_io_prep() local
695 if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) { in spi_qup_io_prep()
696 dev_err(controller->dev, "too big size for loopback %d > %d\n", in spi_qup_io_prep()
697 xfer->len, controller->in_fifo_sz); in spi_qup_io_prep()
701 ret = dev_pm_opp_set_rate(controller->dev, xfer->speed_hz); in spi_qup_io_prep()
703 dev_err(controller->dev, "fail to set frequency %d", in spi_qup_io_prep()
708 controller->w_size = DIV_ROUND_UP(xfer->bits_per_word, 8); in spi_qup_io_prep()
709 controller->n_words = xfer->len / controller->w_size; in spi_qup_io_prep()
711 if (controller->n_words <= (controller->in_fifo_sz / sizeof(u32))) in spi_qup_io_prep()
712 controller->mode = QUP_IO_M_MODE_FIFO; in spi_qup_io_prep()
713 else if (spi_xfer_is_dma_mapped(spi->controller, spi, xfer)) in spi_qup_io_prep()
714 controller->mode = QUP_IO_M_MODE_BAM; in spi_qup_io_prep()
716 controller->mode = QUP_IO_M_MODE_BLOCK; in spi_qup_io_prep()
724 struct spi_qup *controller = spi_controller_get_devdata(spi->controller); in spi_qup_io_config() local
728 spin_lock_irqsave(&controller->lock, flags); in spi_qup_io_config()
729 controller->xfer = xfer; in spi_qup_io_config()
730 controller->error = 0; in spi_qup_io_config()
731 controller->rx_bytes = 0; in spi_qup_io_config()
732 controller->tx_bytes = 0; in spi_qup_io_config()
733 spin_unlock_irqrestore(&controller->lock, flags); in spi_qup_io_config()
736 if (spi_qup_set_state(controller, QUP_STATE_RESET)) { in spi_qup_io_config()
737 dev_err(controller->dev, "cannot set RESET state\n"); in spi_qup_io_config()
741 switch (controller->mode) { in spi_qup_io_config()
743 writel_relaxed(controller->n_words, in spi_qup_io_config()
744 controller->base + QUP_MX_READ_CNT); in spi_qup_io_config()
745 writel_relaxed(controller->n_words, in spi_qup_io_config()
746 controller->base + QUP_MX_WRITE_CNT); in spi_qup_io_config()
748 writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT); in spi_qup_io_config()
749 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT); in spi_qup_io_config()
752 writel_relaxed(controller->n_words, in spi_qup_io_config()
753 controller->base + QUP_MX_INPUT_CNT); in spi_qup_io_config()
754 writel_relaxed(controller->n_words, in spi_qup_io_config()
755 controller->base + QUP_MX_OUTPUT_CNT); in spi_qup_io_config()
757 writel_relaxed(0, controller->base + QUP_MX_READ_CNT); in spi_qup_io_config()
758 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT); in spi_qup_io_config()
760 if (!controller->qup_v1) { in spi_qup_io_config()
763 input_cnt = controller->base + QUP_MX_INPUT_CNT; in spi_qup_io_config()
773 writel_relaxed(controller->n_words, input_cnt); in spi_qup_io_config()
775 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT); in spi_qup_io_config()
779 reinit_completion(&controller->done); in spi_qup_io_config()
780 writel_relaxed(controller->n_words, in spi_qup_io_config()
781 controller->base + QUP_MX_INPUT_CNT); in spi_qup_io_config()
782 writel_relaxed(controller->n_words, in spi_qup_io_config()
783 controller->base + QUP_MX_OUTPUT_CNT); in spi_qup_io_config()
785 writel_relaxed(0, controller->base + QUP_MX_READ_CNT); in spi_qup_io_config()
786 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT); in spi_qup_io_config()
789 dev_err(controller->dev, "unknown mode = %d\n", in spi_qup_io_config()
790 controller->mode); in spi_qup_io_config()
794 iomode = readl_relaxed(controller->base + QUP_IO_M_MODES); in spi_qup_io_config()
798 if (!spi_qup_is_dma_xfer(controller->mode)) in spi_qup_io_config()
803 iomode |= (controller->mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT); in spi_qup_io_config()
804 iomode |= (controller->mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT); in spi_qup_io_config()
806 writel_relaxed(iomode, controller->base + QUP_IO_M_MODES); in spi_qup_io_config()
808 control = readl_relaxed(controller->base + SPI_IO_CONTROL); in spi_qup_io_config()
815 writel_relaxed(control, controller->base + SPI_IO_CONTROL); in spi_qup_io_config()
817 config = readl_relaxed(controller->base + SPI_CONFIG); in spi_qup_io_config()
838 writel_relaxed(config, controller->base + SPI_CONFIG); in spi_qup_io_config()
840 config = readl_relaxed(controller->base + QUP_CONFIG); in spi_qup_io_config()
845 if (spi_qup_is_dma_xfer(controller->mode)) { in spi_qup_io_config()
852 writel_relaxed(config, controller->base + QUP_CONFIG); in spi_qup_io_config()
855 if (!controller->qup_v1) { in spi_qup_io_config()
863 if (spi_qup_is_dma_xfer(controller->mode)) in spi_qup_io_config()
866 writel_relaxed(mask, controller->base + QUP_OPERATIONAL_MASK); in spi_qup_io_config()
876 struct spi_qup *controller = spi_controller_get_devdata(host); in spi_qup_transfer_one() local
889 reinit_completion(&controller->done); in spi_qup_transfer_one()
891 spin_lock_irqsave(&controller->lock, flags); in spi_qup_transfer_one()
892 controller->xfer = xfer; in spi_qup_transfer_one()
893 controller->error = 0; in spi_qup_transfer_one()
894 controller->rx_bytes = 0; in spi_qup_transfer_one()
895 controller->tx_bytes = 0; in spi_qup_transfer_one()
896 spin_unlock_irqrestore(&controller->lock, flags); in spi_qup_transfer_one()
898 if (spi_qup_is_dma_xfer(controller->mode)) in spi_qup_transfer_one()
903 spi_qup_set_state(controller, QUP_STATE_RESET); in spi_qup_transfer_one()
904 spin_lock_irqsave(&controller->lock, flags); in spi_qup_transfer_one()
906 ret = controller->error; in spi_qup_transfer_one()
907 spin_unlock_irqrestore(&controller->lock, flags); in spi_qup_transfer_one()
909 if (ret && spi_qup_is_dma_xfer(controller->mode)) in spi_qup_transfer_one()
1006 struct spi_qup *controller; in spi_qup_set_cs() local
1010 controller = spi_controller_get_devdata(spi->controller); in spi_qup_set_cs()
1011 spi_ioc = readl_relaxed(controller->base + SPI_IO_CONTROL); in spi_qup_set_cs()
1019 writel_relaxed(spi_ioc, controller->base + SPI_IO_CONTROL); in spi_qup_set_cs()
1027 struct spi_qup *controller; in spi_qup_probe() local
1101 controller = spi_controller_get_devdata(host); in spi_qup_probe()
1103 controller->dev = dev; in spi_qup_probe()
1104 controller->base = base; in spi_qup_probe()
1105 controller->iclk = iclk; in spi_qup_probe()
1106 controller->cclk = cclk; in spi_qup_probe()
1107 controller->icc_path = icc_path; in spi_qup_probe()
1108 controller->irq = irq; in spi_qup_probe()
1116 controller->qup_v1 = (uintptr_t)of_device_get_match_data(dev); in spi_qup_probe()
1118 if (!controller->qup_v1) in spi_qup_probe()
1121 spin_lock_init(&controller->lock); in spi_qup_probe()
1122 init_completion(&controller->done); in spi_qup_probe()
1141 controller->out_blk_sz = size * 16; in spi_qup_probe()
1143 controller->out_blk_sz = 4; in spi_qup_probe()
1147 controller->in_blk_sz = size * 16; in spi_qup_probe()
1149 controller->in_blk_sz = 4; in spi_qup_probe()
1152 controller->out_fifo_sz = controller->out_blk_sz * (2 << size); in spi_qup_probe()
1155 controller->in_fifo_sz = controller->in_blk_sz * (2 << size); in spi_qup_probe()
1158 controller->in_blk_sz, controller->in_fifo_sz, in spi_qup_probe()
1159 controller->out_blk_sz, controller->out_fifo_sz); in spi_qup_probe()
1163 ret = spi_qup_set_state(controller, QUP_STATE_RESET); in spi_qup_probe()
1172 if (!controller->qup_v1) in spi_qup_probe()
1179 if (controller->qup_v1) in spi_qup_probe()
1188 IRQF_TRIGGER_HIGH, pdev->name, controller); in spi_qup_probe()
1219 struct spi_qup *controller = spi_controller_get_devdata(host); in spi_qup_pm_suspend_runtime() local
1223 config = readl(controller->base + QUP_CONFIG); in spi_qup_pm_suspend_runtime()
1225 writel_relaxed(config, controller->base + QUP_CONFIG); in spi_qup_pm_suspend_runtime()
1227 clk_disable_unprepare(controller->cclk); in spi_qup_pm_suspend_runtime()
1228 spi_qup_vote_bw(controller, 0); in spi_qup_pm_suspend_runtime()
1229 clk_disable_unprepare(controller->iclk); in spi_qup_pm_suspend_runtime()
1237 struct spi_qup *controller = spi_controller_get_devdata(host); in spi_qup_pm_resume_runtime() local
1241 ret = clk_prepare_enable(controller->iclk); in spi_qup_pm_resume_runtime()
1245 ret = clk_prepare_enable(controller->cclk); in spi_qup_pm_resume_runtime()
1247 clk_disable_unprepare(controller->iclk); in spi_qup_pm_resume_runtime()
1252 config = readl_relaxed(controller->base + QUP_CONFIG); in spi_qup_pm_resume_runtime()
1254 writel_relaxed(config, controller->base + QUP_CONFIG); in spi_qup_pm_resume_runtime()
1263 struct spi_qup *controller = spi_controller_get_devdata(host); in spi_qup_suspend() local
1275 ret = spi_qup_set_state(controller, QUP_STATE_RESET); in spi_qup_suspend()
1279 clk_disable_unprepare(controller->cclk); in spi_qup_suspend()
1280 spi_qup_vote_bw(controller, 0); in spi_qup_suspend()
1281 clk_disable_unprepare(controller->iclk); in spi_qup_suspend()
1288 struct spi_qup *controller = spi_controller_get_devdata(host); in spi_qup_resume() local
1291 ret = clk_prepare_enable(controller->iclk); in spi_qup_resume()
1295 ret = clk_prepare_enable(controller->cclk); in spi_qup_resume()
1297 clk_disable_unprepare(controller->iclk); in spi_qup_resume()
1301 ret = spi_qup_set_state(controller, QUP_STATE_RESET); in spi_qup_resume()
1312 clk_disable_unprepare(controller->cclk); in spi_qup_resume()
1313 clk_disable_unprepare(controller->iclk); in spi_qup_resume()
1321 struct spi_qup *controller = spi_controller_get_devdata(host); in spi_qup_remove() local
1327 ret = spi_qup_set_state(controller, QUP_STATE_RESET); in spi_qup_remove()
1329 dev_warn(&pdev->dev, "failed to reset controller (%pe)\n", in spi_qup_remove()
1332 clk_disable_unprepare(controller->cclk); in spi_qup_remove()
1333 clk_disable_unprepare(controller->iclk); in spi_qup_remove()
1371 MODULE_DESCRIPTION("Qualcomm SPI controller with QUP interface");