Lines Matching +full:spi +full:- +full:feedback +full:- +full:delay
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * A driver for the ARM PL022 PrimeCell SSP/SPI bus master.
5 * Copyright (C) 2008-2012 ST-Ericsson AB
11 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
22 #include <linux/spi/spi.h>
23 #include <linux/delay.h>
31 #include <linux/dma-mapping.h>
92 * SSP Control Register 0 - SSP_CR0
110 * SSP Control Register 0 - SSP_CR1
130 * SSP Status Register - SSP_SR
139 * SSP Clock Prescale Register - SSP_CPSR
144 * SSP Interrupt Mask Set/Clear Register - SSP_IMSC
152 * SSP Raw Interrupt Status Register - SSP_RIS
164 * SSP Masked Interrupt Status Register - SSP_MIS
176 * SSP Interrupt Clear Register - SSP_ICR
184 * SSP DMA Control Register - SSP_DMACR
192 * SSP Chip Select Control Register - SSP_CSR
198 * SSP Integration Test control Register - SSP_ITCR
204 * SSP Integration Test Input Register - SSP_ITIP
214 * SSP Integration Test output Register - SSP_ITOP
232 * SSP Test Data Register - SSP_TDR
245 #define STATE_ERROR ((void *) -1)
246 #define STATE_TIMEOUT ((void *) -2)
249 * SSP State - Whether Enabled or Disabled
255 * SSP DMA State - Whether DMA Enabled or Disabled
311 * struct vendor_data - vendor-specific config parameters
333 * struct pl022 - This is the private SSP driver data structure
338 * @clk: outgoing clock "SPICLK" for the SPI bus
339 * @host: SPI framework hookup
340 * @host_info: controller-specific data from machine setup
392 * struct chip_data - To maintain runtime state of SSP for each client chip
393 * @cr0: Value of control register CR0 of SSP - on later ST variants this
420 * internal_cs_control - Control chip select signals via SSP_CSR.
432 tmp = readw(SSP_CSR(pl022->virtbase)); in internal_cs_control()
434 tmp &= ~BIT(pl022->cur_cs); in internal_cs_control()
436 tmp |= BIT(pl022->cur_cs); in internal_cs_control()
437 writew(tmp, SSP_CSR(pl022->virtbase)); in internal_cs_control()
440 static void pl022_cs_control(struct spi_device *spi, bool enable) in pl022_cs_control() argument
442 struct pl022 *pl022 = spi_controller_get_devdata(spi->controller); in pl022_cs_control()
443 if (pl022->vendor->internal_cs_ctrl) in pl022_cs_control()
448 * flush - flush the FIFO to reach a clean state
455 dev_dbg(&pl022->adev->dev, "flush\n"); in flush()
457 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) in flush()
458 readw(SSP_DR(pl022->virtbase)); in flush()
459 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); in flush()
461 pl022->exp_fifo_level = 0; in flush()
467 * restore_state - Load configuration of current chip
472 struct chip_data *chip = pl022->cur_chip; in restore_state()
474 if (pl022->vendor->extended_cr) in restore_state()
475 writel(chip->cr0, SSP_CR0(pl022->virtbase)); in restore_state()
477 writew(chip->cr0, SSP_CR0(pl022->virtbase)); in restore_state()
478 writew(chip->cr1, SSP_CR1(pl022->virtbase)); in restore_state()
479 writew(chip->dmacr, SSP_DMACR(pl022->virtbase)); in restore_state()
480 writew(chip->cpsr, SSP_CPSR(pl022->virtbase)); in restore_state()
481 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); in restore_state()
482 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); in restore_state()
534 * support, and a new clock feedback delay setting.
557 * load_ssp_default_config - Load default configuration for SSP
562 if (pl022->vendor->pl023) { in load_ssp_default_config()
563 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase)); in load_ssp_default_config()
564 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase)); in load_ssp_default_config()
565 } else if (pl022->vendor->extended_cr) { in load_ssp_default_config()
566 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase)); in load_ssp_default_config()
567 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase)); in load_ssp_default_config()
569 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); in load_ssp_default_config()
570 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase)); in load_ssp_default_config()
572 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase)); in load_ssp_default_config()
573 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase)); in load_ssp_default_config()
574 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); in load_ssp_default_config()
575 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); in load_ssp_default_config()
595 dev_dbg(&pl022->adev->dev, in readwriter()
597 __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end); in readwriter()
600 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) in readwriter()
601 && (pl022->rx < pl022->rx_end)) { in readwriter()
602 switch (pl022->read) { in readwriter()
604 readw(SSP_DR(pl022->virtbase)); in readwriter()
607 *(u8 *) (pl022->rx) = in readwriter()
608 readw(SSP_DR(pl022->virtbase)) & 0xFFU; in readwriter()
611 *(u16 *) (pl022->rx) = in readwriter()
612 (u16) readw(SSP_DR(pl022->virtbase)); in readwriter()
615 *(u32 *) (pl022->rx) = in readwriter()
616 readl(SSP_DR(pl022->virtbase)); in readwriter()
619 pl022->rx += (pl022->cur_chip->n_bytes); in readwriter()
620 pl022->exp_fifo_level--; in readwriter()
625 while ((pl022->exp_fifo_level < pl022->vendor->fifodepth) in readwriter()
626 && (pl022->tx < pl022->tx_end)) { in readwriter()
627 switch (pl022->write) { in readwriter()
629 writew(0x0, SSP_DR(pl022->virtbase)); in readwriter()
632 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase)); in readwriter()
635 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase)); in readwriter()
638 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase)); in readwriter()
641 pl022->tx += (pl022->cur_chip->n_bytes); in readwriter()
642 pl022->exp_fifo_level++; in readwriter()
649 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) in readwriter()
650 && (pl022->rx < pl022->rx_end)) { in readwriter()
651 switch (pl022->read) { in readwriter()
653 readw(SSP_DR(pl022->virtbase)); in readwriter()
656 *(u8 *) (pl022->rx) = in readwriter()
657 readw(SSP_DR(pl022->virtbase)) & 0xFFU; in readwriter()
660 *(u16 *) (pl022->rx) = in readwriter()
661 (u16) readw(SSP_DR(pl022->virtbase)); in readwriter()
664 *(u32 *) (pl022->rx) = in readwriter()
665 readl(SSP_DR(pl022->virtbase)); in readwriter()
668 pl022->rx += (pl022->cur_chip->n_bytes); in readwriter()
669 pl022->exp_fifo_level--; in readwriter()
686 dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl, in unmap_free_dma_scatter()
687 pl022->sgt_tx.nents, DMA_TO_DEVICE); in unmap_free_dma_scatter()
688 dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl, in unmap_free_dma_scatter()
689 pl022->sgt_rx.nents, DMA_FROM_DEVICE); in unmap_free_dma_scatter()
690 sg_free_table(&pl022->sgt_rx); in unmap_free_dma_scatter()
691 sg_free_table(&pl022->sgt_tx); in unmap_free_dma_scatter()
698 BUG_ON(!pl022->sgt_rx.sgl); in dma_callback()
711 dma_sync_sg_for_cpu(&pl022->adev->dev, in dma_callback()
712 pl022->sgt_rx.sgl, in dma_callback()
713 pl022->sgt_rx.nents, in dma_callback()
716 for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) { in dma_callback()
717 dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i); in dma_callback()
718 print_hex_dump(KERN_ERR, "SPI RX: ", in dma_callback()
726 for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) { in dma_callback()
727 dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i); in dma_callback()
728 print_hex_dump(KERN_ERR, "SPI TX: ", in dma_callback()
741 spi_finalize_current_transfer(pl022->host); in dma_callback()
756 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { in setup_dma_scatter()
763 if (bytesleft < (PAGE_SIZE - offset_in_page(bufp))) in setup_dma_scatter()
766 mapbytes = PAGE_SIZE - offset_in_page(bufp); in setup_dma_scatter()
770 bytesleft -= mapbytes; in setup_dma_scatter()
771 dev_dbg(&pl022->adev->dev, in setup_dma_scatter()
777 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { in setup_dma_scatter()
782 sg_set_page(sg, virt_to_page(pl022->dummypage), in setup_dma_scatter()
784 bytesleft -= mapbytes; in setup_dma_scatter()
785 dev_dbg(&pl022->adev->dev, in setup_dma_scatter()
795 * configure_dma - configures the channels for the next transfer
801 .src_addr = SSP_DR(pl022->phybase), in configure_dma()
806 .dst_addr = SSP_DR(pl022->phybase), in configure_dma()
813 struct dma_chan *rxchan = pl022->dma_rx_channel; in configure_dma()
814 struct dma_chan *txchan = pl022->dma_tx_channel; in configure_dma()
820 return -ENODEV; in configure_dma()
824 * Notice that the DMA engine uses one-to-one mapping. Since we can in configure_dma()
828 switch (pl022->rx_lev_trig) { in configure_dma()
845 rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1; in configure_dma()
849 switch (pl022->tx_lev_trig) { in configure_dma()
866 tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1; in configure_dma()
870 switch (pl022->read) { in configure_dma()
886 switch (pl022->write) { in configure_dma()
902 /* SPI pecularity: we need to read and write the same width */ in configure_dma()
913 pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE); in configure_dma()
914 dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages); in configure_dma()
916 ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC); in configure_dma()
920 ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC); in configure_dma()
925 setup_dma_scatter(pl022, pl022->rx, in configure_dma()
926 pl022->cur_transfer->len, &pl022->sgt_rx); in configure_dma()
927 setup_dma_scatter(pl022, pl022->tx, in configure_dma()
928 pl022->cur_transfer->len, &pl022->sgt_tx); in configure_dma()
931 rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl, in configure_dma()
932 pl022->sgt_rx.nents, DMA_FROM_DEVICE); in configure_dma()
936 tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl, in configure_dma()
937 pl022->sgt_tx.nents, DMA_TO_DEVICE); in configure_dma()
943 pl022->sgt_rx.sgl, in configure_dma()
951 pl022->sgt_tx.sgl, in configure_dma()
959 rxdesc->callback = dma_callback; in configure_dma()
960 rxdesc->callback_param = pl022; in configure_dma()
967 pl022->dma_running = true; in configure_dma()
975 dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl, in configure_dma()
976 pl022->sgt_tx.nents, DMA_TO_DEVICE); in configure_dma()
978 dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl, in configure_dma()
979 pl022->sgt_rx.nents, DMA_FROM_DEVICE); in configure_dma()
981 sg_free_table(&pl022->sgt_tx); in configure_dma()
983 sg_free_table(&pl022->sgt_rx); in configure_dma()
985 return -ENOMEM; in configure_dma()
999 pl022->dma_rx_channel = dma_request_channel(mask, in pl022_dma_probe()
1000 pl022->host_info->dma_filter, in pl022_dma_probe()
1001 pl022->host_info->dma_rx_param); in pl022_dma_probe()
1002 if (!pl022->dma_rx_channel) { in pl022_dma_probe()
1003 dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n"); in pl022_dma_probe()
1007 pl022->dma_tx_channel = dma_request_channel(mask, in pl022_dma_probe()
1008 pl022->host_info->dma_filter, in pl022_dma_probe()
1009 pl022->host_info->dma_tx_param); in pl022_dma_probe()
1010 if (!pl022->dma_tx_channel) { in pl022_dma_probe()
1011 dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n"); in pl022_dma_probe()
1015 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); in pl022_dma_probe()
1016 if (!pl022->dummypage) in pl022_dma_probe()
1019 dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n", in pl022_dma_probe()
1020 dma_chan_name(pl022->dma_rx_channel), in pl022_dma_probe()
1021 dma_chan_name(pl022->dma_tx_channel)); in pl022_dma_probe()
1026 dma_release_channel(pl022->dma_tx_channel); in pl022_dma_probe()
1028 dma_release_channel(pl022->dma_rx_channel); in pl022_dma_probe()
1029 pl022->dma_rx_channel = NULL; in pl022_dma_probe()
1031 dev_err(&pl022->adev->dev, in pl022_dma_probe()
1033 return -ENODEV; in pl022_dma_probe()
1038 struct device *dev = &pl022->adev->dev; in pl022_dma_autoprobe()
1049 pl022->dma_rx_channel = chan; in pl022_dma_autoprobe()
1057 pl022->dma_tx_channel = chan; in pl022_dma_autoprobe()
1059 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); in pl022_dma_autoprobe()
1060 if (!pl022->dummypage) { in pl022_dma_autoprobe()
1061 err = -ENOMEM; in pl022_dma_autoprobe()
1068 dma_release_channel(pl022->dma_tx_channel); in pl022_dma_autoprobe()
1069 pl022->dma_tx_channel = NULL; in pl022_dma_autoprobe()
1071 dma_release_channel(pl022->dma_rx_channel); in pl022_dma_autoprobe()
1072 pl022->dma_rx_channel = NULL; in pl022_dma_autoprobe()
1079 if (!pl022->dma_running) in terminate_dma()
1082 struct dma_chan *rxchan = pl022->dma_rx_channel; in terminate_dma()
1083 struct dma_chan *txchan = pl022->dma_tx_channel; in terminate_dma()
1088 pl022->dma_running = false; in terminate_dma()
1094 if (pl022->dma_tx_channel) in pl022_dma_remove()
1095 dma_release_channel(pl022->dma_tx_channel); in pl022_dma_remove()
1096 if (pl022->dma_rx_channel) in pl022_dma_remove()
1097 dma_release_channel(pl022->dma_rx_channel); in pl022_dma_remove()
1098 kfree(pl022->dummypage); in pl022_dma_remove()
1104 return -ENODEV; in configure_dma()
1127 * pl022_interrupt_handler - Interrupt handler for SSP controller
1144 irq_status = readw(SSP_MIS(pl022->virtbase)); in pl022_interrupt_handler()
1156 * Overrun interrupt - bail out since our Data has been in pl022_interrupt_handler()
1159 dev_err(&pl022->adev->dev, "FIFO overrun\n"); in pl022_interrupt_handler()
1160 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF) in pl022_interrupt_handler()
1161 dev_err(&pl022->adev->dev, in pl022_interrupt_handler()
1170 SSP_IMSC(pl022->virtbase)); in pl022_interrupt_handler()
1171 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); in pl022_interrupt_handler()
1172 writew((readw(SSP_CR1(pl022->virtbase)) & in pl022_interrupt_handler()
1173 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); in pl022_interrupt_handler()
1174 pl022->cur_transfer->error |= SPI_TRANS_FAIL_IO; in pl022_interrupt_handler()
1175 spi_finalize_current_transfer(pl022->host); in pl022_interrupt_handler()
1181 if (pl022->tx == pl022->tx_end) { in pl022_interrupt_handler()
1183 writew((readw(SSP_IMSC(pl022->virtbase)) & in pl022_interrupt_handler()
1185 SSP_IMSC(pl022->virtbase)); in pl022_interrupt_handler()
1193 if (pl022->rx >= pl022->rx_end) { in pl022_interrupt_handler()
1195 SSP_IMSC(pl022->virtbase)); in pl022_interrupt_handler()
1196 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); in pl022_interrupt_handler()
1197 if (unlikely(pl022->rx > pl022->rx_end)) { in pl022_interrupt_handler()
1198 dev_warn(&pl022->adev->dev, "read %u surplus " in pl022_interrupt_handler()
1201 (u32) (pl022->rx - pl022->rx_end)); in pl022_interrupt_handler()
1203 spi_finalize_current_transfer(pl022->host); in pl022_interrupt_handler()
1212 * send out on the SPI bus.
1220 residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes; in set_up_next_transfer()
1222 dev_err(&pl022->adev->dev, in set_up_next_transfer()
1225 pl022->cur_transfer->len, in set_up_next_transfer()
1226 pl022->cur_chip->n_bytes); in set_up_next_transfer()
1227 dev_err(&pl022->adev->dev, "skipping this message\n"); in set_up_next_transfer()
1228 return -EIO; in set_up_next_transfer()
1230 pl022->tx = (void *)transfer->tx_buf; in set_up_next_transfer()
1231 pl022->tx_end = pl022->tx + pl022->cur_transfer->len; in set_up_next_transfer()
1232 pl022->rx = (void *)transfer->rx_buf; in set_up_next_transfer()
1233 pl022->rx_end = pl022->rx + pl022->cur_transfer->len; in set_up_next_transfer()
1234 pl022->write = in set_up_next_transfer()
1235 pl022->tx ? pl022->cur_chip->write : WRITING_NULL; in set_up_next_transfer()
1236 pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL; in set_up_next_transfer()
1245 * Default is to enable all interrupts except RX - in do_interrupt_dma_transfer()
1250 ret = set_up_next_transfer(pl022, pl022->cur_transfer); in do_interrupt_dma_transfer()
1255 if (pl022->cur_chip->enable_dma) { in do_interrupt_dma_transfer()
1258 dev_dbg(&pl022->adev->dev, in do_interrupt_dma_transfer()
1267 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), in do_interrupt_dma_transfer()
1268 SSP_CR1(pl022->virtbase)); in do_interrupt_dma_transfer()
1269 writew(irqflags, SSP_IMSC(pl022->virtbase)); in do_interrupt_dma_transfer()
1278 if (pl022->vendor->extended_cr) in print_current_status()
1279 read_cr0 = readl(SSP_CR0(pl022->virtbase)); in print_current_status()
1281 read_cr0 = readw(SSP_CR0(pl022->virtbase)); in print_current_status()
1282 read_cr1 = readw(SSP_CR1(pl022->virtbase)); in print_current_status()
1283 read_dmacr = readw(SSP_DMACR(pl022->virtbase)); in print_current_status()
1284 read_sr = readw(SSP_SR(pl022->virtbase)); in print_current_status()
1286 dev_warn(&pl022->adev->dev, "spi-pl022 CR0: %x\n", read_cr0); in print_current_status()
1287 dev_warn(&pl022->adev->dev, "spi-pl022 CR1: %x\n", read_cr1); in print_current_status()
1288 dev_warn(&pl022->adev->dev, "spi-pl022 DMACR: %x\n", read_dmacr); in print_current_status()
1289 dev_warn(&pl022->adev->dev, "spi-pl022 SR: %x\n", read_sr); in print_current_status()
1290 dev_warn(&pl022->adev->dev, in print_current_status()
1291 "spi-pl022 exp_fifo_level/fifodepth: %u/%d\n", in print_current_status()
1292 pl022->exp_fifo_level, in print_current_status()
1293 pl022->vendor->fifodepth); in print_current_status()
1303 ret = set_up_next_transfer(pl022, pl022->cur_transfer); in do_polling_transfer()
1308 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), in do_polling_transfer()
1309 SSP_CR1(pl022->virtbase)); in do_polling_transfer()
1311 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n"); in do_polling_transfer()
1314 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) { in do_polling_transfer()
1318 dev_warn(&pl022->adev->dev, in do_polling_transfer()
1321 return -ETIMEDOUT; in do_polling_transfer()
1329 static int pl022_transfer_one(struct spi_controller *host, struct spi_device *spi, in pl022_transfer_one() argument
1334 pl022->cur_transfer = transfer; in pl022_transfer_one()
1336 /* Setup the SPI using the per chip configuration */ in pl022_transfer_one()
1337 pl022->cur_chip = spi_get_ctldata(spi); in pl022_transfer_one()
1338 pl022->cur_cs = spi_get_chipselect(spi, 0); in pl022_transfer_one()
1343 if (pl022->cur_chip->xfer_type == POLLING_TRANSFER) in pl022_transfer_one()
1354 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); in pl022_handle_err()
1355 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); in pl022_handle_err()
1362 /* nothing more to do - disable spi/ssp and power off */ in pl022_unprepare_transfer_hardware()
1363 writew((readw(SSP_CR1(pl022->virtbase)) & in pl022_unprepare_transfer_hardware()
1364 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); in pl022_unprepare_transfer_hardware()
1372 if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI) in verify_controller_parameters()
1373 || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) { in verify_controller_parameters()
1374 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1376 return -EINVAL; in verify_controller_parameters()
1378 if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) && in verify_controller_parameters()
1379 (!pl022->vendor->unidir)) { in verify_controller_parameters()
1380 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1383 return -EINVAL; in verify_controller_parameters()
1385 if ((chip_info->hierarchy != SSP_MASTER) in verify_controller_parameters()
1386 && (chip_info->hierarchy != SSP_SLAVE)) { in verify_controller_parameters()
1387 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1389 return -EINVAL; in verify_controller_parameters()
1391 if ((chip_info->com_mode != INTERRUPT_TRANSFER) in verify_controller_parameters()
1392 && (chip_info->com_mode != DMA_TRANSFER) in verify_controller_parameters()
1393 && (chip_info->com_mode != POLLING_TRANSFER)) { in verify_controller_parameters()
1394 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1396 return -EINVAL; in verify_controller_parameters()
1398 switch (chip_info->rx_lev_trig) { in verify_controller_parameters()
1405 if (pl022->vendor->fifodepth < 16) { in verify_controller_parameters()
1406 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1408 return -EINVAL; in verify_controller_parameters()
1412 if (pl022->vendor->fifodepth < 32) { in verify_controller_parameters()
1413 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1415 return -EINVAL; in verify_controller_parameters()
1419 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1421 return -EINVAL; in verify_controller_parameters()
1423 switch (chip_info->tx_lev_trig) { in verify_controller_parameters()
1430 if (pl022->vendor->fifodepth < 16) { in verify_controller_parameters()
1431 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1433 return -EINVAL; in verify_controller_parameters()
1437 if (pl022->vendor->fifodepth < 32) { in verify_controller_parameters()
1438 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1440 return -EINVAL; in verify_controller_parameters()
1444 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1446 return -EINVAL; in verify_controller_parameters()
1448 if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) { in verify_controller_parameters()
1449 if ((chip_info->ctrl_len < SSP_BITS_4) in verify_controller_parameters()
1450 || (chip_info->ctrl_len > SSP_BITS_32)) { in verify_controller_parameters()
1451 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1453 return -EINVAL; in verify_controller_parameters()
1455 if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO) in verify_controller_parameters()
1456 && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) { in verify_controller_parameters()
1457 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1459 return -EINVAL; in verify_controller_parameters()
1462 if (pl022->vendor->extended_cr) { in verify_controller_parameters()
1463 if ((chip_info->duplex != in verify_controller_parameters()
1465 && (chip_info->duplex != in verify_controller_parameters()
1467 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1469 return -EINVAL; in verify_controller_parameters()
1472 if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) { in verify_controller_parameters()
1473 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1477 return -EINVAL; in verify_controller_parameters()
1497 rate = clk_get_rate(pl022->clk); in calculate_effective_freq()
1504 dev_warn(&pl022->adev->dev, in calculate_effective_freq()
1509 dev_err(&pl022->adev->dev, in calculate_effective_freq()
1512 return -EINVAL; in calculate_effective_freq()
1554 clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF); in calculate_effective_freq()
1555 clk_freq->scr = (u8) (best_scr & 0xFF); in calculate_effective_freq()
1556 dev_dbg(&pl022->adev->dev, in calculate_effective_freq()
1559 dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n", in calculate_effective_freq()
1560 clk_freq->cpsdvsr, clk_freq->scr); in calculate_effective_freq()
1582 * pl022_setup - setup function registered to SPI host framework
1583 * @spi: spi device which is requesting setup
1585 * This function is registered to the SPI framework for this SPI host
1593 static int pl022_setup(struct spi_device *spi) in pl022_setup() argument
1600 struct pl022 *pl022 = spi_controller_get_devdata(spi->controller); in pl022_setup()
1601 unsigned int bits = spi->bits_per_word; in pl022_setup()
1603 struct device_node *np = spi->dev.of_node; in pl022_setup()
1605 if (!spi->max_speed_hz) in pl022_setup()
1606 return -EINVAL; in pl022_setup()
1609 chip = spi_get_ctldata(spi); in pl022_setup()
1614 return -ENOMEM; in pl022_setup()
1615 dev_dbg(&spi->dev, in pl022_setup()
1620 chip_info = spi->controller_data; in pl022_setup()
1629 of_property_read_u32(np, "pl022,com-mode", in pl022_setup()
1631 of_property_read_u32(np, "pl022,rx-level-trig", in pl022_setup()
1633 of_property_read_u32(np, "pl022,tx-level-trig", in pl022_setup()
1635 of_property_read_u32(np, "pl022,ctrl-len", in pl022_setup()
1637 of_property_read_u32(np, "pl022,wait-state", in pl022_setup()
1646 dev_dbg(&spi->dev, in pl022_setup()
1650 dev_dbg(&spi->dev, in pl022_setup()
1657 if ((0 == chip_info->clk_freq.cpsdvsr) in pl022_setup()
1658 && (0 == chip_info->clk_freq.scr)) { in pl022_setup()
1660 spi->max_speed_hz, in pl022_setup()
1665 memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq)); in pl022_setup()
1668 clk_freq.cpsdvsr - 1; in pl022_setup()
1672 status = -EINVAL; in pl022_setup()
1673 dev_err(&spi->dev, in pl022_setup()
1680 dev_err(&spi->dev, "controller data is incorrect"); in pl022_setup()
1684 pl022->rx_lev_trig = chip_info->rx_lev_trig; in pl022_setup()
1685 pl022->tx_lev_trig = chip_info->tx_lev_trig; in pl022_setup()
1688 chip->xfer_type = chip_info->com_mode; in pl022_setup()
1691 if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) { in pl022_setup()
1692 status = -ENOTSUPP; in pl022_setup()
1693 dev_err(&spi->dev, "illegal data size for this controller!\n"); in pl022_setup()
1694 dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n", in pl022_setup()
1695 pl022->vendor->max_bpw); in pl022_setup()
1698 dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n"); in pl022_setup()
1699 chip->n_bytes = 1; in pl022_setup()
1700 chip->read = READING_U8; in pl022_setup()
1701 chip->write = WRITING_U8; in pl022_setup()
1703 dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n"); in pl022_setup()
1704 chip->n_bytes = 2; in pl022_setup()
1705 chip->read = READING_U16; in pl022_setup()
1706 chip->write = WRITING_U16; in pl022_setup()
1708 dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); in pl022_setup()
1709 chip->n_bytes = 4; in pl022_setup()
1710 chip->read = READING_U32; in pl022_setup()
1711 chip->write = WRITING_U32; in pl022_setup()
1715 chip->cr0 = 0; in pl022_setup()
1716 chip->cr1 = 0; in pl022_setup()
1717 chip->dmacr = 0; in pl022_setup()
1718 chip->cpsr = 0; in pl022_setup()
1719 if ((chip_info->com_mode == DMA_TRANSFER) in pl022_setup()
1720 && ((pl022->host_info)->enable_dma)) { in pl022_setup()
1721 chip->enable_dma = true; in pl022_setup()
1722 dev_dbg(&spi->dev, "DMA mode set in controller state\n"); in pl022_setup()
1723 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, in pl022_setup()
1725 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, in pl022_setup()
1728 chip->enable_dma = false; in pl022_setup()
1729 dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n"); in pl022_setup()
1730 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, in pl022_setup()
1732 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, in pl022_setup()
1736 chip->cpsr = clk_freq.cpsdvsr; in pl022_setup()
1739 if (pl022->vendor->extended_cr) { in pl022_setup()
1742 if (pl022->vendor->pl023) { in pl022_setup()
1744 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay, in pl022_setup()
1748 SSP_WRITE_BITS(chip->cr0, chip_info->duplex, in pl022_setup()
1750 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len, in pl022_setup()
1752 SSP_WRITE_BITS(chip->cr0, chip_info->iface, in pl022_setup()
1754 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, in pl022_setup()
1757 SSP_WRITE_BITS(chip->cr0, bits - 1, in pl022_setup()
1760 if (spi->mode & SPI_LSB_FIRST) { in pl022_setup()
1767 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4); in pl022_setup()
1768 SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5); in pl022_setup()
1769 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, in pl022_setup()
1771 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, in pl022_setup()
1774 SSP_WRITE_BITS(chip->cr0, bits - 1, in pl022_setup()
1776 SSP_WRITE_BITS(chip->cr0, chip_info->iface, in pl022_setup()
1781 if (spi->mode & SPI_CPOL) in pl022_setup()
1785 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6); in pl022_setup()
1787 if (spi->mode & SPI_CPHA) in pl022_setup()
1791 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7); in pl022_setup()
1793 SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8); in pl022_setup()
1795 if (pl022->vendor->loopback) { in pl022_setup()
1796 if (spi->mode & SPI_LOOP) in pl022_setup()
1800 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0); in pl022_setup()
1802 SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1); in pl022_setup()
1803 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2); in pl022_setup()
1804 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, in pl022_setup()
1808 spi_set_ctldata(spi, chip); in pl022_setup()
1811 spi_set_ctldata(spi, NULL); in pl022_setup()
1817 * pl022_cleanup - cleanup function registered to SPI host framework
1818 * @spi: spi device which is requesting cleanup
1820 * This function is registered to the SPI framework for this SPI host
1823 static void pl022_cleanup(struct spi_device *spi) in pl022_cleanup() argument
1825 struct chip_data *chip = spi_get_ctldata(spi); in pl022_cleanup()
1827 spi_set_ctldata(spi, NULL); in pl022_cleanup()
1834 struct device_node *np = dev->of_node; in pl022_platform_data_dt_get()
1846 pd->bus_id = -1; in pl022_platform_data_dt_get()
1847 of_property_read_u32(np, "pl022,autosuspend-delay", in pl022_platform_data_dt_get()
1848 &pd->autosuspend_delay); in pl022_platform_data_dt_get()
1849 pd->rt = of_property_read_bool(np, "pl022,rt"); in pl022_platform_data_dt_get()
1856 struct device *dev = &adev->dev; in pl022_probe()
1858 dev_get_platdata(&adev->dev); in pl022_probe()
1863 dev_info(&adev->dev, in pl022_probe()
1864 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid); in pl022_probe()
1870 return -ENODEV; in pl022_probe()
1876 dev_err(&adev->dev, "probe - cannot alloc SPI host\n"); in pl022_probe()
1877 return -ENOMEM; in pl022_probe()
1881 pl022->host = host; in pl022_probe()
1882 pl022->host_info = platform_info; in pl022_probe()
1883 pl022->adev = adev; in pl022_probe()
1884 pl022->vendor = id->data; in pl022_probe()
1890 host->bus_num = platform_info->bus_id; in pl022_probe()
1891 host->cleanup = pl022_cleanup; in pl022_probe()
1892 host->setup = pl022_setup; in pl022_probe()
1893 host->auto_runtime_pm = true; in pl022_probe()
1894 host->transfer_one = pl022_transfer_one; in pl022_probe()
1895 host->set_cs = pl022_cs_control; in pl022_probe()
1896 host->handle_err = pl022_handle_err; in pl022_probe()
1897 host->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware; in pl022_probe()
1898 host->rt = platform_info->rt; in pl022_probe()
1899 host->dev.of_node = dev->of_node; in pl022_probe()
1900 host->use_gpio_descriptors = true; in pl022_probe()
1903 * Supports mode 0-3, loopback, and active low CS. Transfers are in pl022_probe()
1906 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; in pl022_probe()
1907 if (pl022->vendor->extended_cr) in pl022_probe()
1908 host->mode_bits |= SPI_LSB_FIRST; in pl022_probe()
1910 dev_dbg(&adev->dev, "BUSNO: %d\n", host->bus_num); in pl022_probe()
1916 pl022->phybase = adev->res.start; in pl022_probe()
1917 pl022->virtbase = devm_ioremap(dev, adev->res.start, in pl022_probe()
1918 resource_size(&adev->res)); in pl022_probe()
1919 if (pl022->virtbase == NULL) { in pl022_probe()
1920 status = -ENOMEM; in pl022_probe()
1923 dev_info(&adev->dev, "mapped registers from %pa to %p\n", in pl022_probe()
1924 &adev->res.start, pl022->virtbase); in pl022_probe()
1926 pl022->clk = devm_clk_get_enabled(&adev->dev, NULL); in pl022_probe()
1927 if (IS_ERR(pl022->clk)) { in pl022_probe()
1928 status = PTR_ERR(pl022->clk); in pl022_probe()
1929 dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n"); in pl022_probe()
1934 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)), in pl022_probe()
1935 SSP_CR1(pl022->virtbase)); in pl022_probe()
1938 status = devm_request_irq(dev, adev->irq[0], pl022_interrupt_handler, in pl022_probe()
1941 dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status); in pl022_probe()
1947 if (status == -EPROBE_DEFER) { in pl022_probe()
1954 platform_info->enable_dma = 1; in pl022_probe()
1955 else if (platform_info->enable_dma) { in pl022_probe()
1958 platform_info->enable_dma = 0; in pl022_probe()
1961 /* Register with the SPI framework */ in pl022_probe()
1963 status = devm_spi_register_controller(&adev->dev, host); in pl022_probe()
1965 dev_err_probe(&adev->dev, status, in pl022_probe()
1966 "problem registering spi host\n"); in pl022_probe()
1972 if (platform_info->autosuspend_delay > 0) { in pl022_probe()
1973 dev_info(&adev->dev, in pl022_probe()
1974 "will use autosuspend for runtime pm, delay %dms\n", in pl022_probe()
1975 platform_info->autosuspend_delay); in pl022_probe()
1977 platform_info->autosuspend_delay); in pl022_probe()
1985 if (platform_info->enable_dma) in pl022_probe()
2008 pm_runtime_get_noresume(&adev->dev); in pl022_remove()
2011 if (pl022->host_info->enable_dma) in pl022_remove()
2023 ret = spi_controller_suspend(pl022->host); in pl022_suspend()
2029 spi_controller_resume(pl022->host); in pl022_suspend()
2049 ret = spi_controller_resume(pl022->host); in pl022_resume()
2062 clk_disable_unprepare(pl022->clk); in pl022_runtime_suspend()
2073 clk_prepare_enable(pl022->clk); in pl022_runtime_resume()
2145 * ST-Ericsson derivative "PL023" (this is not
2147 * stripped to SPI mode only, it has 32bit wide
2171 .name = "ssp-pl022",