Lines Matching full:scr
1484 static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr) in spi_rate() argument
1486 return rate / (cpsdvsr * (1 + scr)); in spi_rate()
1493 u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN; in calculate_effective_freq() local
1498 /* cpsdvscr = 2 & scr 0 */ in calculate_effective_freq()
1500 /* cpsdvsr = 254 & scr = 255 */ in calculate_effective_freq()
1517 * freq) for all values of scr & cpsdvsr. in calculate_effective_freq()
1520 while (scr <= SCR_MAX) { in calculate_effective_freq()
1521 tmp = spi_rate(rate, cpsdvsr, scr); in calculate_effective_freq()
1525 scr++; in calculate_effective_freq()
1536 best_scr = scr; in calculate_effective_freq()
1542 * increased scr will give lower rates, which are not in calculate_effective_freq()
1548 scr = SCR_MIN; in calculate_effective_freq()
1551 WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n", in calculate_effective_freq()
1555 clk_freq->scr = (u8) (best_scr & 0xFF); in calculate_effective_freq()
1559 dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n", in calculate_effective_freq()
1560 clk_freq->cpsdvsr, clk_freq->scr); in calculate_effective_freq()
1598 struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0}; in pl022_setup()
1658 && (0 == chip_info->clk_freq.scr)) { in pl022_setup()
1793 SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8); in pl022_setup()