Lines Matching +full:gpio +full:- +full:ctrl2
1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/dma-mapping.h>
14 #include <linux/gpio/consumer.h>
39 u32 ctrl2; member
88 #define CTRL2_TX_UR_EN BIT(10) /* Enable int on Tx under-run */
89 #define CTRL2_RX_OV_EN BIT(11) /* Enable int on Rx over-run */
105 u32 speed_hz; /* spi-clk rate */
125 writel(CTRL_ON | CTRL_SIDL, &pic32s->regs->ctrl_set); in pic32_spi_enable()
130 writel(CTRL_ON | CTRL_SIDL, &pic32s->regs->ctrl_clr); in pic32_spi_disable()
140 /* div = (clk_in / 2 * spi_ck) - 1 */ in pic32_spi_set_clk_rate()
141 div = DIV_ROUND_CLOSEST(clk_get_rate(pic32s->clk), 2 * spi_ck) - 1; in pic32_spi_set_clk_rate()
143 writel(div & BAUD_MASK, &pic32s->regs->baud); in pic32_spi_set_clk_rate()
148 u32 sr = readl(&pic32s->regs->status); in pic32_rx_fifo_level()
155 u32 sr = readl(&pic32s->regs->status); in pic32_tx_fifo_level()
165 tx_left = (pic32s->tx_end - pic32s->tx) / n_bytes; in pic32_tx_max()
166 tx_room = pic32s->fifo_n_elm - pic32_tx_fifo_level(pic32s); in pic32_tx_max()
170 * though to use (pic32s->fifo_n_byte - rxfl - txfl) as in pic32_tx_max()
176 rxtx_gap = ((pic32s->rx_end - pic32s->rx) - in pic32_tx_max()
177 (pic32s->tx_end - pic32s->tx)) / n_bytes; in pic32_tx_max()
178 return min3(tx_left, tx_room, (u32)(pic32s->fifo_n_elm - rxtx_gap)); in pic32_tx_max()
184 u32 rx_left = (pic32s->rx_end - pic32s->rx) / n_bytes; in pic32_rx_max()
194 for (; mx; mx--) { \
195 v = read##__bwl(&pic32s->regs->buf); \
196 if (pic32s->rx_end - pic32s->len) \
197 *(__type *)(pic32s->rx) = v; \
198 pic32s->rx += sizeof(__type); \
206 for (; mx ; mx--) { \
208 if (pic32s->tx_end - pic32s->len) \
209 v = *(__type *)(pic32s->tx); \
210 write##__bwl(v, &pic32s->regs->buf); \
211 pic32s->tx += sizeof(__type); \
222 disable_irq_nosync(pic32s->fault_irq); in pic32_err_stop()
223 disable_irq_nosync(pic32s->rx_irq); in pic32_err_stop()
224 disable_irq_nosync(pic32s->tx_irq); in pic32_err_stop()
227 dev_err(&pic32s->host->dev, "%s\n", msg); in pic32_err_stop()
228 if (pic32s->host->cur_msg) in pic32_err_stop()
229 pic32s->host->cur_msg->status = -EIO; in pic32_err_stop()
230 complete(&pic32s->xfer_done); in pic32_err_stop()
238 status = readl(&pic32s->regs->status); in pic32_spi_fault_irq()
242 writel(STAT_RX_OV, &pic32s->regs->status_clr); in pic32_spi_fault_irq()
243 writel(STAT_TX_UR, &pic32s->regs->status_clr); in pic32_spi_fault_irq()
244 pic32_err_stop(pic32s, "err_irq: fifo ov/ur-run\n"); in pic32_spi_fault_irq()
253 if (!pic32s->host->cur_msg) { in pic32_spi_fault_irq()
265 pic32s->rx_fifo(pic32s); in pic32_spi_rx_irq()
268 if (pic32s->rx_end == pic32s->rx) { in pic32_spi_rx_irq()
270 disable_irq_nosync(pic32s->fault_irq); in pic32_spi_rx_irq()
271 disable_irq_nosync(pic32s->rx_irq); in pic32_spi_rx_irq()
274 complete(&pic32s->xfer_done); in pic32_spi_rx_irq()
284 pic32s->tx_fifo(pic32s); in pic32_spi_tx_irq()
287 if (pic32s->tx_end == pic32s->tx) in pic32_spi_tx_irq()
288 disable_irq_nosync(pic32s->tx_irq); in pic32_spi_tx_irq()
297 complete(&pic32s->xfer_done); in pic32_spi_dma_rx_notify()
303 struct spi_controller *host = pic32s->host; in pic32_spi_dma_transfer()
309 if (!host->dma_rx || !host->dma_tx) in pic32_spi_dma_transfer()
310 return -ENODEV; in pic32_spi_dma_transfer()
312 desc_rx = dmaengine_prep_slave_sg(host->dma_rx, in pic32_spi_dma_transfer()
313 xfer->rx_sg.sgl, in pic32_spi_dma_transfer()
314 xfer->rx_sg.nents, in pic32_spi_dma_transfer()
318 ret = -EINVAL; in pic32_spi_dma_transfer()
322 desc_tx = dmaengine_prep_slave_sg(host->dma_tx, in pic32_spi_dma_transfer()
323 xfer->tx_sg.sgl, in pic32_spi_dma_transfer()
324 xfer->tx_sg.nents, in pic32_spi_dma_transfer()
328 ret = -EINVAL; in pic32_spi_dma_transfer()
333 desc_rx->callback = pic32_spi_dma_rx_notify; in pic32_spi_dma_transfer()
334 desc_rx->callback_param = pic32s; in pic32_spi_dma_transfer()
346 dma_async_issue_pending(host->dma_rx); in pic32_spi_dma_transfer()
347 dma_async_issue_pending(host->dma_tx); in pic32_spi_dma_transfer()
352 dmaengine_terminate_all(host->dma_rx); in pic32_spi_dma_transfer()
360 struct spi_controller *host = pic32s->host; in pic32_spi_dma_config()
366 cfg.src_addr = pic32s->dma_base + buf_offset; in pic32_spi_dma_config()
367 cfg.dst_addr = pic32s->dma_base + buf_offset; in pic32_spi_dma_config()
368 cfg.src_maxburst = pic32s->fifo_n_elm / 2; /* fill one-half */ in pic32_spi_dma_config()
369 cfg.dst_maxburst = pic32s->fifo_n_elm / 2; /* drain one-half */ in pic32_spi_dma_config()
374 ret = dmaengine_slave_config(host->dma_tx, &cfg); in pic32_spi_dma_config()
376 dev_err(&host->dev, "tx channel setup failed\n"); in pic32_spi_dma_config()
381 ret = dmaengine_slave_config(host->dma_rx, &cfg); in pic32_spi_dma_config()
383 dev_err(&host->dev, "rx channel setup failed\n"); in pic32_spi_dma_config()
395 pic32s->rx_fifo = pic32_spi_rx_byte; in pic32_spi_set_word_size()
396 pic32s->tx_fifo = pic32_spi_tx_byte; in pic32_spi_set_word_size()
401 pic32s->rx_fifo = pic32_spi_rx_word; in pic32_spi_set_word_size()
402 pic32s->tx_fifo = pic32_spi_tx_word; in pic32_spi_set_word_size()
407 pic32s->rx_fifo = pic32_spi_rx_dword; in pic32_spi_set_word_size()
408 pic32s->tx_fifo = pic32_spi_tx_dword; in pic32_spi_set_word_size()
414 return -EINVAL; in pic32_spi_set_word_size()
418 pic32s->fifo_n_elm = DIV_ROUND_UP(pic32s->fifo_n_byte, in pic32_spi_set_word_size()
421 v = readl(&pic32s->regs->ctrl); in pic32_spi_set_word_size()
424 writel(v, &pic32s->regs->ctrl); in pic32_spi_set_word_size()
426 /* re-configure dma width, if required */ in pic32_spi_set_word_size()
427 if (test_bit(PIC32F_DMA_PREP, &pic32s->flags)) in pic32_spi_set_word_size()
446 struct spi_device *spi = msg->spi; in pic32_spi_prepare_message()
450 if (pic32s->bits_per_word != spi->bits_per_word) { in pic32_spi_prepare_message()
451 pic32_spi_set_word_size(pic32s, spi->bits_per_word); in pic32_spi_prepare_message()
452 pic32s->bits_per_word = spi->bits_per_word; in pic32_spi_prepare_message()
456 if (pic32s->speed_hz != spi->max_speed_hz) { in pic32_spi_prepare_message()
457 pic32_spi_set_clk_rate(pic32s, spi->max_speed_hz); in pic32_spi_prepare_message()
458 pic32s->speed_hz = spi->max_speed_hz; in pic32_spi_prepare_message()
462 if (pic32s->mode != spi->mode) { in pic32_spi_prepare_message()
463 val = readl(&pic32s->regs->ctrl); in pic32_spi_prepare_message()
465 if (spi->mode & SPI_CPOL) in pic32_spi_prepare_message()
470 if (spi->mode & SPI_CPHA) in pic32_spi_prepare_message()
477 writel(val, &pic32s->regs->ctrl); in pic32_spi_prepare_message()
478 pic32s->mode = spi->mode; in pic32_spi_prepare_message()
491 return (xfer->len >= PIC32_DMA_LEN_MIN) && in pic32_spi_can_dma()
492 test_bit(PIC32F_DMA_PREP, &pic32s->flags); in pic32_spi_can_dma()
507 if (transfer->bits_per_word && in pic32_spi_one_transfer()
508 (transfer->bits_per_word != pic32s->bits_per_word)) { in pic32_spi_one_transfer()
509 ret = pic32_spi_set_word_size(pic32s, transfer->bits_per_word); in pic32_spi_one_transfer()
512 pic32s->bits_per_word = transfer->bits_per_word; in pic32_spi_one_transfer()
516 if (transfer->speed_hz && (transfer->speed_hz != pic32s->speed_hz)) { in pic32_spi_one_transfer()
517 pic32_spi_set_clk_rate(pic32s, transfer->speed_hz); in pic32_spi_one_transfer()
518 pic32s->speed_hz = transfer->speed_hz; in pic32_spi_one_transfer()
521 reinit_completion(&pic32s->xfer_done); in pic32_spi_one_transfer()
524 if (transfer->rx_sg.nents && transfer->tx_sg.nents) { in pic32_spi_one_transfer()
527 dev_err(&spi->dev, "dma submit error\n"); in pic32_spi_one_transfer()
535 pic32s->tx = (const void *)transfer->tx_buf; in pic32_spi_one_transfer()
536 pic32s->rx = (const void *)transfer->rx_buf; in pic32_spi_one_transfer()
537 pic32s->tx_end = pic32s->tx + transfer->len; in pic32_spi_one_transfer()
538 pic32s->rx_end = pic32s->rx + transfer->len; in pic32_spi_one_transfer()
539 pic32s->len = transfer->len; in pic32_spi_one_transfer()
542 enable_irq(pic32s->fault_irq); in pic32_spi_one_transfer()
543 enable_irq(pic32s->rx_irq); in pic32_spi_one_transfer()
544 enable_irq(pic32s->tx_irq); in pic32_spi_one_transfer()
548 time_left = wait_for_completion_timeout(&pic32s->xfer_done, 2 * HZ); in pic32_spi_one_transfer()
550 dev_err(&spi->dev, "wait error/timedout\n"); in pic32_spi_one_transfer()
552 dmaengine_terminate_all(host->dma_rx); in pic32_spi_one_transfer()
553 dmaengine_terminate_all(host->dma_tx); in pic32_spi_one_transfer()
555 ret = -ETIMEDOUT; in pic32_spi_one_transfer()
582 if (!spi->max_speed_hz) { in pic32_spi_setup()
583 dev_err(&spi->dev, "No max speed HZ parameter\n"); in pic32_spi_setup()
584 return -EINVAL; in pic32_spi_setup()
588 * on tx fifo fill-level. /CS will stay asserted as long as TX in pic32_spi_setup()
589 * fifo is non-empty, else will be deasserted indicating in pic32_spi_setup()
592 * To avoid that we will always handle /CS by toggling GPIO. in pic32_spi_setup()
595 return -EINVAL; in pic32_spi_setup()
602 /* de-activate cs-gpio, gpiolib will handle inversion */ in pic32_spi_cleanup()
608 struct spi_controller *host = pic32s->host; in pic32_spi_dma_prep()
611 host->dma_rx = dma_request_chan(dev, "spi-rx"); in pic32_spi_dma_prep()
612 if (IS_ERR(host->dma_rx)) { in pic32_spi_dma_prep()
613 if (PTR_ERR(host->dma_rx) == -EPROBE_DEFER) in pic32_spi_dma_prep()
614 ret = -EPROBE_DEFER; in pic32_spi_dma_prep()
618 host->dma_rx = NULL; in pic32_spi_dma_prep()
622 host->dma_tx = dma_request_chan(dev, "spi-tx"); in pic32_spi_dma_prep()
623 if (IS_ERR(host->dma_tx)) { in pic32_spi_dma_prep()
624 if (PTR_ERR(host->dma_tx) == -EPROBE_DEFER) in pic32_spi_dma_prep()
625 ret = -EPROBE_DEFER; in pic32_spi_dma_prep()
629 host->dma_tx = NULL; in pic32_spi_dma_prep()
637 set_bit(PIC32F_DMA_PREP, &pic32s->flags); in pic32_spi_dma_prep()
642 if (host->dma_rx) { in pic32_spi_dma_prep()
643 dma_release_channel(host->dma_rx); in pic32_spi_dma_prep()
644 host->dma_rx = NULL; in pic32_spi_dma_prep()
647 if (host->dma_tx) { in pic32_spi_dma_prep()
648 dma_release_channel(host->dma_tx); in pic32_spi_dma_prep()
649 host->dma_tx = NULL; in pic32_spi_dma_prep()
657 if (!test_bit(PIC32F_DMA_PREP, &pic32s->flags)) in pic32_spi_dma_unprep()
660 clear_bit(PIC32F_DMA_PREP, &pic32s->flags); in pic32_spi_dma_unprep()
661 if (pic32s->host->dma_rx) in pic32_spi_dma_unprep()
662 dma_release_channel(pic32s->host->dma_rx); in pic32_spi_dma_unprep()
664 if (pic32s->host->dma_tx) in pic32_spi_dma_unprep()
665 dma_release_channel(pic32s->host->dma_tx); in pic32_spi_dma_unprep()
675 ctrl = readl(&pic32s->regs->ctrl); in pic32_spi_hw_init()
678 pic32s->fifo_n_byte = 16; in pic32_spi_hw_init()
700 writel(ctrl, &pic32s->regs->ctrl); in pic32_spi_hw_init()
704 writel(ctrl, &pic32s->regs->ctrl2_set); in pic32_spi_hw_init()
713 pic32s->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); in pic32_spi_hw_probe()
714 if (IS_ERR(pic32s->regs)) in pic32_spi_hw_probe()
715 return PTR_ERR(pic32s->regs); in pic32_spi_hw_probe()
717 pic32s->dma_base = mem->start; in pic32_spi_hw_probe()
719 /* get irq resources: err-irq, rx-irq, tx-irq */ in pic32_spi_hw_probe()
720 pic32s->fault_irq = platform_get_irq_byname(pdev, "fault"); in pic32_spi_hw_probe()
721 if (pic32s->fault_irq < 0) in pic32_spi_hw_probe()
722 return pic32s->fault_irq; in pic32_spi_hw_probe()
724 pic32s->rx_irq = platform_get_irq_byname(pdev, "rx"); in pic32_spi_hw_probe()
725 if (pic32s->rx_irq < 0) in pic32_spi_hw_probe()
726 return pic32s->rx_irq; in pic32_spi_hw_probe()
728 pic32s->tx_irq = platform_get_irq_byname(pdev, "tx"); in pic32_spi_hw_probe()
729 if (pic32s->tx_irq < 0) in pic32_spi_hw_probe()
730 return pic32s->tx_irq; in pic32_spi_hw_probe()
733 pic32s->clk = devm_clk_get_enabled(&pdev->dev, "mck0"); in pic32_spi_hw_probe()
734 if (IS_ERR(pic32s->clk)) { in pic32_spi_hw_probe()
735 dev_err(&pdev->dev, "clk not found\n"); in pic32_spi_hw_probe()
736 ret = PTR_ERR(pic32s->clk); in pic32_spi_hw_probe()
745 dev_err(&pdev->dev, "%s failed, err %d\n", __func__, ret); in pic32_spi_hw_probe()
755 host = spi_alloc_host(&pdev->dev, sizeof(*pic32s)); in pic32_spi_probe()
757 return -ENOMEM; in pic32_spi_probe()
760 pic32s->host = host; in pic32_spi_probe()
766 host->dev.of_node = pdev->dev.of_node; in pic32_spi_probe()
767 host->mode_bits = SPI_MODE_3 | SPI_MODE_0 | SPI_CS_HIGH; in pic32_spi_probe()
768 host->num_chipselect = 1; /* single chip-select */ in pic32_spi_probe()
769 host->max_speed_hz = clk_get_rate(pic32s->clk); in pic32_spi_probe()
770 host->setup = pic32_spi_setup; in pic32_spi_probe()
771 host->cleanup = pic32_spi_cleanup; in pic32_spi_probe()
772 host->flags = SPI_CONTROLLER_MUST_TX | SPI_CONTROLLER_MUST_RX; in pic32_spi_probe()
773 host->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) | in pic32_spi_probe()
775 host->transfer_one = pic32_spi_one_transfer; in pic32_spi_probe()
776 host->prepare_message = pic32_spi_prepare_message; in pic32_spi_probe()
777 host->unprepare_message = pic32_spi_unprepare_message; in pic32_spi_probe()
778 host->prepare_transfer_hardware = pic32_spi_prepare_hardware; in pic32_spi_probe()
779 host->unprepare_transfer_hardware = pic32_spi_unprepare_hardware; in pic32_spi_probe()
780 host->use_gpio_descriptors = true; in pic32_spi_probe()
783 ret = pic32_spi_dma_prep(pic32s, &pdev->dev); in pic32_spi_probe()
787 if (test_bit(PIC32F_DMA_PREP, &pic32s->flags)) in pic32_spi_probe()
788 host->can_dma = pic32_spi_can_dma; in pic32_spi_probe()
790 init_completion(&pic32s->xfer_done); in pic32_spi_probe()
791 pic32s->mode = -1; in pic32_spi_probe()
793 /* install irq handlers (with irq-disabled) */ in pic32_spi_probe()
794 irq_set_status_flags(pic32s->fault_irq, IRQ_NOAUTOEN); in pic32_spi_probe()
795 ret = devm_request_irq(&pdev->dev, pic32s->fault_irq, in pic32_spi_probe()
797 dev_name(&pdev->dev), pic32s); in pic32_spi_probe()
799 dev_err(&pdev->dev, "request fault-irq %d\n", pic32s->rx_irq); in pic32_spi_probe()
804 irq_set_status_flags(pic32s->rx_irq, IRQ_NOAUTOEN); in pic32_spi_probe()
805 ret = devm_request_irq(&pdev->dev, pic32s->rx_irq, in pic32_spi_probe()
807 dev_name(&pdev->dev), pic32s); in pic32_spi_probe()
809 dev_err(&pdev->dev, "request rx-irq %d\n", pic32s->rx_irq); in pic32_spi_probe()
814 irq_set_status_flags(pic32s->tx_irq, IRQ_NOAUTOEN); in pic32_spi_probe()
815 ret = devm_request_irq(&pdev->dev, pic32s->tx_irq, in pic32_spi_probe()
817 dev_name(&pdev->dev), pic32s); in pic32_spi_probe()
819 dev_err(&pdev->dev, "request tx-irq %d\n", pic32s->tx_irq); in pic32_spi_probe()
824 ret = devm_spi_register_controller(&pdev->dev, host); in pic32_spi_probe()
826 dev_err(&host->dev, "failed registering spi host\n"); in pic32_spi_probe()
851 {.compatible = "microchip,pic32mzda-spi",},
858 .name = "spi-pic32",