Lines Matching +full:gpio +full:- +full:op +full:- +full:cfg
1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/mtd/nand-ecc-mxic.h>
20 #include <linux/spi/spi-mem.h>
74 #define OP_CMD_BYTES(x) (((x) - 1) << 13)
161 #define GPIO 0xc4 macro
195 ret = clk_prepare_enable(mxic->send_clk); in mxic_spi_clk_enable()
199 ret = clk_prepare_enable(mxic->send_dly_clk); in mxic_spi_clk_enable()
206 clk_disable_unprepare(mxic->send_clk); in mxic_spi_clk_enable()
213 clk_disable_unprepare(mxic->send_clk); in mxic_spi_clk_disable()
214 clk_disable_unprepare(mxic->send_dly_clk); in mxic_spi_clk_disable()
223 mxic->regs + IDLY_CODE(0)); in mxic_spi_set_input_delay_dqs()
228 mxic->regs + IDLY_CODE(1)); in mxic_spi_set_input_delay_dqs()
235 ret = clk_set_rate(mxic->send_clk, freq); in mxic_spi_clk_setup()
239 ret = clk_set_rate(mxic->send_dly_clk, freq); in mxic_spi_clk_setup()
250 * Phase degree = 360 * freq * output-delay in mxic_spi_clk_setup()
251 * where output-delay is a constant value 1 ns in FPGA. in mxic_spi_clk_setup()
257 ret = clk_set_phase(mxic->send_dly_clk, 9 * freq / 25000000); in mxic_spi_clk_setup()
268 if (mxic->cur_speed_hz == freq) in mxic_spi_set_freq()
280 mxic->cur_speed_hz = freq; in mxic_spi_set_freq()
287 writel(0, mxic->regs + DATA_STROB); in mxic_spi_hw_init()
288 writel(INT_STS_ALL, mxic->regs + INT_STS_EN); in mxic_spi_hw_init()
289 writel(0, mxic->regs + HC_EN); in mxic_spi_hw_init()
290 writel(0, mxic->regs + LRD_CFG); in mxic_spi_hw_init()
291 writel(0, mxic->regs + LRD_CTRL); in mxic_spi_hw_init()
294 mxic->regs + HC_CFG); in mxic_spi_hw_init()
301 if (spi->mode & (SPI_TX_OCTAL | SPI_RX_OCTAL)) in mxic_spi_prep_hc_cfg()
303 else if (spi->mode & (SPI_TX_QUAD | SPI_RX_QUAD)) in mxic_spi_prep_hc_cfg()
305 else if (spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL)) in mxic_spi_prep_hc_cfg()
313 static u32 mxic_spi_mem_prep_op_cfg(const struct spi_mem_op *op, in mxic_spi_mem_prep_op_cfg() argument
316 u32 cfg = OP_CMD_BYTES(op->cmd.nbytes) | in mxic_spi_mem_prep_op_cfg() local
317 OP_CMD_BUSW(fls(op->cmd.buswidth) - 1) | in mxic_spi_mem_prep_op_cfg()
318 (op->cmd.dtr ? OP_CMD_DDR : 0); in mxic_spi_mem_prep_op_cfg()
320 if (op->addr.nbytes) in mxic_spi_mem_prep_op_cfg()
321 cfg |= OP_ADDR_BYTES(op->addr.nbytes) | in mxic_spi_mem_prep_op_cfg()
322 OP_ADDR_BUSW(fls(op->addr.buswidth) - 1) | in mxic_spi_mem_prep_op_cfg()
323 (op->addr.dtr ? OP_ADDR_DDR : 0); in mxic_spi_mem_prep_op_cfg()
325 if (op->dummy.nbytes) in mxic_spi_mem_prep_op_cfg()
326 cfg |= OP_DUMMY_CYC(op->dummy.nbytes); in mxic_spi_mem_prep_op_cfg()
330 cfg |= OP_DATA_BUSW(fls(op->data.buswidth) - 1) | in mxic_spi_mem_prep_op_cfg()
331 (op->data.dtr ? OP_DATA_DDR : 0); in mxic_spi_mem_prep_op_cfg()
332 if (op->data.dir == SPI_MEM_DATA_IN) { in mxic_spi_mem_prep_op_cfg()
333 cfg |= OP_READ; in mxic_spi_mem_prep_op_cfg()
334 if (op->data.dtr) in mxic_spi_mem_prep_op_cfg()
335 cfg |= OP_DQS_EN; in mxic_spi_mem_prep_op_cfg()
339 return cfg; in mxic_spi_mem_prep_op_cfg()
348 unsigned int nbytes = len - pos; in mxic_spi_data_xfer()
359 ret = readl_poll_timeout(mxic->regs + INT_STS, sts, in mxic_spi_data_xfer()
364 writel(data, mxic->regs + TXD(nbytes % 4)); in mxic_spi_data_xfer()
366 ret = readl_poll_timeout(mxic->regs + INT_STS, sts, in mxic_spi_data_xfer()
371 ret = readl_poll_timeout(mxic->regs + INT_STS, sts, in mxic_spi_data_xfer()
377 data = readl(mxic->regs + RXD); in mxic_spi_data_xfer()
379 data >>= (8 * (4 - nbytes)); in mxic_spi_data_xfer()
382 WARN_ON(readl(mxic->regs + INT_STS) & INT_RX_NOT_EMPTY); in mxic_spi_data_xfer()
393 struct mxic_spi *mxic = spi_controller_get_devdata(desc->mem->spi->controller); in mxic_spi_mem_dirmap_read()
397 if (WARN_ON(offs + desc->info.offset + len > U32_MAX)) in mxic_spi_mem_dirmap_read()
398 return -EINVAL; in mxic_spi_mem_dirmap_read()
400 writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0), mxic->regs + HC_CFG); in mxic_spi_mem_dirmap_read()
402 writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len), in mxic_spi_mem_dirmap_read()
403 mxic->regs + LRD_CFG); in mxic_spi_mem_dirmap_read()
404 writel(desc->info.offset + offs, mxic->regs + LRD_ADDR); in mxic_spi_mem_dirmap_read()
405 len = min_t(size_t, len, mxic->linear.size); in mxic_spi_mem_dirmap_read()
406 writel(len, mxic->regs + LRD_RANGE); in mxic_spi_mem_dirmap_read()
407 writel(LMODE_CMD0(desc->info.op_tmpl.cmd.opcode) | in mxic_spi_mem_dirmap_read()
408 LMODE_SLV_ACT(spi_get_chipselect(desc->mem->spi, 0)) | in mxic_spi_mem_dirmap_read()
410 mxic->regs + LRD_CTRL); in mxic_spi_mem_dirmap_read()
412 if (mxic->ecc.use_pipelined_conf && desc->info.op_tmpl.data.ecc) { in mxic_spi_mem_dirmap_read()
413 ret = mxic_ecc_process_data_pipelined(mxic->ecc.pipelined_engine, in mxic_spi_mem_dirmap_read()
415 mxic->linear.dma + offs); in mxic_spi_mem_dirmap_read()
419 memcpy_fromio(buf, mxic->linear.map, len); in mxic_spi_mem_dirmap_read()
422 writel(INT_LRD_DIS, mxic->regs + INT_STS); in mxic_spi_mem_dirmap_read()
423 writel(0, mxic->regs + LRD_CTRL); in mxic_spi_mem_dirmap_read()
425 ret = readl_poll_timeout(mxic->regs + INT_STS, sts, in mxic_spi_mem_dirmap_read()
437 struct mxic_spi *mxic = spi_controller_get_devdata(desc->mem->spi->controller); in mxic_spi_mem_dirmap_write()
441 if (WARN_ON(offs + desc->info.offset + len > U32_MAX)) in mxic_spi_mem_dirmap_write()
442 return -EINVAL; in mxic_spi_mem_dirmap_write()
444 writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0), mxic->regs + HC_CFG); in mxic_spi_mem_dirmap_write()
446 writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len), in mxic_spi_mem_dirmap_write()
447 mxic->regs + LWR_CFG); in mxic_spi_mem_dirmap_write()
448 writel(desc->info.offset + offs, mxic->regs + LWR_ADDR); in mxic_spi_mem_dirmap_write()
449 len = min_t(size_t, len, mxic->linear.size); in mxic_spi_mem_dirmap_write()
450 writel(len, mxic->regs + LWR_RANGE); in mxic_spi_mem_dirmap_write()
451 writel(LMODE_CMD0(desc->info.op_tmpl.cmd.opcode) | in mxic_spi_mem_dirmap_write()
452 LMODE_SLV_ACT(spi_get_chipselect(desc->mem->spi, 0)) | in mxic_spi_mem_dirmap_write()
454 mxic->regs + LWR_CTRL); in mxic_spi_mem_dirmap_write()
456 if (mxic->ecc.use_pipelined_conf && desc->info.op_tmpl.data.ecc) { in mxic_spi_mem_dirmap_write()
457 ret = mxic_ecc_process_data_pipelined(mxic->ecc.pipelined_engine, in mxic_spi_mem_dirmap_write()
459 mxic->linear.dma + offs); in mxic_spi_mem_dirmap_write()
463 memcpy_toio(mxic->linear.map, buf, len); in mxic_spi_mem_dirmap_write()
466 writel(INT_LWR_DIS, mxic->regs + INT_STS); in mxic_spi_mem_dirmap_write()
467 writel(0, mxic->regs + LWR_CTRL); in mxic_spi_mem_dirmap_write()
469 ret = readl_poll_timeout(mxic->regs + INT_STS, sts, in mxic_spi_mem_dirmap_write()
478 const struct spi_mem_op *op) in mxic_spi_mem_supports_op() argument
480 if (op->data.buswidth > 8 || op->addr.buswidth > 8 || in mxic_spi_mem_supports_op()
481 op->dummy.buswidth > 8 || op->cmd.buswidth > 8) in mxic_spi_mem_supports_op()
484 if (op->data.nbytes && op->dummy.nbytes && in mxic_spi_mem_supports_op()
485 op->data.buswidth != op->dummy.buswidth) in mxic_spi_mem_supports_op()
488 if (op->addr.nbytes > 7) in mxic_spi_mem_supports_op()
491 return spi_mem_default_supports_op(mem, op); in mxic_spi_mem_supports_op()
496 struct mxic_spi *mxic = spi_controller_get_devdata(desc->mem->spi->controller); in mxic_spi_mem_dirmap_create()
498 if (!mxic->linear.map) in mxic_spi_mem_dirmap_create()
499 return -EOPNOTSUPP; in mxic_spi_mem_dirmap_create()
501 if (desc->info.offset + desc->info.length > U32_MAX) in mxic_spi_mem_dirmap_create()
502 return -EINVAL; in mxic_spi_mem_dirmap_create()
504 if (!mxic_spi_mem_supports_op(desc->mem, &desc->info.op_tmpl)) in mxic_spi_mem_dirmap_create()
505 return -EOPNOTSUPP; in mxic_spi_mem_dirmap_create()
511 const struct spi_mem_op *op) in mxic_spi_mem_exec_op() argument
513 struct mxic_spi *mxic = spi_controller_get_devdata(mem->spi->controller); in mxic_spi_mem_exec_op()
517 ret = mxic_spi_set_freq(mxic, mem->spi->max_speed_hz); in mxic_spi_mem_exec_op()
521 writel(mxic_spi_prep_hc_cfg(mem->spi, HC_CFG_MAN_CS_EN), in mxic_spi_mem_exec_op()
522 mxic->regs + HC_CFG); in mxic_spi_mem_exec_op()
524 writel(HC_EN_BIT, mxic->regs + HC_EN); in mxic_spi_mem_exec_op()
526 writel(mxic_spi_mem_prep_op_cfg(op, op->data.nbytes), in mxic_spi_mem_exec_op()
527 mxic->regs + SS_CTRL(spi_get_chipselect(mem->spi, 0))); in mxic_spi_mem_exec_op()
529 writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT, in mxic_spi_mem_exec_op()
530 mxic->regs + HC_CFG); in mxic_spi_mem_exec_op()
532 for (i = 0; i < op->cmd.nbytes; i++) in mxic_spi_mem_exec_op()
533 cmd[i] = op->cmd.opcode >> (8 * (op->cmd.nbytes - i - 1)); in mxic_spi_mem_exec_op()
535 ret = mxic_spi_data_xfer(mxic, cmd, NULL, op->cmd.nbytes); in mxic_spi_mem_exec_op()
539 for (i = 0; i < op->addr.nbytes; i++) in mxic_spi_mem_exec_op()
540 addr[i] = op->addr.val >> (8 * (op->addr.nbytes - i - 1)); in mxic_spi_mem_exec_op()
542 ret = mxic_spi_data_xfer(mxic, addr, NULL, op->addr.nbytes); in mxic_spi_mem_exec_op()
546 ret = mxic_spi_data_xfer(mxic, NULL, NULL, op->dummy.nbytes); in mxic_spi_mem_exec_op()
551 op->data.dir == SPI_MEM_DATA_OUT ? in mxic_spi_mem_exec_op()
552 op->data.buf.out : NULL, in mxic_spi_mem_exec_op()
553 op->data.dir == SPI_MEM_DATA_IN ? in mxic_spi_mem_exec_op()
554 op->data.buf.in : NULL, in mxic_spi_mem_exec_op()
555 op->data.nbytes); in mxic_spi_mem_exec_op()
558 writel(readl(mxic->regs + HC_CFG) & ~HC_CFG_MAN_CS_ASSERT, in mxic_spi_mem_exec_op()
559 mxic->regs + HC_CFG); in mxic_spi_mem_exec_op()
560 writel(0, mxic->regs + HC_EN); in mxic_spi_mem_exec_op()
580 struct mxic_spi *mxic = spi_controller_get_devdata(spi->controller); in mxic_spi_set_cs()
583 writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_EN, in mxic_spi_set_cs()
584 mxic->regs + HC_CFG); in mxic_spi_set_cs()
585 writel(HC_EN_BIT, mxic->regs + HC_EN); in mxic_spi_set_cs()
586 writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT, in mxic_spi_set_cs()
587 mxic->regs + HC_CFG); in mxic_spi_set_cs()
589 writel(readl(mxic->regs + HC_CFG) & ~HC_CFG_MAN_CS_ASSERT, in mxic_spi_set_cs()
590 mxic->regs + HC_CFG); in mxic_spi_set_cs()
591 writel(0, mxic->regs + HC_EN); in mxic_spi_set_cs()
603 if (t->rx_buf && t->tx_buf) { in mxic_spi_transfer_one()
604 if (((spi->mode & SPI_TX_QUAD) && in mxic_spi_transfer_one()
605 !(spi->mode & SPI_RX_QUAD)) || in mxic_spi_transfer_one()
606 ((spi->mode & SPI_TX_DUAL) && in mxic_spi_transfer_one()
607 !(spi->mode & SPI_RX_DUAL))) in mxic_spi_transfer_one()
608 return -ENOTSUPP; in mxic_spi_transfer_one()
611 ret = mxic_spi_set_freq(mxic, t->speed_hz); in mxic_spi_transfer_one()
615 if (t->tx_buf) { in mxic_spi_transfer_one()
616 if (spi->mode & SPI_TX_QUAD) in mxic_spi_transfer_one()
618 else if (spi->mode & SPI_TX_DUAL) in mxic_spi_transfer_one()
620 } else if (t->rx_buf) { in mxic_spi_transfer_one()
621 if (spi->mode & SPI_RX_QUAD) in mxic_spi_transfer_one()
623 else if (spi->mode & SPI_RX_DUAL) in mxic_spi_transfer_one()
628 OP_DATA_BUSW(busw) | (t->rx_buf ? OP_READ : 0), in mxic_spi_transfer_one()
629 mxic->regs + SS_CTRL(0)); in mxic_spi_transfer_one()
631 ret = mxic_spi_data_xfer(mxic, t->tx_buf, t->rx_buf, t->len); in mxic_spi_transfer_one()
644 struct mxic_spi *mxic = nand->ecc.engine->priv; in mxic_spi_mem_ecc_init_ctx()
646 mxic->ecc.use_pipelined_conf = true; in mxic_spi_mem_ecc_init_ctx()
648 return ops->init_ctx(nand); in mxic_spi_mem_ecc_init_ctx()
654 struct mxic_spi *mxic = nand->ecc.engine->priv; in mxic_spi_mem_ecc_cleanup_ctx()
656 mxic->ecc.use_pipelined_conf = false; in mxic_spi_mem_ecc_cleanup_ctx()
658 ops->cleanup_ctx(nand); in mxic_spi_mem_ecc_cleanup_ctx()
666 return ops->prepare_io_req(nand, req); in mxic_spi_mem_ecc_prepare_io_req()
674 return ops->finish_io_req(nand, req); in mxic_spi_mem_ecc_finish_io_req()
686 if (mxic->ecc.pipelined_engine) { in mxic_spi_mem_ecc_remove()
687 mxic_ecc_put_pipelined_engine(mxic->ecc.pipelined_engine); in mxic_spi_mem_ecc_remove()
688 nand_ecc_unregister_on_host_hw_engine(mxic->ecc.pipelined_engine); in mxic_spi_mem_ecc_remove()
698 return -EOPNOTSUPP; in mxic_spi_mem_ecc_probe()
704 eng->dev = &pdev->dev; in mxic_spi_mem_ecc_probe()
705 eng->integration = NAND_ECC_ENGINE_INTEGRATION_PIPELINED; in mxic_spi_mem_ecc_probe()
706 eng->ops = &mxic_spi_mem_ecc_engine_pipelined_ops; in mxic_spi_mem_ecc_probe()
707 eng->priv = mxic; in mxic_spi_mem_ecc_probe()
708 mxic->ecc.pipelined_engine = eng; in mxic_spi_mem_ecc_probe()
720 clk_disable_unprepare(mxic->ps_clk); in mxic_spi_runtime_suspend()
731 ret = clk_prepare_enable(mxic->ps_clk); in mxic_spi_runtime_resume()
752 host = devm_spi_alloc_host(&pdev->dev, sizeof(struct mxic_spi)); in mxic_spi_probe()
754 return -ENOMEM; in mxic_spi_probe()
759 mxic->dev = &pdev->dev; in mxic_spi_probe()
761 host->dev.of_node = pdev->dev.of_node; in mxic_spi_probe()
763 mxic->ps_clk = devm_clk_get(&pdev->dev, "ps_clk"); in mxic_spi_probe()
764 if (IS_ERR(mxic->ps_clk)) in mxic_spi_probe()
765 return PTR_ERR(mxic->ps_clk); in mxic_spi_probe()
767 mxic->send_clk = devm_clk_get(&pdev->dev, "send_clk"); in mxic_spi_probe()
768 if (IS_ERR(mxic->send_clk)) in mxic_spi_probe()
769 return PTR_ERR(mxic->send_clk); in mxic_spi_probe()
771 mxic->send_dly_clk = devm_clk_get(&pdev->dev, "send_dly_clk"); in mxic_spi_probe()
772 if (IS_ERR(mxic->send_dly_clk)) in mxic_spi_probe()
773 return PTR_ERR(mxic->send_dly_clk); in mxic_spi_probe()
775 mxic->regs = devm_platform_ioremap_resource_byname(pdev, "regs"); in mxic_spi_probe()
776 if (IS_ERR(mxic->regs)) in mxic_spi_probe()
777 return PTR_ERR(mxic->regs); in mxic_spi_probe()
780 mxic->linear.map = devm_ioremap_resource(&pdev->dev, res); in mxic_spi_probe()
781 if (!IS_ERR(mxic->linear.map)) { in mxic_spi_probe()
782 mxic->linear.dma = res->start; in mxic_spi_probe()
783 mxic->linear.size = resource_size(res); in mxic_spi_probe()
785 mxic->linear.map = NULL; in mxic_spi_probe()
788 pm_runtime_enable(&pdev->dev); in mxic_spi_probe()
789 host->auto_runtime_pm = true; in mxic_spi_probe()
791 host->num_chipselect = 1; in mxic_spi_probe()
792 host->mem_ops = &mxic_spi_mem_ops; in mxic_spi_probe()
793 host->mem_caps = &mxic_spi_mem_caps; in mxic_spi_probe()
795 host->set_cs = mxic_spi_set_cs; in mxic_spi_probe()
796 host->transfer_one = mxic_spi_transfer_one; in mxic_spi_probe()
797 host->bits_per_word_mask = SPI_BPW_MASK(8); in mxic_spi_probe()
798 host->mode_bits = SPI_CPOL | SPI_CPHA | in mxic_spi_probe()
806 if (ret == -EPROBE_DEFER) { in mxic_spi_probe()
807 pm_runtime_disable(&pdev->dev); in mxic_spi_probe()
813 dev_err(&pdev->dev, "spi_register_controller failed\n"); in mxic_spi_probe()
814 pm_runtime_disable(&pdev->dev); in mxic_spi_probe()
826 pm_runtime_disable(&pdev->dev); in mxic_spi_remove()
832 { .compatible = "mxicy,mx25f0a-spi", },
841 .name = "mxic-spi",