Lines Matching +full:spi +full:- +full:src +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0
3 // Mediatek SPI NOR controller driver
8 #include <linux/clk.h>
10 #include <linux/dma-mapping.h>
19 #include <linux/spi/spi.h>
20 #include <linux/spi/spi-mem.h>
23 #define DRIVER_NAME "mtk-spi-nor"
91 // Reading DMA src/dst addresses have to be 16-byte aligned
93 #define MTK_NOR_DMA_ALIGN_MASK (MTK_NOR_DMA_ALIGN - 1)
97 // Buffered page program can do one 128-byte transfer
100 #define CLK_TO_US(sp, clkcnt) DIV_ROUND_UP(clkcnt, sp->spi_freq / 1000000)
119 struct clk *spi_clk;
120 struct clk *ctlr_clk;
121 struct clk *axi_clk;
122 struct clk *axi_s_clk;
133 u32 val = readl(sp->base + reg); in mtk_nor_rmw()
137 writel(val, sp->base + reg); in mtk_nor_rmw()
140 static inline int mtk_nor_cmd_exec(struct mtk_nor *sp, u32 cmd, ulong clk) in mtk_nor_cmd_exec() argument
142 ulong delay = CLK_TO_US(sp, clk); in mtk_nor_cmd_exec()
146 writel(cmd, sp->base + MTK_NOR_REG_CMD); in mtk_nor_cmd_exec()
147 ret = readl_poll_timeout(sp->base + MTK_NOR_REG_CMD, reg, !(reg & cmd), in mtk_nor_cmd_exec()
150 dev_err(sp->dev, "command %u timeout.\n", cmd); in mtk_nor_cmd_exec()
160 writel(MTK_NOR_ENABLE_SF_CMD, sp->base + MTK_NOR_REG_WP); in mtk_nor_reset()
165 u32 addr = op->addr.val; in mtk_nor_set_addr()
169 writeb(addr & 0xff, sp->base + MTK_NOR_REG_RADR(i)); in mtk_nor_set_addr()
172 if (op->addr.nbytes == 4) { in mtk_nor_set_addr()
173 writeb(addr & 0xff, sp->base + MTK_NOR_REG_RADR3); in mtk_nor_set_addr()
182 return ((uintptr_t)op->data.buf.in & MTK_NOR_DMA_ALIGN_MASK); in need_bounce()
189 if (op->dummy.nbytes) in mtk_nor_match_read()
190 dummy = op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth; in mtk_nor_match_read()
192 if ((op->data.buswidth == 2) || (op->data.buswidth == 4)) { in mtk_nor_match_read()
193 if (op->addr.buswidth == 1) in mtk_nor_match_read()
195 else if (op->addr.buswidth == 2) in mtk_nor_match_read()
197 else if (op->addr.buswidth == 4) in mtk_nor_match_read()
199 } else if ((op->addr.buswidth == 1) && (op->data.buswidth == 1)) { in mtk_nor_match_read()
200 if (op->cmd.opcode == 0x03) in mtk_nor_match_read()
202 else if (op->cmd.opcode == 0x0b) in mtk_nor_match_read()
212 // prg mode is spi-only. in mtk_nor_match_prg()
213 if ((op->cmd.buswidth > 1) || (op->addr.buswidth > 1) || in mtk_nor_match_prg()
214 (op->dummy.buswidth > 1) || (op->data.buswidth > 1)) in mtk_nor_match_prg()
217 tx_len = op->cmd.nbytes + op->addr.nbytes; in mtk_nor_match_prg()
219 if (op->data.dir == SPI_MEM_DATA_OUT) { in mtk_nor_match_prg()
221 tx_len += op->dummy.nbytes; in mtk_nor_match_prg()
229 if ((!op->addr.nbytes) && in mtk_nor_match_prg()
230 (tx_len + op->data.nbytes > MTK_NOR_REG_PRGDATA_MAX + 1)) in mtk_nor_match_prg()
232 } else if (op->data.dir == SPI_MEM_DATA_IN) { in mtk_nor_match_prg()
236 rx_len = op->data.nbytes; in mtk_nor_match_prg()
237 prg_left = MTK_NOR_PRG_CNT_MAX / 8 - tx_len - op->dummy.nbytes; in mtk_nor_match_prg()
241 if (!op->addr.nbytes) in mtk_nor_match_prg()
246 prg_len = tx_len + op->dummy.nbytes + rx_len; in mtk_nor_match_prg()
250 prg_len = tx_len + op->dummy.nbytes; in mtk_nor_match_prg()
261 tx_len = op->cmd.nbytes + op->addr.nbytes; in mtk_nor_adj_prg_size()
262 if (op->data.dir == SPI_MEM_DATA_OUT) { in mtk_nor_adj_prg_size()
263 tx_len += op->dummy.nbytes; in mtk_nor_adj_prg_size()
264 tx_left = MTK_NOR_REG_PRGDATA_MAX + 1 - tx_len; in mtk_nor_adj_prg_size()
265 if (op->data.nbytes > tx_left) in mtk_nor_adj_prg_size()
266 op->data.nbytes = tx_left; in mtk_nor_adj_prg_size()
267 } else if (op->data.dir == SPI_MEM_DATA_IN) { in mtk_nor_adj_prg_size()
268 prg_left = MTK_NOR_PRG_CNT_MAX / 8 - tx_len - op->dummy.nbytes; in mtk_nor_adj_prg_size()
271 if (op->data.nbytes > prg_left) in mtk_nor_adj_prg_size()
272 op->data.nbytes = prg_left; in mtk_nor_adj_prg_size()
278 struct mtk_nor *sp = spi_controller_get_devdata(mem->spi->controller); in mtk_nor_adjust_op_size()
280 if (!op->data.nbytes) in mtk_nor_adjust_op_size()
283 if ((op->addr.nbytes == 3) || (op->addr.nbytes == 4)) { in mtk_nor_adjust_op_size()
284 if ((op->data.dir == SPI_MEM_DATA_IN) && in mtk_nor_adjust_op_size()
287 if (op->data.nbytes > 0x400000) in mtk_nor_adjust_op_size()
288 op->data.nbytes = 0x400000; in mtk_nor_adjust_op_size()
290 if ((op->addr.val & MTK_NOR_DMA_ALIGN_MASK) || in mtk_nor_adjust_op_size()
291 (op->data.nbytes < MTK_NOR_DMA_ALIGN)) in mtk_nor_adjust_op_size()
292 op->data.nbytes = 1; in mtk_nor_adjust_op_size()
294 op->data.nbytes &= ~MTK_NOR_DMA_ALIGN_MASK; in mtk_nor_adjust_op_size()
295 else if (op->data.nbytes > MTK_NOR_BOUNCE_BUF_SIZE) in mtk_nor_adjust_op_size()
296 op->data.nbytes = MTK_NOR_BOUNCE_BUF_SIZE; in mtk_nor_adjust_op_size()
298 } else if (op->data.dir == SPI_MEM_DATA_OUT) { in mtk_nor_adjust_op_size()
299 if (op->data.nbytes >= MTK_NOR_PP_SIZE) in mtk_nor_adjust_op_size()
300 op->data.nbytes = MTK_NOR_PP_SIZE; in mtk_nor_adjust_op_size()
302 op->data.nbytes = 1; in mtk_nor_adjust_op_size()
317 if (op->cmd.buswidth != 1) in mtk_nor_supports_op()
320 if ((op->addr.nbytes == 3) || (op->addr.nbytes == 4)) { in mtk_nor_supports_op()
321 switch (op->data.dir) { in mtk_nor_supports_op()
327 if ((op->addr.buswidth == 1) && in mtk_nor_supports_op()
328 (op->dummy.nbytes == 0) && in mtk_nor_supports_op()
329 (op->data.buswidth == 1)) in mtk_nor_supports_op()
344 if (op->addr.nbytes == 4) in mtk_nor_setup_bus()
347 if (op->data.buswidth == 4) { in mtk_nor_setup_bus()
349 writeb(op->cmd.opcode, sp->base + MTK_NOR_REG_PRGDATA(4)); in mtk_nor_setup_bus()
350 if (op->addr.buswidth == 4) in mtk_nor_setup_bus()
352 } else if (op->data.buswidth == 2) { in mtk_nor_setup_bus()
354 writeb(op->cmd.opcode, sp->base + MTK_NOR_REG_PRGDATA(3)); in mtk_nor_setup_bus()
355 if (op->addr.buswidth == 2) in mtk_nor_setup_bus()
358 if (op->cmd.opcode == 0x0b) in mtk_nor_setup_bus()
373 writel(from, sp->base + MTK_NOR_REG_DMA_FADR); in mtk_nor_dma_exec()
374 writel(dma_addr, sp->base + MTK_NOR_REG_DMA_DADR); in mtk_nor_dma_exec()
375 writel(dma_addr + length, sp->base + MTK_NOR_REG_DMA_END_DADR); in mtk_nor_dma_exec()
377 if (sp->high_dma) { in mtk_nor_dma_exec()
379 sp->base + MTK_NOR_REG_DMA_DADR_HB); in mtk_nor_dma_exec()
381 sp->base + MTK_NOR_REG_DMA_END_DADR_HB); in mtk_nor_dma_exec()
384 if (sp->has_irq) { in mtk_nor_dma_exec()
385 reinit_completion(&sp->op_done); in mtk_nor_dma_exec()
394 if (sp->has_irq) { in mtk_nor_dma_exec()
395 if (!wait_for_completion_timeout(&sp->op_done, in mtk_nor_dma_exec()
397 ret = -ETIMEDOUT; in mtk_nor_dma_exec()
399 ret = readl_poll_timeout(sp->base + MTK_NOR_REG_DMA_CTL, reg, in mtk_nor_dma_exec()
405 dev_err(sp->dev, "dma read timeout.\n"); in mtk_nor_dma_exec()
415 if (op->data.nbytes & MTK_NOR_DMA_ALIGN_MASK) in mtk_nor_read_bounce()
416 rdlen = (op->data.nbytes + MTK_NOR_DMA_ALIGN) & ~MTK_NOR_DMA_ALIGN_MASK; in mtk_nor_read_bounce()
418 rdlen = op->data.nbytes; in mtk_nor_read_bounce()
420 ret = mtk_nor_dma_exec(sp, op->addr.val, rdlen, sp->buffer_dma); in mtk_nor_read_bounce()
423 memcpy(op->data.buf.in, sp->buffer, op->data.nbytes); in mtk_nor_read_bounce()
436 dma_addr = dma_map_single(sp->dev, op->data.buf.in, in mtk_nor_read_dma()
437 op->data.nbytes, DMA_FROM_DEVICE); in mtk_nor_read_dma()
439 if (dma_mapping_error(sp->dev, dma_addr)) in mtk_nor_read_dma()
440 return -EINVAL; in mtk_nor_read_dma()
442 ret = mtk_nor_dma_exec(sp, op->addr.val, op->data.nbytes, dma_addr); in mtk_nor_read_dma()
444 dma_unmap_single(sp->dev, dma_addr, op->data.nbytes, DMA_FROM_DEVICE); in mtk_nor_read_dma()
451 u8 *buf = op->data.buf.in; in mtk_nor_read_pio()
456 buf[0] = readb(sp->base + MTK_NOR_REG_RDATA); in mtk_nor_read_pio()
465 if (!(sp->wbuf_en ^ on)) in mtk_nor_setup_write_buffer()
468 val = readl(sp->base + MTK_NOR_REG_CFG2); in mtk_nor_setup_write_buffer()
470 writel(val | MTK_NOR_WR_BUF_EN, sp->base + MTK_NOR_REG_CFG2); in mtk_nor_setup_write_buffer()
471 ret = readl_poll_timeout(sp->base + MTK_NOR_REG_CFG2, val, in mtk_nor_setup_write_buffer()
474 writel(val & ~MTK_NOR_WR_BUF_EN, sp->base + MTK_NOR_REG_CFG2); in mtk_nor_setup_write_buffer()
475 ret = readl_poll_timeout(sp->base + MTK_NOR_REG_CFG2, val, in mtk_nor_setup_write_buffer()
480 sp->wbuf_en = on; in mtk_nor_setup_write_buffer()
487 const u8 *buf = op->data.buf.out; in mtk_nor_pp_buffered()
495 for (i = 0; i < op->data.nbytes; i += 4) { in mtk_nor_pp_buffered()
498 writel(val, sp->base + MTK_NOR_REG_PP_DATA); in mtk_nor_pp_buffered()
501 (op->data.nbytes + 5) * BITS_PER_BYTE); in mtk_nor_pp_buffered()
507 const u8 *buf = op->data.buf.out; in mtk_nor_pp_unbuffered()
513 writeb(buf[0], sp->base + MTK_NOR_REG_WDATA); in mtk_nor_pp_unbuffered()
526 tx_len = op->cmd.nbytes + op->addr.nbytes; in mtk_nor_spi_mem_prg()
529 if (op->data.dir == SPI_MEM_DATA_OUT) in mtk_nor_spi_mem_prg()
530 tx_len += op->dummy.nbytes + op->data.nbytes; in mtk_nor_spi_mem_prg()
531 else if (op->data.dir == SPI_MEM_DATA_IN) in mtk_nor_spi_mem_prg()
532 rx_len = op->data.nbytes; in mtk_nor_spi_mem_prg()
534 prg_len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes + in mtk_nor_spi_mem_prg()
535 op->data.nbytes; in mtk_nor_spi_mem_prg()
538 // adjust_op_size. return -EINVAL instead of -ENOTSUPP so that in mtk_nor_spi_mem_prg()
539 // spi-mem won't try this op again with generic spi transfers. in mtk_nor_spi_mem_prg()
543 return -EINVAL; in mtk_nor_spi_mem_prg()
546 for (i = op->cmd.nbytes; i > 0; i--, reg_offset--) { in mtk_nor_spi_mem_prg()
547 reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset); in mtk_nor_spi_mem_prg()
548 bufbyte = (op->cmd.opcode >> ((i - 1) * BITS_PER_BYTE)) & 0xff; in mtk_nor_spi_mem_prg()
552 for (i = op->addr.nbytes; i > 0; i--, reg_offset--) { in mtk_nor_spi_mem_prg()
553 reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset); in mtk_nor_spi_mem_prg()
554 bufbyte = (op->addr.val >> ((i - 1) * BITS_PER_BYTE)) & 0xff; in mtk_nor_spi_mem_prg()
558 if (op->data.dir == SPI_MEM_DATA_OUT) { in mtk_nor_spi_mem_prg()
559 for (i = 0; i < op->dummy.nbytes; i++, reg_offset--) { in mtk_nor_spi_mem_prg()
560 reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset); in mtk_nor_spi_mem_prg()
564 for (i = 0; i < op->data.nbytes; i++, reg_offset--) { in mtk_nor_spi_mem_prg()
565 reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset); in mtk_nor_spi_mem_prg()
566 writeb(((const u8 *)(op->data.buf.out))[i], reg); in mtk_nor_spi_mem_prg()
570 for (; reg_offset >= 0; reg_offset--) { in mtk_nor_spi_mem_prg()
571 reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset); in mtk_nor_spi_mem_prg()
577 writel(prg_len * BITS_PER_BYTE + sp->caps->extra_dummy_bit, in mtk_nor_spi_mem_prg()
578 sp->base + MTK_NOR_REG_PRG_CNT); in mtk_nor_spi_mem_prg()
580 writel(prg_len * BITS_PER_BYTE, sp->base + MTK_NOR_REG_PRG_CNT); in mtk_nor_spi_mem_prg()
589 if (op->data.dir == SPI_MEM_DATA_IN) { in mtk_nor_spi_mem_prg()
590 for (i = op->data.nbytes - 1; i >= 0; i--, reg_offset++) { in mtk_nor_spi_mem_prg()
591 reg = sp->base + MTK_NOR_REG_SHIFT(reg_offset); in mtk_nor_spi_mem_prg()
592 ((u8 *)(op->data.buf.in))[i] = readb(reg); in mtk_nor_spi_mem_prg()
601 struct mtk_nor *sp = spi_controller_get_devdata(mem->spi->controller); in mtk_nor_exec_op()
604 if ((op->data.nbytes == 0) || in mtk_nor_exec_op()
605 ((op->addr.nbytes != 3) && (op->addr.nbytes != 4))) in mtk_nor_exec_op()
608 if (op->data.dir == SPI_MEM_DATA_OUT) { in mtk_nor_exec_op()
610 writeb(op->cmd.opcode, sp->base + MTK_NOR_REG_PRGDATA0); in mtk_nor_exec_op()
611 if (op->data.nbytes == MTK_NOR_PP_SIZE) in mtk_nor_exec_op()
616 if ((op->data.dir == SPI_MEM_DATA_IN) && mtk_nor_match_read(op)) { in mtk_nor_exec_op()
621 if (op->data.nbytes == 1) { in mtk_nor_exec_op()
640 static int mtk_nor_setup(struct spi_device *spi) in mtk_nor_setup() argument
642 struct mtk_nor *sp = spi_controller_get_devdata(spi->controller); in mtk_nor_setup()
644 if (spi->max_speed_hz && (spi->max_speed_hz < sp->spi_freq)) { in mtk_nor_setup()
645 dev_err(&spi->dev, "spi clock should be %u Hz.\n", in mtk_nor_setup()
646 sp->spi_freq); in mtk_nor_setup()
647 return -EINVAL; in mtk_nor_setup()
649 spi->max_speed_hz = sp->spi_freq; in mtk_nor_setup()
667 list_for_each_entry(t, &m->transfers, transfer_list) { in mtk_nor_transfer_one_message()
668 txbuf = t->tx_buf; in mtk_nor_transfer_one_message()
669 for (i = 0; i < t->len; i++, reg_offset--) { in mtk_nor_transfer_one_message()
670 reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset); in mtk_nor_transfer_one_message()
676 trx_len += t->len; in mtk_nor_transfer_one_message()
679 writel(trx_len * BITS_PER_BYTE, sp->base + MTK_NOR_REG_PRG_CNT); in mtk_nor_transfer_one_message()
686 reg_offset = trx_len - 1; in mtk_nor_transfer_one_message()
687 list_for_each_entry(t, &m->transfers, transfer_list) { in mtk_nor_transfer_one_message()
688 rxbuf = t->rx_buf; in mtk_nor_transfer_one_message()
689 for (i = 0; i < t->len; i++, reg_offset--) { in mtk_nor_transfer_one_message()
690 reg = sp->base + MTK_NOR_REG_SHIFT(reg_offset); in mtk_nor_transfer_one_message()
696 m->actual_length = trx_len; in mtk_nor_transfer_one_message()
698 m->status = stat; in mtk_nor_transfer_one_message()
706 clk_disable_unprepare(sp->spi_clk); in mtk_nor_disable_clk()
707 clk_disable_unprepare(sp->ctlr_clk); in mtk_nor_disable_clk()
708 clk_disable_unprepare(sp->axi_clk); in mtk_nor_disable_clk()
709 clk_disable_unprepare(sp->axi_s_clk); in mtk_nor_disable_clk()
716 ret = clk_prepare_enable(sp->spi_clk); in mtk_nor_enable_clk()
720 ret = clk_prepare_enable(sp->ctlr_clk); in mtk_nor_enable_clk()
722 clk_disable_unprepare(sp->spi_clk); in mtk_nor_enable_clk()
726 ret = clk_prepare_enable(sp->axi_clk); in mtk_nor_enable_clk()
728 clk_disable_unprepare(sp->spi_clk); in mtk_nor_enable_clk()
729 clk_disable_unprepare(sp->ctlr_clk); in mtk_nor_enable_clk()
733 ret = clk_prepare_enable(sp->axi_s_clk); in mtk_nor_enable_clk()
735 clk_disable_unprepare(sp->spi_clk); in mtk_nor_enable_clk()
736 clk_disable_unprepare(sp->ctlr_clk); in mtk_nor_enable_clk()
737 clk_disable_unprepare(sp->axi_clk); in mtk_nor_enable_clk()
746 writel(0, sp->base + MTK_NOR_REG_IRQ_EN); in mtk_nor_init()
747 writel(MTK_NOR_IRQ_MASK, sp->base + MTK_NOR_REG_IRQ_STAT); in mtk_nor_init()
749 writel(MTK_NOR_ENABLE_SF_CMD, sp->base + MTK_NOR_REG_WP); in mtk_nor_init()
760 irq_status = readl(sp->base + MTK_NOR_REG_IRQ_STAT); in mtk_nor_irq_handler()
761 irq_enabled = readl(sp->base + MTK_NOR_REG_IRQ_EN); in mtk_nor_irq_handler()
763 writel(irq_status, sp->base + MTK_NOR_REG_IRQ_STAT); in mtk_nor_irq_handler()
769 complete(&sp->op_done); in mtk_nor_irq_handler()
770 writel(0, sp->base + MTK_NOR_REG_IRQ_EN); in mtk_nor_irq_handler()
776 static size_t mtk_max_msg_size(struct spi_device *spi) in mtk_max_msg_size() argument
803 { .compatible = "mediatek,mt8173-nor", .data = &mtk_nor_caps_mt8173 },
804 { .compatible = "mediatek,mt8186-nor", .data = &mtk_nor_caps_mt8186 },
805 { .compatible = "mediatek,mt8192-nor", .data = &mtk_nor_caps_mt8192 },
816 struct clk *spi_clk, *ctlr_clk, *axi_clk, *axi_s_clk; in mtk_nor_probe()
823 spi_clk = devm_clk_get(&pdev->dev, "spi"); in mtk_nor_probe()
827 ctlr_clk = devm_clk_get(&pdev->dev, "sf"); in mtk_nor_probe()
831 axi_clk = devm_clk_get_optional(&pdev->dev, "axi"); in mtk_nor_probe()
835 axi_s_clk = devm_clk_get_optional(&pdev->dev, "axi_s"); in mtk_nor_probe()
839 caps = (struct mtk_nor_caps *)of_device_get_match_data(&pdev->dev); in mtk_nor_probe()
841 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(caps->dma_bits)); in mtk_nor_probe()
843 dev_err(&pdev->dev, "failed to set dma mask(%u)\n", caps->dma_bits); in mtk_nor_probe()
847 ctlr = devm_spi_alloc_host(&pdev->dev, sizeof(*sp)); in mtk_nor_probe()
849 dev_err(&pdev->dev, "failed to allocate spi controller\n"); in mtk_nor_probe()
850 return -ENOMEM; in mtk_nor_probe()
853 ctlr->bits_per_word_mask = SPI_BPW_MASK(8); in mtk_nor_probe()
854 ctlr->dev.of_node = pdev->dev.of_node; in mtk_nor_probe()
855 ctlr->max_message_size = mtk_max_msg_size; in mtk_nor_probe()
856 ctlr->mem_ops = &mtk_nor_mem_ops; in mtk_nor_probe()
857 ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD; in mtk_nor_probe()
858 ctlr->num_chipselect = 1; in mtk_nor_probe()
859 ctlr->setup = mtk_nor_setup; in mtk_nor_probe()
860 ctlr->transfer_one_message = mtk_nor_transfer_one_message; in mtk_nor_probe()
861 ctlr->auto_runtime_pm = true; in mtk_nor_probe()
863 dev_set_drvdata(&pdev->dev, ctlr); in mtk_nor_probe()
866 sp->base = base; in mtk_nor_probe()
867 sp->has_irq = false; in mtk_nor_probe()
868 sp->wbuf_en = false; in mtk_nor_probe()
869 sp->ctlr = ctlr; in mtk_nor_probe()
870 sp->dev = &pdev->dev; in mtk_nor_probe()
871 sp->spi_clk = spi_clk; in mtk_nor_probe()
872 sp->ctlr_clk = ctlr_clk; in mtk_nor_probe()
873 sp->axi_clk = axi_clk; in mtk_nor_probe()
874 sp->axi_s_clk = axi_s_clk; in mtk_nor_probe()
875 sp->caps = caps; in mtk_nor_probe()
876 sp->high_dma = caps->dma_bits > 32; in mtk_nor_probe()
877 sp->buffer = dmam_alloc_coherent(&pdev->dev, in mtk_nor_probe()
879 &sp->buffer_dma, GFP_KERNEL); in mtk_nor_probe()
880 if (!sp->buffer) in mtk_nor_probe()
881 return -ENOMEM; in mtk_nor_probe()
883 if ((uintptr_t)sp->buffer & MTK_NOR_DMA_ALIGN_MASK) { in mtk_nor_probe()
884 dev_err(sp->dev, "misaligned allocation of internal buffer.\n"); in mtk_nor_probe()
885 return -ENOMEM; in mtk_nor_probe()
892 sp->spi_freq = clk_get_rate(sp->spi_clk); in mtk_nor_probe()
899 dev_warn(sp->dev, "IRQ not available."); in mtk_nor_probe()
901 ret = devm_request_irq(sp->dev, irq, mtk_nor_irq_handler, 0, in mtk_nor_probe()
902 pdev->name, sp); in mtk_nor_probe()
904 dev_warn(sp->dev, "failed to request IRQ."); in mtk_nor_probe()
906 init_completion(&sp->op_done); in mtk_nor_probe()
907 sp->has_irq = true; in mtk_nor_probe()
911 pm_runtime_set_autosuspend_delay(&pdev->dev, -1); in mtk_nor_probe()
912 pm_runtime_use_autosuspend(&pdev->dev); in mtk_nor_probe()
913 pm_runtime_set_active(&pdev->dev); in mtk_nor_probe()
914 pm_runtime_enable(&pdev->dev); in mtk_nor_probe()
915 pm_runtime_get_noresume(&pdev->dev); in mtk_nor_probe()
917 ret = devm_spi_register_controller(&pdev->dev, ctlr); in mtk_nor_probe()
921 pm_runtime_mark_last_busy(&pdev->dev); in mtk_nor_probe()
922 pm_runtime_put_autosuspend(&pdev->dev); in mtk_nor_probe()
924 dev_info(&pdev->dev, "spi frequency: %d Hz\n", sp->spi_freq); in mtk_nor_probe()
929 pm_runtime_disable(&pdev->dev); in mtk_nor_probe()
930 pm_runtime_set_suspended(&pdev->dev); in mtk_nor_probe()
931 pm_runtime_dont_use_autosuspend(&pdev->dev); in mtk_nor_probe()
940 struct spi_controller *ctlr = dev_get_drvdata(&pdev->dev); in mtk_nor_remove()
943 pm_runtime_disable(&pdev->dev); in mtk_nor_remove()
944 pm_runtime_set_suspended(&pdev->dev); in mtk_nor_remove()
945 pm_runtime_dont_use_autosuspend(&pdev->dev); in mtk_nor_remove()
1006 MODULE_DESCRIPTION("Mediatek SPI NOR controller driver");