Lines Matching +full:- +full:spi
1 // SPDX-License-Identifier: (GPL-2.0)
3 * Microchip CoreSPI SPI controller driver
5 * Copyright (c) 2018-2022 Microchip Technology Inc. and its subsidiaries
21 #include <linux/spi/spi.h>
108 u32 clk_gen; /* divider for spi output clock generated by the controller */
117 static inline u32 mchp_corespi_read(struct mchp_corespi *spi, unsigned int reg) in mchp_corespi_read() argument
119 return readl(spi->regs + reg); in mchp_corespi_read()
122 static inline void mchp_corespi_write(struct mchp_corespi *spi, unsigned int reg, u32 val) in mchp_corespi_write() argument
124 writel(val, spi->regs + reg); in mchp_corespi_write()
127 static inline void mchp_corespi_disable(struct mchp_corespi *spi) in mchp_corespi_disable() argument
129 u32 control = mchp_corespi_read(spi, REG_CONTROL); in mchp_corespi_disable()
133 mchp_corespi_write(spi, REG_CONTROL, control); in mchp_corespi_disable()
136 static inline void mchp_corespi_read_fifo(struct mchp_corespi *spi) in mchp_corespi_read_fifo() argument
138 …while (spi->rx_len >= spi->n_bytes && !(mchp_corespi_read(spi, REG_STATUS) & STATUS_RXFIFO_EMPTY))… in mchp_corespi_read_fifo()
139 u32 data = mchp_corespi_read(spi, REG_RX_DATA); in mchp_corespi_read_fifo()
141 spi->rx_len -= spi->n_bytes; in mchp_corespi_read_fifo()
143 if (!spi->rx_buf) in mchp_corespi_read_fifo()
146 if (spi->n_bytes == 4) in mchp_corespi_read_fifo()
147 *((u32 *)spi->rx_buf) = data; in mchp_corespi_read_fifo()
148 else if (spi->n_bytes == 2) in mchp_corespi_read_fifo()
149 *((u16 *)spi->rx_buf) = data; in mchp_corespi_read_fifo()
151 *spi->rx_buf = data; in mchp_corespi_read_fifo()
153 spi->rx_buf += spi->n_bytes; in mchp_corespi_read_fifo()
157 static void mchp_corespi_enable_ints(struct mchp_corespi *spi) in mchp_corespi_enable_ints() argument
159 u32 control = mchp_corespi_read(spi, REG_CONTROL); in mchp_corespi_enable_ints()
162 mchp_corespi_write(spi, REG_CONTROL, control); in mchp_corespi_enable_ints()
165 static void mchp_corespi_disable_ints(struct mchp_corespi *spi) in mchp_corespi_disable_ints() argument
167 u32 control = mchp_corespi_read(spi, REG_CONTROL); in mchp_corespi_disable_ints()
170 mchp_corespi_write(spi, REG_CONTROL, control); in mchp_corespi_disable_ints()
173 static inline void mchp_corespi_set_xfer_size(struct mchp_corespi *spi, int len) in mchp_corespi_set_xfer_size() argument
177 u32 frames = mchp_corespi_read(spi, REG_FRAMESUP); in mchp_corespi_set_xfer_size()
184 mchp_corespi_write(spi, REG_COMMAND, COMMAND_CLRFRAMECNT); in mchp_corespi_set_xfer_size()
200 * would actually write zeros into the lower 16 bits on an mpfs250t-es, in mchp_corespi_set_xfer_size()
201 * despite documentation stating these bits were read-only. in mchp_corespi_set_xfer_size()
203 * on an mpfs250t-es and will be a NOP for the lower 16 bits on hardware in mchp_corespi_set_xfer_size()
207 control = mchp_corespi_read(spi, REG_CONTROL); in mchp_corespi_set_xfer_size()
210 mchp_corespi_write(spi, REG_CONTROL, control); in mchp_corespi_set_xfer_size()
211 mchp_corespi_write(spi, REG_FRAMESUP, len); in mchp_corespi_set_xfer_size()
214 static inline void mchp_corespi_write_fifo(struct mchp_corespi *spi) in mchp_corespi_write_fifo() argument
218 fifo_max = DIV_ROUND_UP(min(spi->tx_len, FIFO_DEPTH), spi->n_bytes); in mchp_corespi_write_fifo()
219 mchp_corespi_set_xfer_size(spi, fifo_max); in mchp_corespi_write_fifo()
221 while ((i < fifo_max) && !(mchp_corespi_read(spi, REG_STATUS) & STATUS_TXFIFO_FULL)) { in mchp_corespi_write_fifo()
224 if (spi->n_bytes == 4) in mchp_corespi_write_fifo()
225 word = spi->tx_buf ? *((u32 *)spi->tx_buf) : 0xaa; in mchp_corespi_write_fifo()
226 else if (spi->n_bytes == 2) in mchp_corespi_write_fifo()
227 word = spi->tx_buf ? *((u16 *)spi->tx_buf) : 0xaa; in mchp_corespi_write_fifo()
229 word = spi->tx_buf ? *spi->tx_buf : 0xaa; in mchp_corespi_write_fifo()
231 mchp_corespi_write(spi, REG_TX_DATA, word); in mchp_corespi_write_fifo()
232 if (spi->tx_buf) in mchp_corespi_write_fifo()
233 spi->tx_buf += spi->n_bytes; in mchp_corespi_write_fifo()
237 spi->tx_len -= i * spi->n_bytes; in mchp_corespi_write_fifo()
240 static inline void mchp_corespi_set_framesize(struct mchp_corespi *spi, int bt) in mchp_corespi_set_framesize() argument
242 u32 frame_size = mchp_corespi_read(spi, REG_FRAME_SIZE); in mchp_corespi_set_framesize()
249 * Disable the SPI controller. Writes to the frame size have in mchp_corespi_set_framesize()
252 control = mchp_corespi_read(spi, REG_CONTROL); in mchp_corespi_set_framesize()
254 mchp_corespi_write(spi, REG_CONTROL, control); in mchp_corespi_set_framesize()
256 mchp_corespi_write(spi, REG_FRAME_SIZE, bt); in mchp_corespi_set_framesize()
259 mchp_corespi_write(spi, REG_CONTROL, control); in mchp_corespi_set_framesize()
262 static void mchp_corespi_set_cs(struct spi_device *spi, bool disable) in mchp_corespi_set_cs() argument
265 struct mchp_corespi *corespi = spi_controller_get_devdata(spi->controller); in mchp_corespi_set_cs()
268 reg &= ~BIT(spi_get_chipselect(spi, 0)); in mchp_corespi_set_cs()
269 reg |= !disable << spi_get_chipselect(spi, 0); in mchp_corespi_set_cs()
270 corespi->pending_slave_select = reg; in mchp_corespi_set_cs()
280 if (((spi->mode & SPI_CS_HIGH) == 0) == disable) in mchp_corespi_set_cs()
284 static int mchp_corespi_setup(struct spi_device *spi) in mchp_corespi_setup() argument
286 struct mchp_corespi *corespi = spi_controller_get_devdata(spi->controller); in mchp_corespi_setup()
289 if (spi_is_csgpiod(spi)) in mchp_corespi_setup()
297 if (spi->mode & SPI_CS_HIGH) { in mchp_corespi_setup()
299 reg |= BIT(spi_get_chipselect(spi, 0)); in mchp_corespi_setup()
300 corespi->pending_slave_select = reg; in mchp_corespi_setup()
306 static void mchp_corespi_init(struct spi_controller *host, struct mchp_corespi *spi) in mchp_corespi_init() argument
309 u32 control = mchp_corespi_read(spi, REG_CONTROL); in mchp_corespi_init()
312 mchp_corespi_write(spi, REG_CONTROL, control); in mchp_corespi_init()
328 mchp_corespi_write(spi, REG_CONTROL, control); in mchp_corespi_init()
330 mchp_corespi_set_framesize(spi, DEFAULT_FRAMESIZE); in mchp_corespi_init()
332 /* max. possible spi clock rate is the apb clock rate */ in mchp_corespi_init()
333 clk_hz = clk_get_rate(spi->clk); in mchp_corespi_init()
334 host->max_speed_hz = clk_hz; in mchp_corespi_init()
336 mchp_corespi_enable_ints(spi); in mchp_corespi_init()
343 spi->pending_slave_select = SSELOUT | SSEL_DIRECT; in mchp_corespi_init()
344 mchp_corespi_write(spi, REG_SLAVE_SELECT, spi->pending_slave_select); in mchp_corespi_init()
346 control = mchp_corespi_read(spi, REG_CONTROL); in mchp_corespi_init()
351 mchp_corespi_write(spi, REG_CONTROL, control); in mchp_corespi_init()
354 static inline void mchp_corespi_set_clk_gen(struct mchp_corespi *spi) in mchp_corespi_set_clk_gen() argument
358 control = mchp_corespi_read(spi, REG_CONTROL); in mchp_corespi_set_clk_gen()
359 if (spi->clk_mode) in mchp_corespi_set_clk_gen()
364 mchp_corespi_write(spi, REG_CLK_GEN, spi->clk_gen); in mchp_corespi_set_clk_gen()
365 mchp_corespi_write(spi, REG_CONTROL, control); in mchp_corespi_set_clk_gen()
368 static inline void mchp_corespi_set_mode(struct mchp_corespi *spi, unsigned int mode) in mchp_corespi_set_mode() argument
371 u32 control = mchp_corespi_read(spi, REG_CONTROL); in mchp_corespi_set_mode()
389 * Disable the SPI controller. Writes to the frame protocol have in mchp_corespi_set_mode()
394 mchp_corespi_write(spi, REG_CONTROL, control); in mchp_corespi_set_mode()
399 mchp_corespi_write(spi, REG_CONTROL, control); in mchp_corespi_set_mode()
402 mchp_corespi_write(spi, REG_CONTROL, control); in mchp_corespi_set_mode()
408 struct mchp_corespi *spi = spi_controller_get_devdata(host); in mchp_corespi_interrupt() local
409 u32 intfield = mchp_corespi_read(spi, REG_MIS) & 0xf; in mchp_corespi_interrupt()
417 mchp_corespi_write(spi, REG_INT_CLEAR, INT_TXDONE); in mchp_corespi_interrupt()
420 mchp_corespi_write(spi, REG_INT_CLEAR, INT_RXRDY); in mchp_corespi_interrupt()
422 if (spi->rx_len) in mchp_corespi_interrupt()
423 mchp_corespi_read_fifo(spi); in mchp_corespi_interrupt()
426 if (!spi->rx_len && !spi->tx_len) in mchp_corespi_interrupt()
430 mchp_corespi_write(spi, REG_INT_CLEAR, INT_RX_CHANNEL_OVERFLOW); in mchp_corespi_interrupt()
432 dev_err(&host->dev, in mchp_corespi_interrupt()
434 spi->rx_len, spi->tx_len); in mchp_corespi_interrupt()
438 mchp_corespi_write(spi, REG_INT_CLEAR, INT_TX_CHANNEL_UNDERRUN); in mchp_corespi_interrupt()
440 dev_err(&host->dev, in mchp_corespi_interrupt()
442 spi->rx_len, spi->tx_len); in mchp_corespi_interrupt()
451 static int mchp_corespi_calculate_clkgen(struct mchp_corespi *spi, in mchp_corespi_calculate_clkgen() argument
456 clk_hz = clk_get_rate(spi->clk); in mchp_corespi_calculate_clkgen()
458 return -EINVAL; in mchp_corespi_calculate_clkgen()
471 clk_gen = DIV_ROUND_UP(clk_hz, 2 * spi_hz) - 1; in mchp_corespi_calculate_clkgen()
474 clk_gen = fls(clk_gen) - 1; in mchp_corespi_calculate_clkgen()
477 return -EINVAL; in mchp_corespi_calculate_clkgen()
479 spi->clk_mode = 0; in mchp_corespi_calculate_clkgen()
481 spi->clk_mode = 1; in mchp_corespi_calculate_clkgen()
484 spi->clk_gen = clk_gen; in mchp_corespi_calculate_clkgen()
492 struct mchp_corespi *spi = spi_controller_get_devdata(host); in mchp_corespi_transfer_one() local
495 ret = mchp_corespi_calculate_clkgen(spi, (unsigned long)xfer->speed_hz); in mchp_corespi_transfer_one()
497 dev_err(&host->dev, "failed to set clk_gen for target %u Hz\n", xfer->speed_hz); in mchp_corespi_transfer_one()
501 mchp_corespi_set_clk_gen(spi); in mchp_corespi_transfer_one()
503 spi->tx_buf = xfer->tx_buf; in mchp_corespi_transfer_one()
504 spi->rx_buf = xfer->rx_buf; in mchp_corespi_transfer_one()
505 spi->tx_len = xfer->len; in mchp_corespi_transfer_one()
506 spi->rx_len = xfer->len; in mchp_corespi_transfer_one()
507 spi->n_bytes = roundup_pow_of_two(DIV_ROUND_UP(xfer->bits_per_word, BITS_PER_BYTE)); in mchp_corespi_transfer_one()
509 mchp_corespi_set_framesize(spi, xfer->bits_per_word); in mchp_corespi_transfer_one()
511 mchp_corespi_write(spi, REG_COMMAND, COMMAND_RXFIFORST | COMMAND_TXFIFORST); in mchp_corespi_transfer_one()
513 mchp_corespi_write(spi, REG_SLAVE_SELECT, spi->pending_slave_select); in mchp_corespi_transfer_one()
515 while (spi->tx_len) in mchp_corespi_transfer_one()
516 mchp_corespi_write_fifo(spi); in mchp_corespi_transfer_one()
524 struct spi_device *spi_dev = msg->spi; in mchp_corespi_prepare_message()
525 struct mchp_corespi *spi = spi_controller_get_devdata(host); in mchp_corespi_prepare_message() local
527 mchp_corespi_set_mode(spi, spi_dev->mode); in mchp_corespi_prepare_message()
535 struct mchp_corespi *spi; in mchp_corespi_probe() local
540 host = devm_spi_alloc_host(&pdev->dev, sizeof(*spi)); in mchp_corespi_probe()
542 return dev_err_probe(&pdev->dev, -ENOMEM, in mchp_corespi_probe()
543 "unable to allocate host for SPI controller\n"); in mchp_corespi_probe()
547 if (of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs)) in mchp_corespi_probe()
550 host->num_chipselect = num_cs; in mchp_corespi_probe()
551 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; in mchp_corespi_probe()
552 host->use_gpio_descriptors = true; in mchp_corespi_probe()
553 host->setup = mchp_corespi_setup; in mchp_corespi_probe()
554 host->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); in mchp_corespi_probe()
555 host->transfer_one = mchp_corespi_transfer_one; in mchp_corespi_probe()
556 host->prepare_message = mchp_corespi_prepare_message; in mchp_corespi_probe()
557 host->set_cs = mchp_corespi_set_cs; in mchp_corespi_probe()
558 host->dev.of_node = pdev->dev.of_node; in mchp_corespi_probe()
560 spi = spi_controller_get_devdata(host); in mchp_corespi_probe()
562 spi->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in mchp_corespi_probe()
563 if (IS_ERR(spi->regs)) in mchp_corespi_probe()
564 return PTR_ERR(spi->regs); in mchp_corespi_probe()
566 spi->irq = platform_get_irq(pdev, 0); in mchp_corespi_probe()
567 if (spi->irq < 0) in mchp_corespi_probe()
568 return spi->irq; in mchp_corespi_probe()
570 ret = devm_request_irq(&pdev->dev, spi->irq, mchp_corespi_interrupt, in mchp_corespi_probe()
571 IRQF_SHARED, dev_name(&pdev->dev), host); in mchp_corespi_probe()
573 return dev_err_probe(&pdev->dev, ret, in mchp_corespi_probe()
576 spi->clk = devm_clk_get_enabled(&pdev->dev, NULL); in mchp_corespi_probe()
577 if (IS_ERR(spi->clk)) in mchp_corespi_probe()
578 return dev_err_probe(&pdev->dev, PTR_ERR(spi->clk), in mchp_corespi_probe()
581 mchp_corespi_init(host, spi); in mchp_corespi_probe()
583 ret = devm_spi_register_controller(&pdev->dev, host); in mchp_corespi_probe()
585 mchp_corespi_disable(spi); in mchp_corespi_probe()
586 return dev_err_probe(&pdev->dev, ret, in mchp_corespi_probe()
587 "unable to register host for SPI controller\n"); in mchp_corespi_probe()
590 dev_info(&pdev->dev, "Registered SPI controller %d\n", host->bus_num); in mchp_corespi_probe()
598 struct mchp_corespi *spi = spi_controller_get_devdata(host); in mchp_corespi_remove() local
600 mchp_corespi_disable_ints(spi); in mchp_corespi_remove()
601 mchp_corespi_disable(spi); in mchp_corespi_remove()
612 { .compatible = "microchip,mpfs-spi" },
621 .name = "microchip-corespi",
628 MODULE_DESCRIPTION("Microchip coreSPI SPI controller driver");